igneum-labs 7784bdc7d1 chip-model: shadow-k collector, mix optimiser, edge rows; the report's method sections ... Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com> Documents-only replay of 6fab785c5 (bfccc26ed4) for the box mirror master		2026-10-08 14:32:43 +00:00
..
denominator.md	Class v6 floor lane 4: the sweep closed (20 rows, the 4060 Ti's class v5 stock row, the three cards not reached), sections 2, 6 and 8 regenerated; 10 of 10 on build-3	2026-10-08 13:41:15 +00:00
invention.md	Class v6 floor lane 5 (invention): the knee row from PC 1 (the hash lane, kit d): at the 1,300 lock the hinted w64 form reads 37.6 against the 4-byte row's 100.6 MH/s at 2.3x the energy per hash, so W = 16 is dead at the knee as at stock; every row this lane owed on W = 16 is closed	2026-10-08 14:05:41 +00:00
shadow-k.md	chip-model: shadow-k collector, mix optimiser, edge rows; the report's method sections	2026-10-08 14:32:43 +00:00
sm-sparse.md	Class v6 floor lane 1: sm-sparse.md, the PC 1 table deduplicated (the job's five-minute uploads repeat earlier lines)	2026-10-08 13:49:30 +00:00
sram-and-floor.md	Class v6 floor lane 3: the close is 15:45 UK (the founder's rule of 13:3x); the four clock references updated, later rows as amendments	2026-10-08 12:29:15 +00:00