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Counter ASIC 3.0: status

Started 6 October 2026, 07:15 UTC, on the founder's order "run it all"; closed 09:5x UTC with every item measured on the Mac and the 5090 and every AMD row owed (PC 1 not released). Final tree: ca3-coord, 45 commits over the base, no-conflict-markers.sh clean, observer tests 10 of 10, igneum-pow 96 of 96 with the pinned v2 and v3 packs byte for byte. Coordinator worktree igneum-wt-ca3-coord, branch ca3-coord from 50df751 (ca2-coord 9206aea merged with master ddfcdac). The plan: docs/plans/counter-asic-3.md. The audit behind it: docs/analysis/asic-resistance-history.md. The 2.0 record: docs/plans/counter-asic-2-status.md, docs/bench-log.md "Counter ASIC 2.0, the numbers", docs/analysis/chip-model-v3.md. Class v3 is live on the devnet since DAA 154,800 (crossing 03:51:42Z, verdict PASS 05:21:48Z). Nothing in this run publishes to the devnet; what passes is a class v4 candidate behind program_class_v4_activation_daa under the six gates and the two-publish rollout of 2.0.

The test every result is judged against (the founder, 6 October): a chip maker must have to build a better GPU than NVIDIA to launch an ASIC, the way Bitmain's Antminer X5 reached CPU parity per joule only at many times the price. The binding rule from 2.0: the hash stays bound by dependent random memory reads.

1. Machines and rules in force today

Machine State Rule
Mac M5 Max mining paused; Metal worker free measurements under with-lock.sh measure only
PC 2 (1ccfe586, RTX 5090) HELD for the 0.3.14 shipper's Rust suite from 17:5x UK (main): nothing of 3.0 goes to PC 2 until the shipper reports the suite done (the P2 G6 run waits on it). Earlier: RELEASED at 08:43:24Z after the three jobs (derive 08:26 to 08:29Z, shadow 08:29 to 08:41Z, family 08:41 to 08:43Z, all exit 0; prover ON, app untouched); then the prover-floor agent, then the 0.3.12 release engineer's build. Before that: CLEAR at 08:24:27Z (the clear file carries the proving agent's constraints: prover left ON, no quit or restart, /opt/igneum, /opt/igneum-segal and settings.json untouched); the three 3.0 jobs run one at a time through the mkdir lock (items 8, 2, 6); "PC 2 released" to the proving agent after the last; the prover-floor agent next. Before that: the proving agent's jobs segments-pc2-pv1 runs b and c (run b claimed nothing on a PowerShell key bug; run c from about 07:53Z); "PC 2 clear" expected about 08:35Z; then three 3.0 jobs one at a time (items 2, 6, 8); the prover-floor agent queues after "PC 2 released" nothing published until "PC 2 clear"; one job at a time (/tmp/igneum-devnet/pc2-ca3.lock); released by message when done
PC 1 (ae432dc7, RTX 5090 + RTX 4070 + RX 9070 XT) FREE at 18:01:05Z after the queue (reset, family runs a to e, G2, derive, the 4070 ladder, the watts job that failed and left the 9070 XT off, the restore and the flag job); handed to main for the founder's 0.3.14 click and the Ember window. Earlier: the founder's desk; the AMD queue opens on "Ember closed" (reset, family, G2, derive, the 4070, watts, about 25 min), then the Ember agent's 6-minute window, then the 0.3.14 update on the founder's click (after the last job, not between jobs: an update wipes the jobs folder and the kits) not used today; every AMD row OWED

Standing rule from main (17:5x UTC; CLAUDE.md on master 630b537, docs/plans/build-server.md): from the next build, every Linux and Windows cargo build and every Linux test suite from the 3.0 lanes runs on igneum-build-1 through tools/build-remote.sh and tools/cross-remote.sh from the worktree's crate directory (artefacts in target-remote/, IGNEUM_AGENT=ca3-<lane>, one slot, a 2 h cap; the clean node build 87 s there against 9 to 18 min on the Mac). PC 2 keeps only GPU and Windows-runtime jobs (G6's engine test on the card stays a PC job; the crate suites move). Passed to the node lane, the hash lane and the PC 1 worker.

2. The items

# Item Worker branch State Close
1 Partial-store chip and the time-memory curve ca3-analysis CLOSED, merged (71df794) verdict OVER 2x: the f = 1 chip (the dataset stored in DRAM, nothing recomputed) is 5.1x per joule on GDDR7 and 7.5x to 9.2x on HBM3 in the model, 2.1x to 4.8x by the Ethash precedent, $2.8 per MH/s against the 5090's $14.7; the curve is monotone toward f = 1, so the partial-store chip is never built; the mixer and item 2 do not touch it; chip-model-v3.md section 5
2 Per-day item-derivation program (reserve entry, verifier gate, daily build) ca3-derive CLOSED, merged (acb96ee, dd5041b, bdc07d3, 54bc188); 5090 job run-ca3-derive-pc2-20261006 exit 0 in 126 s GO as reserve R0; NO-GO for genesis-live at dr736 (verifier 4.9 ms per unit on one M5 Max core, about 12 ms on a 2019-class core by the 2.5x rule, over the gate; dr368 2.69 ms passes both); urgency LOW after item 1 (the stored-dataset chip derives no item)
4 + 5 Share-pattern detector, trigger rules, FPGA lane, layer 9 against 7 ca3-detector CLOSED, merged (c0642af, merge ed06814) detector.mjs + 7 of 7 tests + one observer hook, dry run quiet on the devnet (max correlation 0.53 against the 0.8 edge; excess spread 0 to 5.2 percent); funding.md rule 5: bounty escrowed and benchmark live before daily issuance crosses USD 20,000 a day; epoch-length.md sections 11 and 12: signal trigger M = 6 windows; FPGA soft overlay 0.30x to 0.39x per watt on the measured basis, 0.7x to 1.9x at the bank-bound ceiling (unmeasured); layer 9 ranks above layer 7. The live observer is NOT restarted yet: the write path is untested; one restart after item 7's hook merges, then the first live detector row is recorded here
3 Cryptanalysis brief in funding.md ca3-crypto-brief CLOSED, merged (43c3ead) funding.md line item USD 80k to 160k, reviewer shortlist, ranked break list; verdict GO to commission (no outreach, no spend)
6 + 7 Reserve order with step costs, vendor-share metric ca3-reserve CLOSED, merged (b85f0f1, merge 820f4d4); 5090 job run-ca3-family-pc2-20261006 exit 0 in 36 s, the card to itself proposed reserve order R1 byte permute, R2 popcount and clz, R3 indexed shuffle, R4 bit-field extract, R5 variable shifts, R6 select, R7 andn, R8 mm8 (docs/plans/counter-asic-3-reserve.md, a decision for the founder, not in the spec); vendor-share.mjs with tests and one observer hook; repro.md carried from repro-bench (dda9fa3) with section 8: today's devnet NVIDIA 0.986 of blue blocks, Intel 0.014, coverage 1.00 at 135.8 MH/s with PC 1 off
8 (added by item 1's finding, coordinator 08:xx UTC) Program work in the latency shadow: the hash rate, watts and verifier cost at N = 50,000, 100,000, 200,000 ops per hash on the M5 Max and the 5090; the 5090 power-cap rows ca3-shadow CLOSED, merged (70eaf06, merge 12d8a93); 5090 job run-ca3-shadow-pc2-20261006 (lock 08:29:22 to 08:41:03Z), the card empty GO as a class v4 candidate at mx8+sh256x27 (100,000 ops per hash): the chip's per-joule edge over the 5090 falls from 5.6x to 2.1x at k = 1 for 0.2 percent of the 5090's rate and 1.5 percent of the Mac's; NO-GO above 130,000 ops or a block over 256 instructions; the chip question is decided by k, the chip core's energy per op against the 5090's measured 11 pJ: over 2x only at k under 0.5

3. Measured numbers

Item 1 (analysis, no new measurement; every chip figure is arithmetic on cited memory figures, approximate where marked)

Row Rate against the 5090's 136.1 MH/s Per joule against 2.40 microjoules per hash $ per MH/s Binding
f = 0 on-die recompute chip (sections 1 to 3; 9,360 ops per item hoisted, 10,512 unhoisted) 0.31x bare, 0.92x with the 3x factor (0.27x / 0.82x unhoisted) 1.86x (1.75x unhoisted; 1.3x to 2.4x over the on-die read energy) $16.8 compute
f = 1 on GDDR7 (the 5090's own memory system, 21.3 G reads/s activate ceiling) 1.22x 5.1x $2.8 memory
f = 1 on one HBM3 stack 0.61x 7.5x $6.6 memory
f = 1 on eight HBM3 stacks 4.9x 9.2x $4.0 memory
f = 0.25 to 0.75, both memories between the ends and worse than both on $ per MH/s

The whole case for the f = 1 chip: the 5090's memory system draws about 55 W of its 326 at the hash (17 percent, approximate); the rest is the GPU spinning on loads at 0.15 percent of its integer budget. The op count per mixer application, counted from memhard.rs: 144 as written, 128 with the RC and rk adds hoisted; 72 x 128 + 144 = 9,360 per item, which is the spec's "about 130" x 72 exactly; the chip model's rows stand at 9,360 and are given at 10,512 beside them.

What moves the f = 1 rows (chip-model-v3.md section 5.7): not the dataset size (one HBM3 stack holds 24 GB, the schedule reaches 4 GiB at year 4), not the read width (the decision to stay at 4 B stands), not the chain length; only (a) the honest card's watts at the hash (a 5090 holding 136 MH/s at a 250 W cap reads 3.9x on GDDR7, at 200 W 3.2x) and (b) program work in the latency shadow (the card hides 512 ops per hash behind 128 reads and could hide about 330,000 before compute binds; at N = 330,000 the model reads 1.85x at a chip core as efficient as the GPU's ALU, 2.5x at 1.5x worse), which is the design item this run adds (item 8 below) and the one that answers the founder's test directly: a chip must carry the memory system AND the ALU budget.

Item 2, the Mac rows (interim, ca3-derive dd5041b; measure lock, load average 4.5 to 5.3; the 5090 rows queued on PC 2; the 9070 XT OWED)

Class Ops per item (chip, RC + rk hoisted / GPU as written / multiplies) Verifier ms per unit, one M5 Max core (worst cold) 2019-class core, 2.5x rule, approximate Metal 1 GiB build Hash rate, M5 Max Bit-exact Chip row (bare / at a 1.2x / 1.5x allowance; the 3x no longer applies)
v2 (x1) 1,152 / 1,296 / 144 0.598 1.5 2.45x
v3 (x8), live 9,216 / 10,368 / 1,152 (the acceptance floors) 2.061 to 2.063 5.2 22.1 ms 27.1 MH/s yes 0.31x / 0.92x with the 3x factor
dr368 (9 x 368 instructions) about half of dr736 2.69 6.7, passes
dr736 (9 x 736 instructions, the genesis-day draw: 9,992 / 10,659 / 1,461) 4.875 to 4.944 (5.241) 12, over the gate 29.0 ms 27.1 MH/s (equal) yes (Metal and Apple OpenCL, fingerprint 50e3eaa779da4f1e) 0.29x / 0.34x / 0.43x

Verifier headroom under the 10 ms gate (bdc07d3, the budget item 8's shadow ops may spend; steady / worst cold): on this M5 Max core x8 7.9 / 7.8 ms, dr368 7.3 / 7.1, dr736 5.1 / 4.8; on the approximate 2019-class core x8 4.8 / 4.6, dr368 3.3 / 2.8, dr736 none (over by 2.2 / 3.1). cargo test -p igneum-pow on acb96ee under the build lock: 95 passed, 0 failed; the pinned v2 and v3 packs regenerate byte for byte.

The 5090 rows (job run-ca3-derive-pc2-20261006, 08:26:43 to 08:28:49Z, exit 0; the card was LOADED: the miner stayed up because the job posted the settings key without the device index, see corrections; ratios valid, absolutes not): bit-exact on CUDA for both dr736 packs (64 samples, 96 lanes, fingerprints 50e3eaa779da4f1e and 9553f6d5c667205a equal to the Mac's); 1 GiB build 42 / 32 ms against x8 40 and v2 46; rates 61 to 62 MH/s on every pack (the v2 control 62.3 against 136 unloaded); NVRTC compile 1,266 ms against x8's 164 ms, +1.1 s per pack because memhard.h's item function sits inside every hash-kernel and race-variant compile, so a once-a-day derivation module is a requirement of the class, not an option. Prover left ON, app untouched.

The RX 9070 XT rows (PC 1 job run-ca3-pc1-amd-derive-20261006, 17:23:56 to 17:29:13Z, exit 0, beside the miners so the absolutes are loaded-card figures and the ratios stand): bit-exact on AMD OpenCL for both dr736 packs (fingerprints 9553f6d5c667205a and 50e3eaa779da4f1e equal to the Mac's and the 5090's, two passes each, self-tests PASS); the OpenCL compile 2,070 to 2,092 ms per dr736 pack against 41 ms for mx8 (+2.0 s per pack, the AMD twin of NVRTC's +1.1 s: the once-a-day derivation module is a requirement on every vendor, and on a one-click AMD miner the shadow-free x8 pack compiles in 0.04 s where the derivation pack takes 2.1); the 1 GiB daily build 168 to 189 ms against 205 to 273 for mx8 in the same loaded session (a build the same size or smaller, inside the noise); the rate ratio to mx8 0.982 and 1.006 (no hash-rate cost). With these the derivation's bit-exactness is on all three vendors and its hash-rate cost is zero on all three.

Consequence: the derivation costs no hash rate on any card and 7 ms a day of build on the Mac (29 against 22 ms; the 5090 and the 9070 XT rows owed, the loaded-iGPU tier is the one to watch); it costs the verifier, and the verifier budget is shared with item 8's shadow ops under the one 10 ms gate, so the class v4 candidate is the pairing that fits, not either lever alone (both workers told).

Item 8, the Mac rows (interim, ca3-shadow a050a54; knob d4b7300; docs/analysis/latency-shadow-2026-10-06.md; Metal packbench, IOReport GPU + DRAM watts without root; the 5090 rows queued on PC 2; the 9070 XT OWED)

N, shadow ops per hash M5 Max MH/s (against the control 27.07 to 27.10) Watts (GPU + DRAM) Microjoules per hash Verifier per warp, one M5 Max core Reading
512 (class v3 today) 27.1 21 0.78 2.06 ms the honest best per joule we own: 3x better than the 5090's 2.34 at 290 W
about 100,000 -1.5 percent 37 1.40 2.06 + 0.32 still latency-bound
about 130,000 -5 percent the 2.0 rule's edge on this card
151,000 -7.3 percent
200,000 -10 percent compute binds
331,000 -21 percent 40 1.88 2.06 + 0.56 (about 1.4 ms more on a 2019-class core)

The verifier is not the constraint: 3.2 microseconds per 1,000 shadow instructions per warp, so no pairing of item 2's class with any N binds the gate before the cards do; the cards bind. Block size on Apple: a 64-instruction block +2.5 percent, 256 holds, 1,024 costs 17 percent at the same N. Marginal ALU energy on the Mac 6.9 pJ per counted op at N = 100,000. Chip side at N = 100,000 and a chip core equal to the GPU's ALU (k = 1): 1.4x over the M5 Max per joule, 2.7x over the 5090 on the model watts (5.0x today at 290 W with the shadow empty); k decides it. Power caps: the 5 October sweep re-used (floor 400 W, the cap never binds), no -pl steps; the PC 2 job carries the N ladder and -lgc clock rows at the four Ember caps (OWED if refused).

Consequence per tier (interim): the M5 Max at 21 W is the per-joule best honest miner we own (0.78 against the 5090's 2.34 microjoules), so against Apple silicon the stored-dataset chip of item 1 reads 1.7x per joule on GDDR7 (0.47 against 0.78) and 2.4x on one HBM3 stack, inside the "1 to 2x" band on GDDR7; per pound the Mac stays the worst tier (list price against 27 MH/s). Filling the shadow to about 100,000 ops costs an Apple miner 16 W more for 1.5 percent of rate (0.78 to 1.40 microjoules) and buys 1.4x against a chip at k = 1; the N the project can pick without any card we own losing over 5 percent is set by the Mac at about 130,000 until the 5090 and 9070 XT rows land. An NVIDIA owner's number is the PC 2 job; an AMD owner's is owed.

Item 8, the 5090 rows and the chip side (ca3-shadow 70eaf06; job run-ca3-shadow-pc2-20261006, the card confirmed empty by nvidia-smi compute-apps and the process list, the installed worker's --bench, nvidia-smi at 1 Hz, the app's 431 W cap; every pack bit-exact on Metal, CUDA, clang emulation and Apple OpenCL)

N ops per hash M5 Max MH/s (delta) M5 Max W, microjoules RTX 5090 MH/s (delta) 5090 W, SM MHz, microjoules Verifier ms per warp, one M5 Max core
930 (class v3 today: 512 instructions, 384 ALU, about 1.83 counted ops each) 27.08 21.0, 0.78 132.2 350, 3,040, 2.65 2.06
49,700 26.75 (-1.2%; a 64-instruction block +2.5%) 31.1, 1.16 132.3 (+0.1%; 64-block +3.5%) 425, 3,034, 3.21 2.21
102,100 (sh256x27, the candidate) 26.67 (-1.5%) 37.2, 1.40 131.95 (-0.2%) 431 cap, 2,824, 3.27 2.23
150,800 25.10 (-7.3%) 36.7, 1.46 131.75 (-0.3%) 431, 2,427, 3.27 2.33
199,600 24.25 (-10.4%) 38.2, 1.58 128.67 (-2.7%) 431, 1,753, 3.35 2.43
330,700 21.39 (-21%) 40.1, 1.88 86.39 (-35%, compute-bound at the capped clock, 28.6 T op/s) 431, 1,834, 4.99 2.62 (worst cold 2.77)

Where each card leaves the latency bound (the 5 percent rule): M5 Max about 130,000 ops; RTX 5090 about 210,000 at its 431 W cap (the cap binds from 102,100 ops and the governor lowers the clock); RX 9070 XT OWED. The verifier's law: 2.06 ms + 3.2 microseconds per 1,000 shadow instructions per warp, so 330,700 ops add 0.56 ms (about 1.4 ms on a 2019-class core): it fits every pairing's headroom (x8 7.8 / 4.6 ms, dr368 7.1 / 2.8, dr736 5.1 / none), and the node never binds before the cards. The verifier on a SLOWER core, measured 7 October 08:46 UK by the node lane on igneum-build-1 (an EPYC 9454P core at 3.66 GHz under schedutil, the measure hold, load 6.1; the ladder worktree's igneum-pow 59ae70cf; 50 warps averaged, the cold warp beside it) for the testnet's latency ladder (its rungs are item 8's shadow packs): rung 2 = 199,566 counted ops (the sh256x53 pack) 8.99 ms loaded (9.25 cold), ADMISSIBLE under the 10 ms gate; rung 3 = 330,740 ops (sh256x88) 5.95 ms alone (9.04 cold), 10.11 ms with the sibling loaded (10.85 cold), OVER the gate by 0.85 ms, so the testnet freezes that rung FALSE. Reading against the M5 Max's law (2.06 ms + 3.2 microseconds per 1,000 shadow instructions: 2.62 ms at 330,700): the server core is 2.3x slower alone and 3.9x loaded, so the 2.5x rule's "about 6.5 ms" for a slower core was right alone and short under load; the candidate at 100,000 ops sits well inside the gate on this core by the same ratios (about 5.3 ms loaded, approximate, not measured), and the 2019-class laptop core (O-1.14) stays the owed row. Consequence per tier: a pool core or a node on a server-class CPU verifies the candidate class inside the gate with room; the ladder's top rung is out for any core slower than an M5 Max under load, which is why the testnet ships it false.

Marginal ALU energy per counted op: the 5090 10 to 13 pJ at its shipping clock (twice the 5.5 pJ the item 1 model assumed), the M5 Max 6.9 pJ. Power caps: -pl below 400 W cannot be set, the 5 October sweep rows re-used (302 to 316 W at every cap); the clock rows are OWED (nvidia-smi refused -lgc without rights; the job did not ask; an elevated job is a decision for the founder, section 6). Item 1's denominator: the 5090 at the hash is 290 W in the app and 350 W in the bench, not 326; the f = 1 rows move 2 to 11 percent.

Chip side (approximate: the f = 1 stored-dataset chip of item 1 plus an ALU core at k times the 5090's measured 11 pJ per op): at N = 100,000 its per-joule edge over the 5090 falls from 5.6x (shadow empty, 350 W) to 2.1x on GDDR7 and 2.3x on one HBM3 stack at k = 1, 1.5x at k = 1.5, 3.2x at k = 0.5, 4.1x at k = 0.3; over the M5 Max from 1.6x to 0.9x at k = 1. The chip needs a 14,000-lane ALU array (about 30 mm^2 at N5, 150 W at k = 1) at 100,000 ops and 22,600 lanes (60 to 100 mm^2, 500 W) at 331,000; at 28 nm the array is reticle-class. That is the founder's test as a number: with the shadow filled the chip must carry the memory system and a GPU-class datapath, and its edge is the ratio k of its datapath's energy per op to the GPU's.

Consequences per tier at N = 100,000: an Apple miner loses 1.5 percent of rate and pays 16 W more (0.56x per watt, per pound unchanged); a 5090 loses 0.2 percent and goes from 350 to 431 W (0.81x per watt), so a 5090 rig pays about 23 percent more electricity for the same blocks; a pool user sees nothing; a small NVIDIA card (4060 class) binds near 100,000 by its ALU budget (model, owed); AMD holds by its budget (owed); every verifier tier is untouched (+0.17 ms per warp).

Item 8, the RTX 4070 rows (PC 1 job run-ca3-pc1-4070-shadow-20261006, 17:36:05 to 17:48:10Z, exit 0; the 4070 alone through api/cards, the installed CUDA worker's --bench, nvidia-smi at 1 Hz with 12 of 12 idle samples carrying power; the card at its Ember tune point: a 1,860 MHz core lock and the 160 W cap, memory 10,251 MHz; the 5090 and 9070 XT mining beside it; every pack's fingerprint equal to the Mac's)

N ops per hash Pack 4070 MH/s (delta) Watts (min to max) Microjoules per hash SM MHz Reading
930 (class v3) mx8-devnet-epoch0, twice 30.95 79.3 to 79.8 2.56 to 2.58 1,860 the control: 2.5x the M5 Max's energy per hash, a third more than the 5090's at the hash
49,700 sh256x13 31.08 (+0.4%) 93.5 3.01 1,860
49,700, 64-instruction block sh64x52 32.09 (+3.7%) 92.6 2.89 1,860 the 64-block gain seen on the Mac and the 5090
102,100 (the candidate) sh256x27 31.08 (+0.4%) 109.0 3.51 1,860 latency-bound; +30 W for no rate
199,600 sh256x53 31.07 (+0.4%) 138.2 4.45 1,860 still latency-bound
330,700 sh256x88 27.14 (-12.3%) 159.9 (the cap) 5.89 1,846 the 160 W cap binds; compute-bound under it

Reading: the model's "a small NVIDIA card binds near 100,000" is replaced by the measurement: the 4070 holds its rate to about 200,000 ops per hash at its tune point and binds only at 330,700 when its power cap does. Consequence per tier (main's reading, 17:5x UTC): class v4's 100,000 ops per hash costs the 12 GB NVIDIA tier nothing in rate, and the shadow has 2x headroom on that card; the 4070 owner pays 30 W more (79 to 109, 0.73x per watt); the N no card we own loses 5 percent at stays set by the M5 Max (about 130,000), not by the small card. One line to check: the restore printed "no entry was enabled before this job" and waited for no worker, while the card had been mining at 28.8 MH/s before it; the card's state after the job is read from the intake below.

Item 8, the RX 9070 XT rows (PC 1 job run-ca3-pc1-amd-g1-shadow-20261006, 15:46:27 to 15:56:54Z, exit 0; the 9070 XT alone through api/cards in every key form (amd:3:gfx1201 is the installed key today), confirmed by the process list, restored in finally and mining again 15 s later; the 5090 and 4070 mining beside it, the 5090 probably clock-locked at about 2,781 MHz from the aborted Ember step; AMD OpenCL 3683.0, device-event time, 2^24 per dispatch)

N ops per hash Pack 9070 XT MH/s (window s) OpenCL build ms / dataset ms Watts Fingerprint = the Mac's
930 (class v3) mx8-devnet-epoch0 18.92 (82), 18.92 again at the end 41 to 51 / 74 OWED (the ADLX helper ran, 0 samples parsed) yes
49,700 sh256x13 19.31 (80) 429 / 74 OWED yes
49,700, 64-instruction block sh64x52 19.07 (81) 342 / 74 OWED yes
102,100 (the candidate) sh256x27 19.29 (80) 428 / 74 OWED yes
199,600 sh256x53 19.11 (71) 424 / 74 OWED yes
330,700 sh256x88 19.60 (53) 418 / 70 OWED yes

Reading: the AMD card never leaves the latency bound on this ladder (its ALU budget is about 650,000 ops per hash); the +2 to 4 percent with the shadow is inside its clock and noise band. Consequence per tier: an AMD RDNA 4 owner loses nothing at the candidate and nothing at 330,700; the N the project can pick stays set by the M5 Max (about 130,000) and the capped 5090 (about 210,000); the one-click AMD miner pays 0.42 s of OpenCL compile per pack at the boundary against 0.05 on class v3, under half a second; the daily build is unchanged at 74 ms. The AMD per-joule row (item 1) and MH per W stay OWED until the sampler reads watts.

Item 6, the 5090 rows (ca3-reserve b85f0f1; job run-ca3-family-pc2-20261006, 08:42:27 to 08:43:03Z, exit 0, the card quiet, prover off and back on; nvcc 12.8 sm_120; best of 3 runs; every row bit-exact)

Family M5 Max, Metal (ratio to the alu chain, 881 G steps/s) RTX 5090, CUDA (ratio to the alu chain, 7,941 G steps/s) RX 9070 XT Native or emulated
rotr (live) 1.13 1.32 OWED native everywhere
shflx (live shuffle) 0.86 1.49 OWED native
variable shifts shl / shr 0.85 / 0.86 1.27 / 1.28 OWED native
bfe (bit-field extract) 0.77 1.54 (a two-instruction sequence on NVIDIA) OWED native on Apple and AMD, sequence on NVIDIA
andn 0.75 1.26 OWED native
perm (byte permute) 1.13, EMULATED 1.30 (prmt) OWED emulated on Apple
popc / clz 0.87 / 1.01 1.50 / 1.63 OWED native
sel 0.76 1.32 OWED native
shfla (lane + delta) 1.91 (2.2x the xor shuffle) 1.53 OWED native; the 32-lane crossbar is the chip's cost (about 6x the xor butterfly, approximate)
dot4 (comparison) 1.60 unsigned / 4.73 signed, emulated 1.16 1.06 (5 October)
mm8 (comparison, R8) OWED (Metal 4 matmul2d) 2.43 (mma.m8n8k16.u8, bit-exact) OWED the licensable block

The RX 9070 XT column (PC 1 job run-ca3-pc1-amd-family-20261006-e, 17:31:57 to 17:34:47Z, exit 0; the card ALONE: every gfx1201 entry posted off, its worker pid 19788 gone, three runs at 17:32:11 / 15 / 19Z with card_state=alone, every entry restored with its own flag and identities and the card mining again 20 s later under pid 13040; the gfx1036 and old-platform columns run after the restore beside the miners; AMD OpenCL 3683.0, gfx1201, 32 CUs; the range below is over the three runs' best-of-3): alu 1,074 to 1,186 G steps/s (ratio 1.00); rotr 0.99 to 1.13; shflx (xor shuffle, ds_bpermute) 0.82 to 1.21; shl 1.00 to 1.02; shr 0.91 to 1.02; bfe 1.00 to 1.09 NATIVE (amd_bfe); andn 0.91 to 1.01; perm 1.73 to 1.93 EMULATED (no byte-permute path in AMD's OpenCL C); popc 0.91 to 1.01; clz 1.19 to 1.30; sel 0.90 to 1.01; shfla (lane + delta, ds_bpermute) 0.75 to 0.84 NATIVE; dot4 1.00 to 1.11 NATIVE (sudot4); mm8 1.68 to 1.83 NATIVE (the WMMA iu8 builtin reaches gfx12; exact UNVERIFIED: the fragment layout is not in any source at hand, so the CPU reference was not attempted rather than guessed). The AMD column of item 6 is CLOSED. Reading: on RDNA 4 every 32-bit datapath family sits within 0.75x to 1.30x of the alu chain, the shuffles cheaper than it (an LDS operation overlapping the dependent chain), so the ds_bpermute number that could have moved R3 leaves the order as proposed; the two dear rows on AMD are the same two as on Apple and NVIDIA, the byte permute and mm8.

Reading: against the live rotr every candidate is 0.95x to 1.23x on NVIDIA; on Apple only perm (emulated) and shfla cost more than rotr; the 8x emulation bound of 1.13.2 holds everywhere by 4x or more; the 5 percent hash-rate bound at W_new = 4 is argued from the step cost (under 1 percent of ALU time on a read-bound hash), not measured, since no reserve family is live. Proposed order R1 perm, R2 popc and clz, R3 shfla, R4 bfe, R5 shifts, R6 sel, R7 andn, R8 mm8, W_new = 4 each, family n at era n (mm8's era-4 unlock kept as a named exception or moved to era 8: the founder's call); the full proposed 1.13.2 text with edge vectors per family is docs/plans/counter-asic-3-reserve.md section 6. Consequence per tier: an Apple miner pays the emulated perm at 1.13x a step and shfla at 1.91x, under 1 percent of its hash rate at W_new = 4 (argued); an NVIDIA miner pays nothing measurable; an AMD miner's row is owed and its ds_bpermute_b32 cost is the one number that could move R3; a chip pays a barrel shifter, a byte crossbar, a popcount tree and a 32-lane crossbar per lane, which is the point.

Item 6, the Mac rows (interim, ca3-reserve 192a683; the 5090 job waits on PC 2)

Step cost per family on the M5 Max as a ratio to the add-xor-rotate chain (881 G steps/s; best of 3; load average 7.64; all bit-exact): shl 0.85, shr 0.86, bfe 0.77, andn 0.75, byte permute 1.13 (emulated on Apple), popcount 0.87, clz 1.01, select 0.76, indexed shuffle 1.91 (2.2x the xor shuffle), live rotr 1.13, dot4 unsigned 1.60, dot4 signed 4.73. Every 32-bit datapath family costs an Apple lane under 1.2x a step, inside the 8x emulation bound of 1.13.2 with room; the matrix family is the only one past 1.6x. The rows feed item 8's ALU pricing. The full table with consequences lands at item 6's close.

Items 4 and 7 on the live tables (dry mode, read-only, 09:2x UTC; the live observer still runs master's code)

Module Reading Consequence
Detector (window epochs 41 to 46, tip DAA 171,165, 20 ids) network 125 to 152 MH/s per epoch, settled; bands from the fleet log 5090 99.4 / 115.6 / 123 MH/s (n 849), M5 Max 26.5 / 27.4 / 28.5 (n 586), Intel UHD 1.7 / 1.8 / 2.2 (n 758); correlation pairs 6, max r 0.94, edges 1 (the two 5090 ids, PC 1 back since 07:2x), groups none; alert inactive, held 0 of 6; events none quiet on the devnet; two findings sent to the detector worker: two honest same-model cards cross the 0.8 edge (the group rule of 3 or more ids is what keeps the alert off; the edge may be a network-estimate artefact), and each 5090 id reads about 50 MH/s on chain against the 115 MH/s band (a factor of two to explain before an unknown miner is banded). ANSWERED (ca3-detector 9c7838e, merged): the r 0.94 edge was an artefact of the epoch common factor (the mean over every present id let the paused-and-resumed Mac push the other residuals together); the factor is now the median over the steady core ids, and the same window reads max r 0.10, no edge, tests 7 of 7, the fabricated design still alerts. The factor of two is identities=2 on PC 2's worker (2 x 50.4 = 100.8 MH/s on chain against the 115.6 band, 0.87x, the ratio the whole network shows: reds, pending blocks, template latency); the key count joins the coinbase tag with the card model (owed, 0.3.12). The devnet's max pairwise r over the windows run is 0.10 to 0.53 against the 0.8 edge; the alert stands as a trigger with the 3-id group rule
Vendor share (10-minute window, network 253 MH/s) fleet-reported: NVIDIA 241.7 MH/s (2 workers, 0.920), AMD 18.8 (1, 0.072), Intel 2.2 (1, 0.008), Apple 0 (the Mac paused); chain-attributed: NVIDIA 0.914 (529 of 579 blue blocks, 10 ids), AMD 0.078 (45 blocks, 8 ids), Intel 0.009, unknown 0 (every id maps to a fleet key, 30 mapped) the two readings agree within 1 percent; the devnet is a one-vendor fleet at 91 percent NVIDIA, which is what the metric is for: an AMD owner's share of income is 0.078 for 1 of 4 cards, an Apple owner's 0 while paused; the public testnet's number is the one that matters

The live observer runs the shared checkout, which autosync fast-forwards from origin/master; new code reaches it only through a push to master, which is the founder's call (CLAUDE.md: push only when the founder asks). So the one restart main asked for waits on that push; the dry rows above are the evidence until then.

Consequences per tier (item 1)

Tier Meaning Being done
Home miner, 8 or 12 GB card Nothing today (no chip exists; a 28 nm controller project is $5M to $30M and about 32 months by the Ethash precedent); when one lands it runs 0.3 to 0.5 microjoules per hash against 10 to 20 for this tier (approximate), the first tier out the power-cap rows and the item 8 measurement; the detector (item 4) is what tells this miner a chip has arrived
16 GB AMD (9070 XT) 7x worse per joule than the 5090 and 30x worse than the chip (approximate); a chip ends AMD home mining first vendor-share metric (item 7); nothing in the hash fixes AMD's 2.4 G dependent reads/s
24 or 32 GB (5090, M5 Max) the honest best at 2.40 microjoules; 5x to 9x behind the chip in the model, 2x to 5x by the precedent a 200 W cap on the 5090, if the rate holds, halves the gap
Rig per joule it is its cards; at $2.8 against $14.7 per MH/s a chip fleet is cheaper per dollar too the issuance trigger: bounty and benchmark live before daily issuance crosses about $50K (item 4b)
Pool user a chip fleet is a few operators; Monero's was found at 85 percent by its share pattern the detector, before the public testnet
The public claim "under 2x" held for the recompute chip at the op budget; per joule and against the stored-dataset chip the model reads over 2x on both memories and the precedent reads 2.1x to 4.8x; NOT SAFE TO PUBLISH as worded decision for the founder (section 6); nothing on the site or the devnet changes from this run

3a. Corrections found by the run

Found by What was wrong Fixed
item 3 (43c3ead) spec 01 section 1.13.1's era table and docs/plans/mixer-x4.md section 2 still said mixer_mult = 4; the code (LoadClass::MX8, V3_CLASS) and spec 1.8.5 say 8 both lines corrected on ca3-coord, 6 October 2026
PC 1 job 2 (family, run-ca3-pc1-amd-family-20261006, 16:56 to 16:59Z) the probe ran on device 0, the integrated gfx1036, not the 9070 XT (device 1): every row dev=0 name= empty, alu 40.59 G steps/s (a one-CU figure); the rows are RDNA 2 iGPU ratios (shifts 1.15, bfe 1.15 native, andn 1.16, popc 1.55, clz 1.75, sel 1.81, shfla and shflx 1.89 through ds_bpermute, perm 2.43 and dot4 2.57 emulated, mm8 none: AMD's OpenCL C compiles no byte-permute, dot4 or WMMA builtin) and the 9070 XT column stays owed the probe picks the device by name (gfx1201 on the newest AMD platform) and prints it in every row; re-run in the next PC 1 slot
the watts job (run-ca3-pc1-amd-watts-20261006, 17:49:46 to 17:52:54Z, FAILED exit 1) the sampler proved itself (12 of 12 9070 XT watts lines), the 90 s app-state window ran (the card mining at 18.87 MH/s, 203 W, identities 8 before it), every gfx1201 entry was posted off, the card went quiet and the sh256x27 bench started; then the script exited with no APPROW, no LADDER, no watts error= and NO RESTORE line in any upload (no enabled=True post, no card_workers_after): a finally that did not run or did not print, so the 9070 XT may have been left OFF CONFIRMED and restored: api/state at 17:55:10Z read the card enabled false, state off, 23 W idle; the identities job run d posted it back and at 17:57:10Z it mined under pid 3436 at 18.9 MH/s, 195 W, identities 8; the entry amd:1:gfx1201 was set back to enabled at 17:59:05Z (job run-ca3-pc1-amd-flag-amd1-20261006) with the card mining through it (18.86 MH/s, 200 W); PC 1 free at 18:01:05Z; the AMD watts row stays OWED; the cause and a fixed script (an unconditional finally with its own first line, no exit inside the try, the device dumps out of the report) with the script worker before any re-run
the 4070 ladder's restore line "no entry was enabled before this job" and no wait for the worker, while the card had mined at 28.8 MH/s before it the intake shows the 4070's worker restarted 15 s after the restore and racing at 30.9 MH/s: the card came back; the script's settings read, not the card, was wrong
PC 1 family run d (run-ca3-pc1-amd-family-20261006-d, 17:17 to 17:20Z, exit 0; run b had failed because the script's probe parameter was named $args, PowerShell's automatic variable, so the splat was empty: renamed, with a rule added to tools/ci/ps-drive-ref-check.sh that fires on the old signature and stays quiet on the new) the probe chose the 9070 XT by name (gfx1201, 32 CUs); every variant built on it: mm8 NATIVE through the WMMA builtin on gfx12 (exact unverified), dot4 native (sudot4), bfe native, the shuffles native (ds_bpermute, ds_swizzle), the byte permute EMULATED (no amd_perm path in AMD's OpenCL C). The step costs are unusable: the card was mining beside the probe, the alu chain read 226 then 195 G steps/s and the ratios swung from 5.9 to 11.8x (run 1) to 0.17 to 1.3x (run 2), the loaded card's scheduler the 9070 XT column is taken with the card alone (run e, job 1's switch path), after the G2 job
the identities job, first run (run-ca3-pc1-amd-identities-20261006, 17:02:10Z, failed in 0 s) my own script: "... under $appDir: nothing posted" is a PowerShell 5.1 parse error ($appDir: reads as a drive-qualified variable), so the script never started; the script worker checks this shape by hand, CI did not ${appDir}:; the class guard tools/ci/ps-drive-ref-check.sh added to ci.yml (67 .ps1 files clean; a backtick-escaped $ in a bash-generating here-string is ignored); the job republished as -b
the identities job, run c (run-ca3-pc1-amd-identities-20261006-c, 17:05:53 to 17:07:53Z, done) the 9070 XT's live entry amd:gfx1201 read identities 2 at 18.91 MH/s and 203 W before; the one POST (the app's cards-array shape) and a 120 s settle; after: identities 8, mining under a new worker pid, 18.9 MH/s (avg 18.77), 199 W. The identities count moves no rate (18.92 at 2 was the number to beat). Run b of the same job had failed on the flat body shape (400) closed: PC 1's 9070 XT runs as it did before job 1
the reset job (16:55Z) the 9070 XT's ADLX state read factory 0 after Ember run 6 (offsets zero, the flag cleared by the engine's set of 0); the app runs the card under amd:gfx1201 with identities 2 where it ran 8 before job 1's restore the reset to factory 1 applied and read back; the one POST api/cards back to 8 identities running as its own job, the rate before and after recorded
item 2's PC 2 job the settings.json card key is nvidia:0:NVIDIA GeForce RTX 5090 (with the device index); the 5 October job scripts posted the state's key without the index, so POST api/cards switched nothing and the miner stayed up through the 90 s wait: the job's 5090 rows are loaded-card figures items 6 and 8 told to post both key forms and confirm by the process list; the class fix (one key form everywhere, a check that fails a job script posting a card key without the index) is owed to the job tooling
the coordinator's merge of ca3-shadow git add -A docs staged docs/bench-log.md with its conflict markers inside (a conflicted path is marked resolved by git add), so 45f3019 carried markers into HEAD; found at the ca3-reserve merge as nested markers the three 6 October entries kept in order with every marker removed (fcce185); the class guard already exists, tools/ci/no-conflict-markers.sh in CI, and it would have failed the push; it passes on the merged tree
the merge of ca3-derive and ca3-shadow both added a field to LoadClass (derive_len, shadow); resolved as the union, every other literal spreads ..; cargo test -p igneum-pow on the merged tree (cargo 1.99 at ~/.cargo/bin; the Homebrew 1.69 on PATH cannot read the lock file): 59 + 7 + 4 + 19 + 7 = 96 passed, 0 failed, the pinned v2 and v3 packs byte for byte merged 09:10 UTC
item 3 the mixer's op count: 144 integer ops per application as written in memhard.rs (128 with RC and rk hoisted) against the 130 the chip model prices (chip-model-v3.md section 1, from spec 1.8.4) items 1 and 2 asked to state which figure their rows use and why; the status close carries the answer

4. The chip model, before and after

Every chip figure is arithmetic on cited memory and logic figures and is approximate; every GPU figure is measured and names its entry. "Per chip" is rate per chip against the 5090's rate; "per joule" is energy per hash, the Ethash chips' metric.

Chip Before 3.0 (the 2.0 record, 5 October) After 3.0 (6 October) Source
On-die 256 MiB cache recompute chip (f = 0), class v3 0.31x bare, 0.92x with the 3x fixed-function factor per chip; per joule not priced; the public claim "under 2x" rested on this row per chip unchanged; per joule 1.86x (1.3x to 2.4x over the on-die read energy); with the per-day derivation (item 2, dr736) the 3x factor goes: 0.29x bare, 0.34x at a 1.2x allowance, 0.43x at 1.5x chip-model-v3.md sections 2, 5.4, 6
Stored-dataset memory-controller chip (f = 1), the Ethash class not priced (O-1.6 open, the curve never drawn) per chip 1.22x on GDDR7, 0.61x on one HBM3 stack, 4.9x on eight; per joule 5.1x (GDDR7) to 9.2x (eight HBM3 stacks) at the 326 W denominator, 5.6x at the measured 350 W bench control; $2.8 per MH/s against the 5090's $14.7; the Ethash precedent for this class 2.1x to 4.8x per joule; the curve is monotone toward f = 1 so the partial-store chip is never built; the mixer, item 2 and x16 do not touch it chip-model-v3.md section 5; history rows 3 and 4
The same chip with the latency shadow filled (item 8, N = 100,000 ops per hash, class v4 candidate mx8+sh256x27) not a lever anyone had priced per joule over the 5090 2.1x (GDDR7) and 2.3x (HBM3) at k = 1, 1.5x at k = 1.5, 3.2x at k = 0.5; over the M5 Max 0.9x at k = 1; the chip needs a 14,000-lane ALU array, about 30 mm^2 at N5 and 150 W at k = 1, reticle-class at 28 nm; k, the chip core's energy per op against the 5090's measured 11 pJ, decides it, and 2x is crossed only at k under 0.5 latency-shadow-2026-10-06.md sections 6 and 8
The honest denominators the 5090 at 136.1 MH/s and 326 W (a peak with the prover on) the 5090 at 290 W in the app and 350 W in the bench (2.34 to 2.65 microjoules per hash), cap floor 400 W so no power cap binds; the M5 Max at 21 W GPU plus DRAM (0.78 microjoules), three times better per joule than the 5090 and the honest best we own item 8; miner-eff's 4 October log

What 3.0 did to the model in one line: the chip that matters is not the one 2.0 priced; it is the Ethash-class memory-controller chip, over 2x per joule today; the lever that answers it is program work in the latency shadow, which makes the chip carry a GPU-class datapath, and the measured candidate takes its edge from 5.6x to 2.1x at a chip core no better than the GPU's, for 0.2 percent of the 5090's rate.

5. What passes as class v4

Judged on measurements against the six gates of docs/plans/counter-asic-2-rollout.md section 7. Nothing is published; nothing is cut.

Candidate Measured The six gates Verdict
mx8+sh256x27: class v3 plus a 256-instruction ALU block run 27 times per iteration, about 100,000 ops per hash (item 8) hash rate -0.2 percent on the 5090, -1.5 percent on the M5 Max, under the 5 percent rule; verifier +0.17 ms per warp (2.23 ms, gate 10 ms, 2019-class core about 5.6 ms); bit-exact on Metal, CUDA, clang emulation and Apple OpenCL; the 5090 at 431 W (its cap) from 350; the 9070 XT owed G1 bit-exact: NVIDIA and Apple GREEN, the AMD vendor NOT RUN (gfx1036 or the 9070 XT); G2 (1,000 random hashes per card re-hashed on the CPU): NOT RUN; G3 (crate suite green: 96 of 96; the Metal fuzz, edge and stats runs on the class): NOT RUN; G4 (the fast-time 3-node network across a v4 activation): NOT RUN; G5, G6: NOT RUN READY FOR THE GATE RUN as THE class v4 candidate, on the founder's word; not ready for a cut. Two design decisions ride with it: the acceptance rule does not yet interpret the block (cost stated in the analysis), and the block stays at 64 to 256 instructions
dr368 or dr736: the per-day derivation (item 2) dr736 verifier 4.9 ms per unit on the M5 Max core, about 12 ms on a 2019-class core (over the gate); dr368 2.69 ms, passes both; bit-exact on Metal, Apple OpenCL and CUDA; build +7 ms a day on the Mac, +2 ms on the 5090; NVRTC +1.1 s per pack (a once-a-day module is a requirement) not a v4 candidate: a reserve entry GO as reserve R0 (proposed text, counter-asic-3-derivation.md section 6); NO-GO genesis-live at dr736 until O-1.14; urgency LOW (the f = 1 chip derives no item)
The reserve order R1 to R8 (item 6) step costs on two cards, every family under 1.91x a step, bit-exact a spec ordering, no activation GO for the order as proposed; a decision for the founder
Layer 9 (epoch length) ranked above layer 7 (mm8) (item 5) FPGA soft overlay 0.30x to 0.39x per watt on the measured basis, 0.7x to 1.9x at the unmeasured bank-bound ceiling reserve ranking GO for the ranking; the rented FPGA hour owed

So: one class v4 candidate, mx8+sh256x27, defined and measured on the hash's own numbers, with gates G1 (AMD), G2, G3 (Metal runs), G4, G5 and G6 still to run before any publish, by the two-publish rollout of 2.0 and a program_class_v4_activation_daa at tip + 14,400.

5a. The gate run (the founder, 16:50 UTC: "3.0 run it now"; opened 16:5x UTC)

No publish, no manifest, nothing on the live devnet; PC 2 one job at a time with the installed app untouched; the Mac's miner stays paused. Two lanes: the hash side (branch ca3-v4-hash: G1 Metal, Apple OpenCL and CUDA, G2, G3 and the verifier benchmark; one PC 2 job first) and the node side (branch ca3-v4-node and the fork worktree igneum-node-ca3v4 from release-0.3.13-node: the v4 switch through igneum-pow, the fork, the workers, the miner and the app, then G4, G4b, G6 with --features igneum-pow, G5; its PC 2 jobs after the hash lane's). G1 AMD rides in PC 1 job 1 on "go PC 1 AMD". Evidence lands in docs/plans/counter-asic-3-gate/.

Gate What State Evidence (full lines in docs/plans/counter-asic-3-gate/hash-gates.md and node-gates.md, JSON per run beside them)
G1 bit-exact v4 on every vendor against the Mac reference (2^24 fingerprint, self-test) GREEN on all three vendors Apple (Metal and Apple OpenCL, 15:49 to 15:50Z) and NVIDIA (the 5090, PC 2 job, 15:52Z): eight packs, three harnesses, one fingerprint per pack; AMD (PC 1 job run-ca3-pc1-amd-g1-shadow-20261006, 15:46 to 15:56Z): 7 of 7 packs equal to the Mac's on gfx1201 (sh256x27 3d2e8245cc084d07)
G2 the CPU verifier exact on 1,024 random hashes per card GREEN on all three vendors AMD (PC 1 job run-ca3-pc1-amd-g2-20261006, 17:22Z, the kit worker's serve mode on gfx1201 through the class=v3 and class=v4 tokens, beside the miners): 1,024 of 1,024 found and distinct on the control mx8-devnet-epoch0 (digest 2a1824a2...) and on the generator-4 candidate v4-devnet-epoch0 (435b976a...), both re-hashed on the Mac through tools/ca3-v4/g2-recheck.sh --digest: MATCH 1,024 of 1,024 each. The first kit's sh256x27 is a string-seed pack the worker's job protocol refuses, so G2 ran the chain-seed packs the 5090 and the Mac ran
G3 the soundness suite green on the class GREEN the crate suite 96 of 96 (97 on the merged tree at 17:17Z, cargo 1.99); the Metal fuzz 200 of 200 and 50 of 50; Apple OpenCL 20 of 20 and 5 of 5; 4 of 4 CPU tests on the class and on the era-composed class
Verifier benchmark ms per warp on one M5 Max core, v2 / x8 / v4 in one session, gate 10 ms GREEN 2.33 ms on the candidate (x8 2.06), about 5.8 ms on a 2019-class core by the 2.5x rule (approximate); the 2019-class core itself still unmeasured (O-1.14)
G4 the fast-time 3-node network across a v4 activation, plus the known-failed case GREEN (and GREEN again on the id fix with the id assertion and its failed case, 491131a) run 1 (15:54 to 15:59Z, class-v4.mjs, activation 150 rounded to epoch 3 at DAA 180, the v3 switch at 60): 3 of 3 switch lines, templates class 2 / 3 / 4 by epoch, 181 blocks before and 128 after DAA 180, program ids agree on all three miners and no v2 or v3 id reappears under v4, rejected 0/0/0, one sink at 308/308/308, one digest; the first v4 epoch's cache ready in 2 ms (the v3 day cache reused across the boundary); run 2 the known-failed case (the switch at never: no v4 epoch reported)
G4b a real Metal miner across a v4 boundary through --prepare-packs GREEN run 3 (16:02 to 16:07Z, igneum-bench from the committed tree): 5 PREPARE lines 5 to 6 DAA before each boundary, three class=v4 era=<hex>, the worker's prepared lines (430 ms the first with the v4 day built on the GPU, 139 and 175 ms with the day resident; a v3 prepare 62 ms), every swap with no pause, 301 blocks accepted on the Metal miner (123 after the switch) all re-checked on the CPU mismatched 0, need 0, no mismatch or out-of-date line, no exit 42 or 44
G5 the PC-built Windows workers and the Mac workers from the same commit GREEN, one gap named (re-done from the fix 7c22d0d: cuda.exe 3bc8ad8f..., opencl.exe 16ef0154..., igneum-bench f9ca4b07...) the Windows workers cross-built on the Mac from a522d04 as 0.3.11's G5 did (the build job has no worker unit: a tooling gap): igneum-worker-cuda.exe e563126e... (1,536,512 bytes), igneum-worker-opencl.exe 7fce1249... (478,208), both with the resource block, mingw not bit-reproducible (a link-time stamp); the Mac igneum-bench 30c70754... from the same tree, the binary G4b mined with; the node and app from PC 2 job build-20261006-155958, every sha256 verified
G6 the node suites on PC 2 with --features igneum-pow, from a fork branch off the current release tip GREEN fork ca3-v4-node 5f7e0543 on release-0.3.13-node; PC 2 job build-20261006-155958 (15:59 to 16:08Z under the lock, the app untouched, the prover on): every stage ok in 392 s; kaspa-consensus 98 (2.0's flake did not recur), consensus-core 109 + 7 (override_params_carry_the_program_class_v4_activation), kaspa-pow 15 with the v4 engine test under the feature, p2p-flows 33, igneum-app 112 + 26 + 8

BLOCKER before any cut (found by the hash lane, 17:0x UTC): program_id(3, seed, attempt) is class-independent, so all seven v4 packs carry the same program id as the v3 control of their seed (73bcbfe8ccf988f1), and a stale worker across the activation would see no id mismatch (2.0's G4 id check cannot fire on it; G4's per-epoch ids differ only because each epoch has its own seed). The fix is on the v4 seam, assigned to the node lane: a generator-4 stamp in the id so a v3 and a v4 program of one seed differ, v2 and v3 ids byte-identical, the packs re-exported (fingerprints unchanged, ids moved), G4's id assertion and the fuzz re-run. FIX MERGED (ca3-v4-node 7c22d0d, 17:3x UTC): the trap was the CLI's --era path (stamp_era stamped generator 3 on any class), not the chain seam (the fork already stamped generator 4 and its kaspa-pow test asserts the same-seed v3 and v4 ids differ); now generate_era and the CLI stamp the generator from the class, the shadow block marks class v4 in packcheck.rs, packfile.h and main.swift (a generator-3 pack with a shadow block is refused as "a v4 program stamped v3", a generator-4 pack without one refused; the ladder packs stay loadable); v2 and v3 ids byte-identical; the crate suite 97 of 97 on the merged tree; the seven gate packs re-exported with generator 4, class "v4" and program id c120d7963abdcd96 (the v3 control keeps 73bcbfe8ccf988f1), only the generator, id, class and comment lines changed, the kernels and vectors byte-identical. The hash lane's re-run on the fix is GREEN (ca3-v4-hash ca61dec, merged; hash-gates.md "Follow-up 1"): the crate suite 97 of 97; the seven packs re-exported here equal the tree's (0 differing files); the fingerprints unchanged on the rebuilt Metal and Apple OpenCL harnesses (all eight); Mac G2 through the class=v4 token 1,024 of 1,024 on all eight packs, both harnesses; the fuzz 200 programs and 800 units, stats, edge and determinism 4 of 4 on the class and 4 of 4 era-composed, the same-seed v3 and v4 ids now differ (assert_ne). The node lane's re-run on the fix is GREEN (ca3-v4-node 491131a, merged): G4 re-run 16:32 to 16:38Z on igneumd and igneum-miner rebuilt on the fixed crate, SUMMARY PASS, 181 / 125 blocks across DAA 180, rejected 0/0/0 and 0/0/0, one sink at 305/305/305, and the id assertion: every v4 epoch's id on all three miners equals the CLI's class v4 id for that seed and era and differs from the same-seed v3 id (e3 30544487d1289d6e against 1ae1c9f0eda0cef5, e4 53e36801cc6fafcf against af81f6e844959460, e5 876e155e3fb59983 against b4f25c4678496a78); the assertion's own failed case (--id-check-against v4) reports exactly FAILED CHECK v4_ids_differ_from_the_same_seed_v3_id, exit 1. The seven re-exported packs' Metal fingerprints by packbench equal the table (only the ids moved). G5 re-done from 7c22d0d because packfile.h and main.swift moved: igneum-worker-cuda.exe 3bc8ad8f..., igneum-worker-opencl.exe 16ef0154... (resource block verified), igneum-bench f9ca4b07...; kaspa-pow with the feature 15 of 15 on the rebuilt fork. THE BLOCKER IS CLOSED: the gate table is green on the hash and on the cut, with AMD G2 and the AMD watts the owed rows (queued on PC 1). Two conditions ride with the fix: every kit sent to a PC carries the re-exported packs (the AMD G2 kit is being rebuilt from the merged tree), and the mixer.rs harness change rides with any merge of 7c22d0d (it does, on ca3-coord). The PC 1 AMD rows taken on the old-id packs stand: the id is not an input to the hash.

The per-tier cost line of the candidate (item 8, measured): the 5090 -0.2 percent of rate at 350 to 431 W (a rig about 23 percent more electricity), the M5 Max -1.5 percent at 21 to 37 W, pool users nothing, the verifier +0.17 ms per warp; the 9070 XT and the 4070 rows land with the PC 1 jobs. Owed before the cut, besides the blocker: the AMD watts (the sampler fix is in; the re-run queued), the 2019-class core (O-1.14; the US laptop's CPU could answer it with a Windows igneum-pow build, a proposal), the G2 found-lines file and digest and the 200 KB report cap (tooling, in hand on ca3-v4-hash).

Two preconditions on the cut, from main (17:0x UTC, both from today's incident), assigned to the node lane:

# Precondition What passes it State
P1 The cut rehearses first on the rented fleet as a staging network (the fleet agent owns the boxes; the node lane supplies the v4 override object and the rehearsal plan docs/plans/counter-asic-3-rehearsal.md) a fleet-only chain crosses the v4 activation with every box switched: zero rejected blocks, blocks on both sides, the G4 id assertion live on every box, one sink, one digest; the stale-box case refused at the handshake with no fork PASSED 19:33Z (the run's record in section 5a's P1 cell below the table and docs/plans/counter-asic-3-rehearsal.md). PLAN WRITTEN (ca3-v4-node f39a8eb, merged): fleet-only chain igneum-devnet-400 from its own genesis state, 12 or more mining boxes, a seed box, one stale 0.3.13 box; the signal flip at DAA 7,200 (the first full 3,600-DAA window) with the floor at 14,400 not reached; ten steps, the report fields and pass rules; the id assertion from the boxes' miner lines. Two objects as files in docs/plans/counter-asic-3-gate/: the publish object (the live 13 fields plus program_class_v4_activation_daa = N6, the floor, tip + 14,400 rounded up, 219,600 at the 16:57Z DAA of 202,919, and program_class_v4_signal_window_daa = 86,400; digest ac8e60ce...) and the rehearsal object (every earlier switch at 0, window 3,600, floor 14,400; digest bc2142b1...); the no-file devnet digest on this binary 7f2e49be... (3c505021 superseded: the window field joined the digest). THE RUN STARTED 18:22Z (the fleet agent): igneum-devnet-400 from the devnet genesis with the re-cut 1-block/s object override-v4-rehearsal-1bps.json (600-DAA epochs, lead 100, window 600, the flip at epoch 2 = DAA 1,200, the floor at 2,400; node digest d23394e7...; the file written byte for byte on every box) and the signalling fork's Linux binaries from PC 2 job build-20261006-174823 (igneumd 847ddfd1..., igneum-miner 37178aeb..., verified on the Mac and every box); the seed on the RunPod pod dn2-seed (public p2p 213.173.110.229:11927, no miner); 15 mining boxes beside their live-devnet nodes on separate ports with fresh appdirs and 1-thread CPU miners (dn2-1, dn2-2, dn2-3, hub-1, 3080, 4070, 4090, 5090, A5000, 3090-2, 3090-3, 4070-1, 4090-1b, 4090-3, the 8x 4090 rig); the stale box p2-3090-4 on 0.3.13's igneumd d6350586 with the same file and no miner, started last; the 38 wave pods join about 18:50Z. The clock from the seed's genesis at about 18:23Z: the window full 18:41Z, the flip about 18:43Z, the floor about 19:03Z (run to the floor so its line is exercised). A sampler on every box every 5 minutes; the id lines go to the node lane for the CLI check; the report in section 4's table plus rehearsal-
P2 No fixed-height activation on the live devnet again: miner signalling for class changes as the v4 seam's activation rule (the block carries the miner's object version; the class flips at the first epoch boundary after 95 percent of mining weight over a window signals the new object, with a floor height after which it flips regardless), PROPOSED spec text in counter-asic-3-node.md, implemented behind the override, with the fast-time harness test (67 percent does not flip; 100 percent flips at the next boundary; nobody signals and the floor flips it; each with its failed case) and G6 again on PC 2 the three harness runs PASS with their failed cases; G6 green on the fork change GREEN (ca3-v4-node 0635c04 and 3892035, fork 0562a7f2 on 5f7e0543; PROPOSED text in counter-asic-3-node.md section 6: the header version's high byte carries the node's object version, the low byte stays the block version so later objects pass the version check; weight = blue blocks by the finality walk over the window ending at each epoch's seed block; 95 percent = 9,500 bps; window 86,400 DAA in the file and the digest, 0 = off; monotone, memoised per seed block; the fixed height stays as the floor; IGNEUM_CLASS_SIGNAL lowers a node's byte on devnet and simnet only; RPC fields 20 to 23). The fast-time gate infra/fast-time/class-v4-signal.mjs (three CPU miners, window 120, v3 from 60): two of three signalling PASS with no v4 epoch over epochs 0 to 7 (share 6,166 to 7,583 bps, 0 rejected, one sink 424/424/424); all three PASS with the flip at epoch 3, the first full window, 10,000 bps, 3 of 3 switch lines, 181 / 124 blocks, 0 rejected, one sink, the id assertion on epochs 3 to 5 (e3 e48e6be7c6699824 against the v3 6847355c88e8215f); nobody with the floor at 300 PASS, 0 bps, the flip at epoch 5 by the floor and not before; the failed case (two of three told to expect a flip) FAIL on eight checks. G6 on the signalling fork: three PC 2 jobs under the lock, prover on, app untouched (build-20261006-173017 hit 2.0's flake, 97 of 98; build-20261006-174027 kaspa-consensus alone exit 0; build-20261006-174823 the five crates exit 0 in 35 s with consensus-core 110 + 7, igneum-exec 18, kaspa-pow 15 with the v4 engine and the signal-rule tests, igneum-miner 18, p2p-flows 33, and the app 112 + 26 + 8 exit 0; its closing line "upload incomplete" is the relay blob fault after both test stages closed exit 0). Owed and named: a class-signal witness in the pruning-proof format (a proof-synced node falls back to the floor rule for epochs whose window reaches below its pruning point and logs it), the same class as the era witness

Facts for the cut from the node lane (docs/plans/counter-asic-3-node.md): the devnet digest moves (c562d70e... to 3c505021...), so the cut is a one-sweep binary rollout and a 0.3.13 node is refused at the handshake afterwards (intended, fleet-wide); a 0.3.13 miner reads the v4 height as never (an optional proto field), so miners and nodes move together; infra/fast-time/override-60x.json as committed carried the proving-v1 block twice and lacked four 0.3.12 and 0.3.13 fields (the node refused the file; fixed, with a new CI check override-json-check.sh); the 48 GiB target clone vendor/igneum-node-ca3v4/target-ca3v4 can go after the cut.

THE ONE LINE FOR THE FOUNDER: class v4 (mx8+sh256x27, 100,000 ops per hash in the latency shadow) has passed every gate on the fixed tree (the program-id blocker closed with its own failed case) and P1 HAS PASSED (the fleet rehearsal, 19:33Z: the flip by miner signal on 52 nodes, one program id per epoch on every box for three epochs, zero rejected, the stale box refused, the floor crossed with v4 in force), so class v4 is ready for the cut ON THE FOUNDER'S GO, in the order publish 1 the 0.3.15 binary with no handshake split under the digest-compat rule, publish 2 the sixteen-field object as the one sweep once every NODE AND EVERY WORKER in the fleet is 0.3.15's (the shipped 0.3.14 worker refuses a generator-4 pack, so a box whose worker lags stops at the flip), its digest read on the fixed 0.3.15 binary: P2, miner-signalled activation (95 percent of blue-block weight over a one-day window, the floor height after which it flips regardless), is designed, implemented and GREEN on the fast-time gate with its failed case and on G6; P1, the rehearsal on the rented fleet as a staging network, has its plan and objects written and waits for the fleet agent's run; the clean-day wait removed by the founder ("can we run the v4 class now?", 18:2x UTC): the P1 rehearsal runs NOW on the fleet (15 prover boxes plus the four Devnet 2 boxes, the wave joining about 18:50Z) and the 0.3.15 cut (class v4 plus the fourteenth field, one digest move, miners first, hands last) goes tonight on the founder's go the minute P1 passes; its cost is the 5090 at 431 W instead of 350 for 0.2 percent less rate (a rig pays about 23 percent more electricity), the M5 Max at 37 W instead of 21 for 1.5 percent, the 9070 XT no rate at all (its watts pending), the verifier +0.27 ms per warp; what it buys is the stored-dataset chip's per-joule edge over the 5090 falling from 5.6x to 2.1x at a chip core equal to the GPU's; proposed for a day when no other cut is in flight, not tonight (0.3.14 and the fleet night come first).

6. Decisions for the founder

  1. The public claim. "Under 2x" is true of the recompute chip per chip at the op budget and false of the stored-dataset chip per joule (item 1). Nothing on the site or in the litepaper changes from this run; the two drafts below are for the founder's decision, with the rows that bound them.
Row Per chip (rate) Per joule Source
On-die recompute chip, class v3 (f = 0) 0.92x with the 3x factor (0.31x bare) 1.86x (1.3x to 2.4x over the on-die read energy) chip-model-v3.md sections 2 and 5.4, model
Stored-dataset memory-controller chip, GDDR7 (f = 1) 1.22x 5.1x chip-model-v3.md 5.4, model
Stored-dataset chip, HBM3 one stack / eight stacks 0.61x / 4.9x 7.5x / 9.2x chip-model-v3.md 5.4, model
Ethash precedent, the same chip class: Linzhi Phoenix 2020, Antminer E9 2022, Jasminer X4 2021 2.1x / 2.9x / 4.8x per joule asic-resistance-history.md rows 3 and 4
With the latency shadow filled (item 8, model until measured) 1.22x 1.85x at N = 330,000 and a chip core equal to the GPU's ALU; 2.5x at 1.5x worse chip-model-v3.md 5.7

Draft (a), scoped: "The strongest recompute chip we can price, holding the whole 256 MiB cache on-die, reaches under 1x per chip against an RTX 5090. A memory-controller chip that stores the whole dataset reaches 1.2x per chip and, in our model, 5x to 9x per joule; the Ethash chips of this class reached 2.1x to 4.8x. The lever against it, program work in the latency shadow, is being measured (Counter ASIC 3.0 item 8)."

Draft (b), the measured fact only: "An RTX 5090 mines this hash at 136 MH/s and 17.5 billion dependent 4-byte reads a second, 82 percent of its memory's random-read ceiling, with its integer units at 0.15 percent of their budget. A chip beats it only by reading per watt what a 512-bit GDDR7 board reads, and the gap is the card's own idle logic."

Either replaces "under 2x" on the site and in the litepaper once the founder chooses; until then the claim stays as it is and this file records that it is not safe as worded.

  1. The class v4 candidate: run the six gates on mx8+sh256x27 (100,000 ops per hash) and, if green, cut it by the 2.0 rollout shape. Cost to the tiers: the 5090 goes from 350 to 431 W for the same blocks (a rig pays about 23 percent more electricity), the M5 Max from 21 to 37 W for 1.5 percent of rate; the verifier +0.17 ms per warp. Gain: the stored-dataset chip's per-joule edge over the 5090 falls from 5.6x to 2.1x at a chip core equal to the GPU's. Alternative: wait for the 9070 XT and the 4060-class rows (both owed) before the gates, since a small card binds near 100,000 by its ALU budget (model).
  2. The reserve order R1 perm, R2 popc and clz, R3 shfla, R4 bfe, R5 shifts, R6 sel, R7 andn, R8 mm8 (W_new = 4 each; mm8's era-4 unlock kept as the named exception or moved to era 8), and R0 the per-day derivation as a reserve family (dr368 the safe draw; dr736 after O-1.14).
  3. Commission the mixer cryptanalysis: USD 80,000 to 160,000, the brief and the reviewer shortlist in funding.md (item 3); it should name random ARX programs (item 2's class) beside M_r. No outreach has been made.
  4. The bounty trigger: escrowed and the benchmark live before daily issuance crosses USD 20,000 a day (funding.md rule 5); the detector is the clock (quiet on the devnet, max pairwise r 0.10 to 0.53 against the 0.8 edge).
  5. The live observer: the detector and the vendor-share hooks reach it only through a push to master (autosync); the founder's word on the push, then one restart and the first live rows into this file.
  6. The 5090 clock rows (-lgc at 2,781 / 2,472 / 2,163 / 1,854 MHz): an elevated job on PC 2 would ask for administrator rights at the keyboard (the 5 October prompt class); not run without the founder's word.
  7. PC 1: the 9070 XT rows for items 2, 6 and 8, the detector's band and the FPGA ranking's AMD line are all owed on PC 1's release.
  8. The job tooling: one card-key form everywhere (the settings.json key carries the device index) and a CI check that fails a job script posting a key without it (the class fix for item 2's loaded-card run).

Main's decisions on section 6 (18:0x UTC, 6 October 2026)

# Decision Record
1 The public claim: the sentence deployed on the hero at 16:21Z ("In our public model the strongest chip reaches 5x to 9x per joule against an RTX 5090 today, about 2x once the lever now in its gates ships") plus the litepaper's long form; "under 2x" nowhere docs/evidence.md row 17 (the claim, its sources, draft (a) of this file chosen); the review finding behind it: docs/review/round-4-reddit-2026-10-06.md item 3 (Serious), flipped by the measured fact
2 The cut: yes, after P1's rehearsal passes and 0.3.14 has run a clean day; the fleet agent owns P1's run section 5a
3 R0 (the per-day derivation, dr368 the safe draw) and the reserve order R1 perm to R8 mm8: GO as proposed, with the once-a-day item module recorded as a requirement on every vendor (NVRTC +1.1 s, AMD OpenCL +2.0 s per pack) counter-asic-3-derivation.md, counter-asic-3-reserve.md
4 The cryptanalysis spend, USD 80,000 to 160,000: AWAITING THE FOUNDER (his money decision; put to him with the brief on a quieter day, not tonight) funding.md
5 Push: ca3-coord merged into master through CI (nothing activates: v4 sits behind the override; the detector and vendor-share hooks go live on the observer's next restart) the merge commit and the CI run, below
6 The AMD watts: on the runner's --cards-off mechanism, next cut section 6a
7 The 2019-class core (O-1.14): a Windows igneum-pow job on the US laptop when it next appears on the relay owed list

6a. A rule from the run (main, 17:5x UTC, from the watts job's failure)

A script never switches the installed app's cards: a POST of enabled false to /api/cards from a script is the same class as /api/pause from a script (a script that dies leaves the box degraded, unattended). A job that needs a card alone asks the runner for it: the runner's --stop-miners grows a --cards-off <keys> that posts the exact settings entries off before the script and restores them with their own flags and identities on ANY exit, as it restarts miners; tools/ci/playbook-quit-check gains the api/cards enabled-false pattern so the shape fails CI. Both land tonight (the PC 1 worker, branch ca3-pc1-amd); the four PC 1 scripts that carry the shape move to the flag; the AMD watts row re-runs only on the runner mechanism, after the app that carries it is installed (owed to the next cut).

7. Unverified and owed

Item Owed Why
1 the 5090's watts at the hash alone: LANDED from Ember Tune run 5 (job ember-tune-pc1-5, PC 1, 15:30 to 15:38Z, elevated, nvidia-smi -pl set directly, the clock unlocked at 2,850 MHz core and 13,801 MHz memory, 75 s a step, MH/s wall from the worker's STATUS lines): 575 W cap 127.38 MH/s at 309.9 W (0.411 MH per W); 518 W 99.32 at 313.6 (a stall inside the hold); 460 W 123.11 at 312.2; 403 W 127.38 at 310.9; 400 W (the floor) 127.38 at 311.3; 64 to 65 C. The cap never binds on this hash (310 to 314 W under every limit), the power knob is flat at 0.41 MH per W, 2.44 microjoules per hash in the app on PC 1 beside two other cards; the clock caps were not measured (the watchdog ended the run at the first clock step, fixed on ember-tune 5e4ef43) and the card was left clock-locked at about 2,781 MHz until a reset (not a card under test in the PC 1 AMD jobs). The earlier state: the run of 07:21 to 07:56Z produced no 5090 step (its second engine never mined; re-run pending the founder); the 4 October PC 1 log (miner-eff record, run win-ae432dc7-20261004-164723) gives p95 290 W at 124 MH/s in the app under a 460 W limit, and the card's cap floor is 400 W, so a power cap CANNOT bind on this kernel: item 1's 326 W denominator is a peak with the prover on, the hash alone is about 290 W (2.34 microjoules at 124 MH/s), and the lever that can move the watts is the core clock, now in item 8's PC 2 job (-lgc steps at 2,781 / 2,472 / 2,163 / 1,854 MHz); every DRAM energy figure is a streaming figure applied to random reads; the 9070 XT rows PC 1 not released; no chip measured
4 the 9070 XT rate band for the detector; the coinbase card-model tag (0.3.12) so the chain-attributed band needs no fleet log; the public testnet's first-week baseline (history check 2) PC 1 not released; a miner change
5 a rented FPGA hour (the soft-overlay reads-in-flight number is a model on cited HBM figures) no FPGA in the fleet
6 the 9070 XT step costs PC 1 not released
4 + 7 the live observer restart with both hooks, and the first live detector and vendor-share rows needs a push to master (the founder's word)
2 the 2019-class core (O-1.14), which decides dr736 against dr368; the once-a-day NVRTC module for the item function (required before any activation); cryptanalysis of random ARX programs; the loaded-iGPU tier's build with the day program; the 5090 absolutes re-run with the card quiet (ratios stand) unmeasured; unimplemented
8 the 9070 XT and 4060-class rows (where a small card binds); the 5090 clock rows (an elevated job); the 5090 at a 575 W cap (model only); the Mac package watts (IOReport gives GPU + DRAM, Ember's 38 W approximate); the chip side's k, lane area and 28 nm scaling; the Metal fuzz, edge and stats runs and gates G2, G4 to G6 on the class; the acceptance rule's reading of the block PC 1 not released; no elevated job; the gates are the next step on the founder's word
6 mm8 as a chain on Apple (Metal 4 matmul2d; the Mac's Swift toolchain has no tensor API); mm8's exactness on AMD (the gfx12 WMMA fragment layout; an empirical layout probe would settle it in one job); the 5 percent rule per family with the family live (argued only); the RDNA ISA guides unread (mnemonics from LLVM's tables). The 9070 XT step costs themselves are CLOSED (run e)
1 the DRAM energy figures are streaming figures applied to random 32-byte reads; the GDDR7 burst and HBM3 tFAW are behind the JEDEC paywall; no chip has been built or torn down
all every AMD RDNA 4 number in this run PC 1 is the founder's desk today. 16:0x UTC: the RX 9070 XT is back on PC 1 (amd:gfx1201, 16,304 MiB) beside the 5090 and an RTX 4070; main has asked for the PC 1 jobs to be PREPARED, not published: (1) G1 AMD plus item 8's ladder on the 9070 XT (about 15 min, the card alone), (2) item 6's family step costs on AMD (about 3 min), (3) item 2's dr736 build and compile on AMD (about 3 min), (4) optional: the 4070 ladder (about 10 min); branch ca3-pc1-amd (1f33cc6, e054ed7, merged): the four scripts pass every CI check, the kit zip sha256 a70fce5b... verified, the AMD watts readback is igneum-gpu-telemetry.exe (ADLX board watts); the commands and the row map in tools/ca3-pc1-amd/README.md; published one at a time on "go PC 1 AMD" after the 0.3.13 update and the Ember table run, about 33 min of PC 1 in all

The 0.3.15 cut (class v4), in flight (the shipper, with the node lane)

Step State
The node: the signalling fork 0562a7f2 merged onto 0.3.14's node tip 4c6b129d = f86a33c0 merged; the header processor byte-identical between 0562a7f2 and f86a33c0 (the class signal read after the cheap checks, as before)
The suite on igneum-build-1 one test, cheap_checks_run_before_the_pow_engine, failed at its LAST assertion (the genesis-day hint), not the four cheap-check assertions: a test race on two process-wide things (the engine captured at consensus construction inside the test's install window; the live day length another test can swap) that the box's 96 test threads hit and PC 2's 24 never did; the fix is tests only, fork commit 791ff22c on ca3-v4-order-fix from f86a33c0 (an install_engine_lock in kaspa-pow held across the window by both installing tests; the day assertion made the processor's own promise), with the shipper at 18:5xZ; the single test 1 of 1 on the box (43 s); the full kaspa-consensus run from the fix worktree on the box, its line pending
The order, with the shipper's measurement on the 0.3.15 Mac binary (fork f86a33c0, no suffix, no peers) THE DIGEST MOVES AT PUBLISH 1: on the live thirteen-field file 0.3.15 reads c09c3e48... where 0.3.14 reads b18ed271... (the two v4 fields fold into the digest at never when absent), so publish 1 (binaries only) is itself the one-sweep handshake split and every node moves inside one window there, miners first, the hand nodes and the seeds last; publish 2: the SIXTEEN-field object (the live thirteen plus 0.3.14's exec_restart_state_root, the floor 226,800 from DAA 209,458 at a 19:47Z publish, the window 86,400; digest 2c1162e2... on 0.3.15; the node's lines "Program class v4 from the override file: active from epoch 63 (DAA 226800)" and the 86,400 window at 9,500 bps) only once every node reports 0.3.15; a 0.3.14 node given it exits at parse ("unknown field program_class_v4_activation_daa"), confirmed on the Mac binary as the rehearsal found. The node lane's tests-only fix 791ff22c merges into the release node. MAIN'S RULING (19:0x UTC): publish 1 must not be a handshake split. The node lane adds to ca3-v4-order-fix a digest-compat change: an ABSENT optional field contributes nothing to the digest, so 0.3.15 on the thirteen-field file prints b18ed271... and peers with 0.3.14; the binary rolls out with no window; the sixteen-field file at publish 2 is the one sweep (miners first, the hand nodes and the seeds last, only when every node reports 0.3.15); the sixteen-field digest is re-read on the fixed binary before publish 2. IMPLEMENTED (fork ca3-v4-order-fix 713ef876, with the shipper): the two v4 fields enter the digest only once set, the window's default 0 on every network, the no-file devnet digest back to c562d70e...; the box's suite on 713ef876 kaspa-consensus 98 and consensus-core 111 + 7, 0 failed; pinned in a new test: the thirteen-field live file b18ed271... (0.3.14's value), fourteen fields 23e76936..., sixteen fields (the pin, floor 219,600, window 86,400) 1dddfa55...; the rehearsal unaffected by construction (its object sets both fields, so a15db4f0 on devnet-400 stands); the two harness lines on real nodes both PASS (the fixed Mac binary of 713ef876 against the 0.3.14 binary, 18:58Z, infra/fast-time/digest-compat.mjs, the P3 row on ca3-v4-node 38ac2a3): COMPAT, a fixed node and a 0.3.14 node on the live thirteen-field file print one digest and peer; REFUSAL, the fixed node on the sixteen-field file prints another and is refused with the handshake's own "consensus params digest mismatch" line on both sides; on the devnet id the sixteen-field object re-reads 1dddfa55... (the pinned value), the thirteen-field file b18ed271..., no file c562d70e.... The rehearsal's flip (about 19:01Z) and floor (about 19:21Z) are the PASS clock main holds the founder to
The fork's final tree for 0.3.15 (ca3-v4-order-fix, four commits) 791ff22c the order-test race (tests only); 713ef876 the digest once-set rule; 17c60367 the signal stamp and read gated on both v4 fields (header version 2 on the live file, 1026 only with publish 2's object); 7961c5f1 a sync request below a pruned node's retention answered as SyncManagerError::BlockBelowRetention to the peer, never an unwrap (the hub's 19:57Z panic: a remote crash vector against every pruned node since the first one). The shipper built 0.3.15 from 7961c5f1 on all three platforms, the digests unchanged, the six-crate suite green. The node-compat gate (ca3-v4-node 4d7e677, infra/fast-time/node-compat.mjs, 20:19Z): a mining new node beside a 0.3.14 node on the live object PASS (one digest on five nodes, the new miner's 75 blocks accepted by the old hub, header versions 2 only, 195 blocks on every node including the clean join through the old hub, the old node served from genesis by the new one, the new node restarted and re-synced); the canary binary 713ef876 on the same gate FAILS with the fleet's exact reject lines (the known-failed case). Ledger rows N1 and N2 (security, conceded, dated, with the fixes) in docs/fud-ledger.md. The audit pass landed (fork ca3-v4-deps f8f0f1df from 7961c5f1, Cargo.lock only, the shipper's 0.3.15.1 node change): h2 0.4.20, quinn-proto 0.11.19, rustls 0.23.45, crossbeam-epoch 0.9.21, ruint 1.20.1; cargo audit on the box 6 vulnerabilities and 16 warnings before, 1 and 16 after (the one left tracing-subscriber 0.2.25 pinned through ark-groth16, a major bump, named and not taken); the six-crate suite green on the new lock (99 / 111 + 7 / 20 / 15 / 18 / 33); row P5 on ca3-v4-node 536e084. The receive-side fix f1ea7a38 (fork ca3-v4-order-fix on 7961c5f1, 21:39 UK, to the shipper 21:46 UK; the box line kaspa-consensus 99, consensus-core 111 + 7, rc 0): with the window or the floor absent, a header's version must be exactly 2 (0.3.14's rule), so a 1026 header is refused before the engine with WrongBlockVersion(1026, 2) and never relayed; with publish 2's object both bytes are read as designed; the test inside cheap_checks_run_before_the_pow_engine; the gate re-run with a poisoned peer in the topology (a 713ef876 node mining 1026 blocks into the new node, 20:42 to 20:45Z) PASS: 12 refusals with 0.3.14's exact line, none relayed, the old hub's chain holding version-2 headers only, every clean node at 180; stale blocks on the live devnet: a 0.3.14 node holding them is disconnected by its 0.3.14 peers by their own rule, new nodes are immune, the fleet wipes the poisoned datadirs; ledger N1 extended; the shipper rebuilds once on f1ea7a38. The node lane's further queue (the peer-driven unwrap class with a sync-request fuzz gate, the 7-window signalling rule, the Horizon items, the stale-block nuisance-peer case) reports to main: it is the cut's and the ledger's, not this file's
The founder's go given in advance for tonight; publish 1 on the 0.3.15 canary line, publish 2 once every online node and worker reads 0.3.15
PUBLISH 2 LIVE AND READ BACK (22:43Z, the shipper) the sixteen-field object (the live thirteen, the exec pin, program_class_v4_activation_daa 831,600, program_class_v4_signal_window_daa 86,400), digest eada4bda8aa8368c2b2c3d17744bc7a70a0ff0e996dad681884d3ac5de1207eb on igneumd/2.1.0-f1ea7a38, on the fleet's 14 standing boxes, both PCs, the hands and the seed; every node prints "active from epoch 231" and the 86,400 window at 9500 bps; THE VOTE OPENED at DAA 223,667. Two facts from the way there: 0.3.15's node gained two gates beyond the signalling fork (the stamp AND the header-version rule both gated on publish 2's object: 17c60367, f1ea7a38) after the live canary found a 0.3.15 node writing version 1026 on the thirteen-field file and then accepting one from a poisoned peer; and the floor sits a week past the publish (831,600) because the floor flips unconditionally on this node (the 0.3.17 P2 rule applied early). The rehearsal chain igneum-devnet-400 ends on this line (the fleet agent told)
A FAULT SINCE PUBLISH 2, fixed (the node lane, 03:03 UK, fork ca3-v4-0317-fix 90aaf38e on 02d15a87, with the shipper) protocol/flows/src/ibd/flow.rs sync_and_validate_pruning_proof compared the syncer's relay block's WHOLE header version with the block version (upstream's guard) while the consensus rule reads the low byte when the signals are active, so a fresh node on the headers-proof IBD path with the window object refused every legal 1026 relay block; the live f1ea7a38 has the same line, so no fresh node joined through that path since the window opened at 22:43Z (nodes syncing without a proof, under 419 headers, were unaffected, which is why the hands moved). The fix: one shared reading, igneum::header_version_acceptable, at both sites; the known-failed unit test first (1026 against 2 legal with the signals, refused without); consensus-core 123, the header tests, p2p-flows 34 green on the box. Owed: the two-daemon integration test with the window object over relay and IBD (next on the 0318 tree). It alters no consensus outcome and the digest is untouched. MAIN'S DECISION: 0.3.17 is a node-only hotfix on the 0.3.16 app tree (the fresh-join fix, node b3c228fa), taken by the canary, then the Mac, PC 1 and PC 2 by update-now on the shipper's line; the feature tree becomes 0.3.18 and decimals 0.3.19

7a. The two fast-forwards to master (decision 5)

Push Commit ci windows-ci
1 88f5026 (ca3-coord merged with master: Counter ASIC 3.0 complete, the two CI check fixes, the close) GREEN (37508680115) red on "payload inputs (payload-inputs.zip from the downloads host ...)", red since 630b537 at 17:51Z, the shipper's 0.3.14 payload on the downloads host; the last green windows-ci 2cf8851 at 15:53Z; untouched by this branch
2 0396580 (35776fe: the runner's --cards-off with the restore on any exit, the quit-check's rule 2 with the dated allow list, the stripped PC 1 scripts; plus the executable bit on the quit-check) GREEN (37509530709) cancelled (37509530516): superseded by the build-server fix 3e6a488 pushed to master minutes later; the payload-inputs step is the shipper's to turn green with 0.3.15's payload

7b. The final row: the P1 rehearsal PASSED (6 October 2026, 19:33Z)

Check Result
The flip by miner signal the identical line on all 52 signalling nodes at epoch 2: 10,000 bps over 600 DAA, 599 of 599 blue blocks, one seed block
One program id per epoch across the boxes, equal to the CLI's class v4 id, differing from the v3 id epochs 2, 3 and 4: 24304f0788ea9408, cc266b4f5dbc3447, 634018bab5e5f283 (the v3 ids d8927052c764f00b, de3a34f1f2130228, 170e3aa4b2f69d60); the pre-flip epoch 1 generator 3, id b237a661a3c7f7c1
Rejected 0 PoW rejected on all 16 nodes over the run; every miner mismatched 0, rejected 0
The stale old-binary box refused by digest at every connect (11 refusals, 22 mismatch lines), never a peer; on the full file refuses at parse and exits
Blocks on v4 on every box from the 19:15:47Z resume on the generator-4 worker; about 1.6 blocks/s
The floor crossed at DAA 2,400 with v4 already in force; the chain mined through it; one chain, no fork at the 19:34:54Z sweep
G2 serve mode on the epoch-2 v4 pack 1,024 of 1,024, digest 7bf77506..., the Mac recheck MATCH line for line
Cut-critical an old worker refuses a generator-4 pack, so publish 2 waits on every node and every worker; a 0.3.13 node exits at parse on the file; publish 1 carries no handshake split

The founder gave the go in advance for tonight: the shipper runs publish 1 on the 0.3.15 canary line, then publish 2 once every online node and worker reads 0.3.15, miners first, hands last; the rehearsal chain ends on the line that publish 2's digest is read back on every node (its miners off, the boxes to the standing roster or run A). The evidence folder's last entry: counter-asic-3-gate/class-v4-20261006-rehearsal-PASS.json. The public bench-log entry (numbers only, no box names): docs/bench-log.md "6 October 2026, Counter ASIC 3.0: the class v4 rehearsal". The 3.0 lane is closed.

7c. Reopened on the v4 seam, 7 October 2026 (morning): AP-F8-1, the item read map's skew

Item State
The finding (the attack-pass lane, F8 phase D, one class v4 program, 2^26 nonces; docs/analysis/attack-pass/f8-uniform.md on branch attack-pass) the top 0.1 percent of items take 0.520 percent of reads against 0.115 uniform (4.05x); the top 1 percent 2.49 (1.37x); one item 0xca5b92 takes 78,479 reads, 153x the mean; read site 15 feeds 6.37 percent of its reads into the top 0.1 percent in all 8 iterations; the excess grows with N. The ask: a generator fix on the v4 seam with the gate "top 0.1 percent within 1.2x of uniform over 2^26 nonces on 64 seeds"; the attack-pass lane re-gates with tools/attack/f8-uniform
The lane's framing class v4's item map is not designed to be uniform per program: layer 8's per-site windows (k_off = below(3): the whole dataset, a half or a quarter per site, under the era stride and interleave) concentrate a quarter-window site 4x on its quarter, which is the 4.05x; the null is the window model from the program's own 16 draws; the 153x item is the number to explain (coinciding windows under the era mapping with a stated tail, or a low-entropy source at site 15, a fault); the chip consequence a 1.7 MB hot-set cache serving 0.5 percent of reads, under one percent of rate
The cut consequence v4 is on the live devnet's vote and the class lives in the binary: any generator change to v4 is a class change (new vectors, the six gates) that must reach every node before the flip or the chain splits; unless F8's phase E census shows a fault beyond the window model, the answer is the documented null and, for a tighter tail, an acceptance bound in the next class, not in v4; a fault beyond the model is main's and the shipper's decision (a class amendment before the flip, or the flip held by the floor)
Who the hash lane, branch ca3-v4-uniform from master: the model, the reproduction with F8's harness on the v4 packs and the mixer harness's 200 programs, the census, the re-priced row; a fix only on a fault
THE ANALYSIS (the hash lane, ca3-v4-uniform 095f84a7, docs/analysis/ca3-v4-uniform.md, the tool on igneum-build-1) the window model moves the null from 0.115 to 0.160 percent (1.39x, not 4.05x); the rest is a FAULT beyond it: site 15 reads a register last written by or r6, r4, so all-ones recurs at (3/4)^32 per read and the era map sends it to F8's hottest item exactly (the popcount model predicts 77,348 all-ones reads against 78,479; the top-0.1-percent share 0.58 against 0.52); it passes the acceptance rule because part (a) takes any write as a fresh source and part (c) counts saturation on final values only. The census of 1,024 chain-shaped v4 programs: 96.6 percent carry a lossy-sourced load (or, mul, mulhi as the last writer), 48.5 percent an or-sourced one (0.30 percent of all reads per site), 4.9 percent an or-of-or chain (4.6 percent of all reads on 0.1 percent of items); F8's 1.2x gate fails 96.6 percent of today's programs. Worth to a chip: 1.07 MB of SRAM ($0.25) serving 0.52 percent of a typical program's reads and 4.6 percent of the worst class's, at most 1.005x and 1.048x in rate; the ceiling under rule (c)'s 120-of-128 floor one site repeating its item in all 8 iterations, 6.25 percent of reads, 1.067x in 64 bytes; the 2x margin stands; the public line says "bounded at 1.067x", not "uniform" (the public text corrected)
The two options, priced, STOPPED at the coordinator for the founder's word A: a 0.3.19 class amendment before the flip (the generator draws a load's source from the registers whose last writer injects): a new program stream, new vectors, the seven gate packs re-exported, the six gates again (G1 to G3 and the verifier about an hour on the Mac and PC 2; G4 to G6 the node lane), every node before the flip under the one-box-at-a-time rule; the risk a node that misses the build splits the chain at the flip. B: hold the flip at the floor with v4 as it is; the bound documented; the source rule to class v5: a hot set worth up to 1.005x on about half the hours and 1.05x on 5 percent, 1.067x at the ceiling; no chain risk. The number: 1.067x at the ceiling against the 2x margin. The lane recommends B
The v5 bound (sent to the v5 lane) H = W_0.1 (the window term, 0.115 to 0.251 percent) + the sum over load sites of h(last writer) (or 0.30 percent, an or chain 4.5, mul 0.067, mulhi 0.049, an injecting op or a rotate 0), H at or under 1.2 x W_0.1, which is the static rule "every load's source was last written by an injecting op or a rotate"; as a rejection it costs 96.6 percent of candidates (about 30 attempts per seed), as a generator draw nothing; gate F8's 64-seed census with the saturated-source count
THE FOUNDER'S WORD (15:2x UK, 7 October): OPTION A, "do this but limit the testing, get it pushed" the class v4 amendment: a load's source drawn only from registers whose last writer injects or is a rotate (the v5 rule applied now), a new program stream and vectors, the seven gate packs re-exported, the amended class with its own generator stamp; rides 0.3.20, the feature node (release-0.3.20-node = dc141409; 0.3.19 is an app-only cut with nothing of ours), on the shipper's line. The rollout arithmetic for the flip clock (the shipper): the standing fleet's one-box-at-a-time rollout took 32 minutes for 14 boxes (04:56 to 05:28Z, 7 October), the hands and the seed about 3 minutes after the miners, the Mac and the PCs within minutes of the publish; every 0.3.20 worker must accept the amended stamp before any flip. Owners: the hash lane (ca3-v4-amend: the generator, the vectors, the packs, the pairing on the box, one G1 run on PC 2, the ledger row), the node lane (release-0.3.20-node: the stamp agreed with the hash lane, the split-protection mechanism and the earliest flip time, the digest test, the mixed-version Devnet 2 gate), the attack-pass lane (the F8 census at 2^24 on the new stream, the gate 1.2x of the window model over 64 seeds), the shipper (the cut, the rollout order that sets the earliest flip). Testing limited to what prevents a split and proves the fix; G2, G3, the ladder re-measure and the rest of G4 to G6 OWED. THE STAMP agreed (the node and hash lanes, 7 October afternoon): generator 4 with sub-version 1 inside igneum-pow's id function, so the amended v4's program id for a seed differs from the old v4's (the old devnet epoch-0 id c120d7963abdcd96 pinned as the must-differ vector in kaspa-pow's test). SPLIT PROTECTION SETTLED (the node lane, plan section 6.6, ca3-v4-node fa5bc9e6; the node side on release-0.3.20-node): a fresh object byte. CLASS_SIGNAL_V4 is 5; the amended binary stamps 5 and the tally counts a block only at byte 5 or above; object 4 was stamped only by the unpublished dc141409 canary, so no published block carries it and a byte-4 block never counts; a node of the 6 October stream that sees byte 5 counts it as v4 (its rule is at least 4), flips to its own stream at the same epoch and forks ALONE (its blocks fail the amended id check, generator 4 sub-version 1 inside every id; the amended blocks fail its own), ours to upgrade in the sweep; object 6 is class v5's; the two holds already in the rule keep the window shut until every node is on 0.3.20 (a node stamps and tallies only with both v4 fields in its file; the fields publish only after the one-sweep rollout); a lagging worker refuses the amended pack at packcheck and mines nothing after the flip, costing that box, never the chain; no extra window hold: seven full day-windows are the hold. THE EARLIEST FLIP (approximate, measured 09:40Z: DAA 270,659, 1.095 DAA/s over 25 hours, 1.165 over 4; epoch 3,600, lead 600; seven windows 604,800 DAA wholly after the sweep's end D_s = T + about 40 minutes; the flip epoch the first e with 3600 e - 600 >= D_s + 604,800): T + 6 days 10 hours to T + 6 days 11 hours UK; for a publish at 12:00 UK on 7 October, 13 October between 22:20 and 23:10 UK (about 13:00 UK if the 4-hour rate holds). The floor as it stands (831,600, about 13 October 09:00 UK) would fire before any seven-window signal from a publish today completes, so it moves by the 0.3.16 rule to the publish DAA + 604,800 rounded up to the epoch boundary (882,000 for a 12:00 UK publish), firing about 30 minutes before the earliest signal flip: either way about 6 days 10 hours after the publish, never before every node has had the sweep plus a week. THE CLOCK (the node lane, 11:3x UK, after a Mac reboot moved its runs to the box): the 0.3.20 node line (dc141409 plus the proof archive aea0ca5c plus the amended v4 at object byte 5, igneum-pow at the hash lane's a0aaca92 beside the fork on the box) tested on the box, committed on release-0.3.20-node, pushed to the mirror and origin, igneumd and igneum-miner built, the tip to the shipper: about 12:00 UK; the mixed-version Devnet 2 gate (node-compat.mjs on the box, the amended node beside the 5899f603 pair for ten minutes) and the digest test (digest-compat.mjs): about 12:45 UK; the object-byte pin 5 unless the v5 lane answers both lanes with another assignment (v5 at 6 proposed). THE HASH SIDE on ca3-v4-amend (tip 8c728ca3, read from the branch 14:0x UK; the hash lane's own report pending): 1748fd1d the PC 2 G1-only playbook; e1f48d63 the fud-ledger entry AP-F8-1 (the fault, the founder's ruling, the amendment, the split protection, the owed tests); d8859522 the G1 line (the eight fingerprints equal on the RTX 5090, self-test PASS) and the node lane's signal byte 5; 4aa0c665 the v4 unit test following the amendment; 965d9e96 igneum-pow taken from release-0.3.20's 3f1652bf (the ladder's chain_program_shadow with the reps argument, never on master) with the amendment re-applied, the seven packs re-exporting byte-identical; 8c728ca3 the source rule keyed on the class with the shadow's pass count set aside, so every ladder rung draws under it (the fork's ladder test). The shipper took this igneum-pow tree into release-0.3.20 (00249643, byte-equal); nothing after 8c728ca3 touches igneum-pow. THE VECTORS AND THE PACKS (read from the branch and its ledger entry, 14:1x UK): the seven amended v4 packs (v4-devnet-epoch0, v4-era-0 to 5) carry generator 4, sub-version 1, one program id 1a4230699a6b9c60 (the 2.0 one-id-per-seed rule across the eras; the old c120d7963abdcd96 pinned as must-differ); the v3 control mx8-devnet-epoch0 untouched (73bcbfe8ccf988f1, fingerprint 90f794dd556f7a3b); the seven 2^24 fingerprints, Metal equal to Apple OpenCL: 867dbc45cfb36b4d, 2146ecacc8c75a8e, fe52602393f6d3d4, 3b206471a13912b4, c3f03c4a5d7333aa, f1dfd7209f15bb97, 8c194da64fadf31d; the zip of the eight packs sha256 889ec99976d2728b4b5035bfa476032e5b6a13b928968fc45236d5f25084aa39; the per-pack vectors.json sha256 prefixes 756301bf (devnet epoch 0), 1b5f4568, d430cadc, 1a1b21d8, 460fff9e, 4a85d49d, f83a1196 (eras 0 to 5). G1 on the RTX 5090 (PC 2 job run-ca3-v4-amend-g1-pc2-20261007, 09:41:07 to 09:41:28Z, exit 0, the installed worker): every fingerprint equal to the Mac's (the seven above and the control), NVRTC 188 to 332 ms per pack, the 1 GiB build 38 to 49 ms. hash-gates.md's older table still lists the pre-amendment fingerprints (f410c731... and the eras), which no longer apply to the amended packs; the ledger entry is the record. THE FIRST GREEN (11:31 UK, the box): the kaspa-pow suite on release-0.3.20-node (dc141409 plus the proof archive aea0ca5c plus the object-5 change) against the hash lane's igneum-pow 8c728ca3: 17 passed, 0 failed; the amended devnet epoch-0 id 1a4230699a6b9c60 pinned equal and c120d7963abdcd96 differing, the ladder's rung test green under the rekeyed rule, the v3 control unchanged; the consensus-core and exec RPC suites follow, then the node line (commit, push, box build, the tip to the shipper), then the digest and mixed-version gates. CLOCK RE-CUT (the node lane, 13:0x UK): the node line now carries, beside the object-5 change and the vector test, the lane's 0.3.20 fixes from the day (isSynced from the hook's stamp, the lazy template snapshot, the weight-table cache, the submit path returning after the block task, the watchdog, the RPC fields), about 13:30 UK if the box suites are green; the shipper's fresh-join canary 60 to 100 minutes after the cut; PC 1 as its first machine about 16:00 UK at the earliest, approximate until the shipper names the cut; the earliest flip about 6 days 10 hours after the publish. BUILD-2 LINES (12:28 to 12:33 UK): consensus-core 123 passed (the 60x file test green with the ladder window and activation pinned), the behind test green, kaspa-pow 17 passed (the amended vectors, earlier on build-1), the exec RPC suite green, the flows and rpc-service checks green with the submit-path change; the 24-requester latency test's first run tripped an unrelated flapping-fork double insert (24 equal forks from one parent; the test now builds on the sink as a real miner does; the double insert owed to a small fork harness before it is called a bug); THE NODE LINE COMMITTED (13:1x UK): release-0.3.20-node = 8097d600 (dc141409 + the proof archive aea0ca5c + one commit) on the mirror, pairing igneum-pow 8c728ca3, the hash with the shipper; in it the amended class v4 as object 5 (CLASS_SIGNAL_V4 = 5, byte 4 never counts, the kaspa-pow vector test pinning 1a4230699a6b9c60 equal and c120d7963abdcd96 differing, the daemon's window line naming object 5 and sub-version 1) beside the day's fixes (isSynced from the hook's stamp, the weight-table cache, the lazy snapshot, the submit path, the 100 ms template wait); the suites green on build-2 (consensus-core 123, the exec RPC suite, the four finality tests including 24 requesters under 200 ms: the worst template 100 ms, the worst submit 102 ms) and kaspa-pow 17 on build-1. Next: igneumd and igneum-miner building from 8097d600 on build-1, then the two gate lines (the mixed-version Devnet 2 gate: the 8097d600 node mining beside the 5899f603 pair for ten minutes on the live file without the v4 fields, the old node accepting every block; the digest test: the thirteen-field file b18ed271 unchanged, the sixteen-field object re-read on the 8097d600 binary), expected about 13:30 UK; the shipper picks the cut point. THE DATE FIXED (the node lane, from the hub's live file, 13:3x UK): publish 2 of 6 October (22:49:45Z, digest eada4bda) already put BOTH v4 fields on the live devnet (floor 831,600, window 86,400), so the 0.3.17 fleet has stamped object byte 4 since 7 October 00:2x UK and the floor is live at about 13 October 09:00 UK, before any seven-window signal completes; a 0.3.17 node left on that file flips to the OLD v4 stream at epoch 231 whatever anyone signals, a 0.3.20 node to the amended stream at the same epoch, and the two never share an id, so each straggler forks alone there. REQUIREMENT for the 0.3.20 publish (with the shipper and main): a new file with the floor at the publish DAA + 604,800 rounded up (about 882,000 for a publish today), the digest moving, the one-sweep rollout replacing every 0.3.17 node before 13 October 09:00 UK; any node that misses the sweep is alone then; the earliest flip after that about 6 days 10 hours past the publish; plan section 6.6 amended today. IN THE 0.3.20 PLAN (the shipper, 13:4x UK): both requirements; the node pin by main's rule is the node lane's second commit (the claim floor, the listener watchdog, the claim RPCs, on top of 8097d600) if its suites, both gates and the fleet's 12 GB prover line are green by 15:30 UK, else 8097d600; igneum-pow 8c728ca3 either way; the digest read on whichever binary pins. THE LINE AT 13:5x UK: three commits on release-0.3.20-node, 8097d600 (the object-5 amended class v4 and the day's fixes), 6b94c823 (test-only: the stale PC 1 test from 500ddd66 inverted by the isSynced ruling; the FALLBACK pin, code byte-identical to 8097d600, so the module reads green whole) and 6a3432a3 (the app lane's key methods, the observer's claims, the settled claim floor, the listener watchdog); suites on build-2 on 6a3432a3's code (the whole finality module 25, the exec suite 29 with the watchdog test, the kaspad, flows and rpc-service checks; consensus-core 123 and kaspa-pow 17 earlier); the cut 6a3432a3 if its gates and the fleet's 12 GB settled-claim line are green by 15:30 UK, else 6b94c823; both binaries building on build-1, the two gates (the digest gate, then the ten-minute mixed-version gate beside the 5899f603 pair) on the 8097d600 build, lines about 14:05 UK. GATE NEWS (13:53 UK): on 6a3432a3's own digest gate the listener watchdog counted a bind failure (the four harness nodes share one exec JSON-RPC port) as a listener death and exited three of four nodes at 20 s, where 0.3.17 and 8097d600 only warn and live without the exec RPC; the digest facts came out first and stand (the thirteen-field file a89be8a7 on both binaries, the compat case; the sixteen-field object db9a85f9 refused with the mismatch line, the refusal case); the ten-minute gate on 6a3432a3 stopped as void for the same cause. The fix: a bind failure is a retry every poll, one line a minute, no death counted and never an exit, with a second watchdog test whose known-failed shape is the old rule's exit on a held port; the third commit and its build about 14:15 UK, its gates about 14:35 UK; the fallback 6b94c823's gates on build-1 on their own binary (no watchdog there), lines about 14:20 UK; ledger row N12 for the bind-failure class. A ROLL BLOCKER on every kept datadir (the node lane, 14:1x UK, ledger N13): the fleet started 6a3432a3 on a kept 0.3.17 datadir (pool-1's copy) and it died at start (virtual_state.rs:250, DeserializationError(UnexpectedEof)); the cause 10db4b61 on the 0.3.16 feature line added silent: bool to BlockRewardData under serde(default), which bincode ignores, so every build from 10db4b61 on (dc141409, 8097d600, 6b94c823, 6a3432a3, 09124180) reads a 0.3.17 node's virtual-state row short; no canary saw it because every canary wiped, and a one-box roll keeps datadirs, so it blocks the roll on every standing box, the hands and the hub whatever the pin. The fix on the line: the store reads the current layout first and on a deserialization error decodes the row as a v1 mirror, converts with silent false and rewrites it under the same key, with the known-failed test first; the fourth commit and build about 14:40 UK, the fleet's kept-datadir start on the fixed binary about 14:50 UK, its gates after. THE RULE IT ADDS for every node cut from now: a kept-datadir restart gate on a standing box's datadir copy beside the wiped canary. THE CANDIDATE PIN (14:2x UK): b7cc37e7 (8097d600, 6b94c823, 6a3432a3, 09124180, b7cc37e7; igneum-pow 8c728ca3): the N13 fix with its test green on build-2 at 14:04 UK and the kaspad check green, the build on build-1; the fallback 6b94c823 is no longer a pin for the one-box roll (it dies on a kept datadir like every build since 10db4b61): if b7cc37e7's gates are not green by 15:30 UK the honest fallback is 0.3.17's 5899f603 staying live. In flight on build-1: the earlier commits' gates, then b7cc37e7's own digest and ten-minute mixed-version gates on its binary with the read-back, lines about 15:05 UK; on the fleet the kept-datadir start on b7cc37e7 about 14:50 UK and the 12 GB settled-claim line 14:50 to 15:00 UK. Plan section 6.6 amended with the hard date (ca3-v4-node 9d763edd, merged to master); N12 and N13 on the ledger. THE GATES ON THE FALLBACK'S OWN BINARY (6b94c823, sha b1b7d47b, 13:56 to 14:08 UK; code byte-identical to 8097d600, so the amendment's node side): the digest gate, the thirteen-field file a89be8a7 on both binaries (the compat case, n0 peering n1 and n2) and the sixteen-field object db9a85f9 refused with the mismatch line (the refusal case); the mixed-version gate, ten minutes, one digest b0afb2ee on all five nodes, the 5899f603 hub accepting every block the amended node mined (146 new, 246 old, 0 rejected), plain header version 2 on the thirteen-field file, counts equal on all five through the two clean joins and the restart. Two FAILED checks, both the harness's own and fixed (36d3efdc): a refused peer's count read 1 with the reconnect in flight (now the minimum of five), and six address-in-use panics in the two old nodes because the second gate reused the first's ports the second they were sent SIGTERM (a 20 s gap now). CLOCK CORRECTION (the node lane, 12:12Z = 13:12 BST): every "UK" stamp it sent today was the box's CEST, an hour fast of BST; its lines read UTC from now. Restated: b7cc37e7's build about 12:15Z, its digest and mixed-version gates on that binary with the sha and string about 12:32Z (13:32 BST), the fleet's kept-datadir start on it about 12:25Z, its 12 GB settled-claim line 12:50 to 13:00Z; the shipper's checkpoint 14:30Z (15:30 BST), two hours of room. The 13 October date stands (derived from UTC DAA rates): the floor 831,600 about 08:00Z, 09:00 BST. b7cc37e7'S OWN LINES (binary sha256 bc28331abf21f4d5, the string read back on build-1 and on the fleet's pod): the digest gate 12:14:39Z to 12:16:18Z SUMMARY PASS (thirteen fields a89be8a7 on both binaries with the peers as the gate wants them; the sixteen-field object db9a85f9 refused with the line and no peer; the live file's digest eada4bda on the binary, unmoved); the kept-datadir start on the fleet's copy of pool-1's 0.3.17 datadir: the first start 12:17:12Z reads the v1 row through the mirror and rewrites it ("1 mergeset rewards"), the finality blob converts (1,747 locks), the node comes up on its ports with no panic; the second start 12:18:53Z reads first-try with no rewrite line and no panic; 6a3432a3's death on the same copy is the known-failed shape. The ten-minute mixed-version gate beside the 5899f603 pair runs on the same binary since 12:16:39Z, its line about 12:28Z; then the only line outstanding for the shipper's 14:30Z rule is the fleet's 12 GB settled-claim line, 12:50 to 13:00Z. AP-F8-1 RESIDUAL CLASS ON THE AMENDED STREAM (attack-pass lane 12:18Z on igneum-pow 8c728ca3, sub-version 1). F9 over 1,000,000 seeds: programs flagged (hot share at least 1 percent or 7 constant address bits) 1,871 (0.19 percent) against 11,696 (1.17 percent) unamended; worst hot share 9.66 percent against 17.3; mean 0.011 against 0.063 percent; 84 percent of the flagged programs and the whole or-saturation tail gone. F8 at 30 of 64 seeds: nine over 1.2x of the window model (p31 29.3x, p11 5.5x, p19 3.3x, p6 3.1x, p23 2.0x, the rest 1.3x to 1.6x); the 64-seed 1.2x gate is heading to FAIL on sub-version 1. Mechanism, confirmed on the two worst seeds: an all-ones load source (image 0x0ca59e4c under the era map) delivered through a writer the source rule counts as entropy-keeping, a rotate (rotl and rotr map all-ones to itself) or a load whose own source was saturated, with the saturation made one or more writes upstream by or. The rule looks one writer back; it must look through saturation-preserving writers or test the source's values. The ceiling has not moved: rule (c)'s 120-of-128 floor still caps any program at one saturated site, 6.25 percent of reads, a chip edge of at most 1.067x, and the residual (worst seed two sites at 0.53 and 0.56) sits inside it. THE SENTENCE "no lossy-sourced load by construction" IS HELD: it goes in no plan row and no ledger entry as true; sub-version 1 removes the or-source class and bounds the rest. MAIN'S RULING (13:2x UK): 0.3.20 ships object byte 5 on sub-version 1 as it stands, strictly better than the old stream the live floor flips to on 13 October; the fix is sub-version 2 on ca3-v4-amend (object byte 6 or whatever the v5 alignment leaves free) with both fixes: (F1) the static rule made transitive (rotates do not keep entropy; a load keeps entropy only if its own source did; one draw change, no attempts lost) and (F2) the dynamic source check (saturated load SOURCE values counted per site over the 64 units' 16,384 evaluations, rejected above 163 of 16,384, the same 1 percent the final-value rule uses; costs attempts on about 0.2 percent of seeds; rides with F1 because an or-written source is all-ones only (3/4)^32 of the time). Gate before sub-version 2 is proposed, run by the attack-pass lane and not by the hash lane: the full 64-seed census under 1.2x on every seed and the hot-set census. Hash lane's estimate about an hour its side (implement, re-export seven packs, vectors, crate suite, pairing, one G1 on PC 2) plus the node lane's vector re-pin and the attack-pass re-gate. The flip floor for sub-version 1 is expected to move (the founder's word) so the chain never flips to a stream that fails this gate. Also recorded: the crate suite at 8c728ca3 100 of 100 on the box (rc 0, 77 s); the pairing against the fork at dc141409 compiled and ran 15 of 16, the one failure the fork's own pre-amendment assertion (base equals v3's, igneum.rs:972), which 8097d600 on the release-0.3.20-node line turns into assert_ne; the pairing re-runs at b7cc37e7, its line to follow. CORRECTION (the attack-pass lane's own retraction, 13:3x UK): the F9 hot-set figures above (1,871 of 1,000,000, worst 9.66 percent, 84 percent removed, the two or-then-rotate listings) are WITHDRAWN: F9's harness draws through candidate_class with its own era class, outside candidate_from_words_class where the source rule lives, so it measured the old stream (the 8c728ca3 binary prints the identical program to the sub-version-0 binary for its worst seed). F8's 64-seed census on the chain path (pairing verified on 1a4230699a6b9c60) is the valid re-gate and STANDS: at 30 of 64 seeds, nine over 1.2x of the window model (p31 29.3x, p11 5.5x, p19 3.3x, p6 3.1x, p23 2.0x, p4 1.6x, p10 1.5x, p26 1.3x, p25 1.3x). The residual mechanism on the amended stream: a load-after-load chain (a saturated source reads one fixed word, which is the next load's address), admitted because a load injects; and the rotate-preserves-saturation path (generator.rs sets entropy_kept true for a rotate whatever it rotated), correct in code and a second admitted path if it occurs on the chain stream. Sub-version 2 must close both: dataflow freshness per register (a load fresh only if its source was fresh; add, sub, xor, mad, shfl fresh if either operand was; rotates only if the operand was; or, mul, mulhi never) plus the (c') count of saturated load sources per site as the backstop. The STOP holds on F8's evidence alone; the options and the 1.067x ceiling are unchanged. The sentence "no lossy-sourced load by construction" waits on the sub-version 2 census verdict and stays out of every public text until then. SUB-VERSION 2 IN BUILD (the hash lane, ca3-v4-amend, on the coordinator's direction, 13:4x UK): F1 (dataflow freshness per register, keyed on the class v4 shape on every draw path, era or not, so the candidate_class path and the chain path draw one stream) plus F2 (the (c') count of saturated load source values per site over the 64 units' 16,384 evaluations, rejected above 163, keyed on the same shape so v2 and v3 verdicts do not move); PROGRAM_SUBVERSION_V4 = 2, new ids, the seven packs re-exported, recheck.rs with 1a4230699a6b9c60 and c120d7963abdcd96 as the must-differ pair. Clock (UTC): the commit on the branch by 13:30; the crate suite on box 2 and the pairing against b7cc37e7 by about 13:50 (the pairing's vector test fails on the fork's sub-version-1 pin until the node lane re-pins; the compile and the other 15 are the pairing evidence); the G1 job on PC 2 under --cards-off by about 14:10, lock permitting; then the attack-pass lane's full 64-seed census and hot-set census on the chain path. Two consequences stated in the commit: the rule on every draw path moves the no-era sh256xN ladder packs' stream (packs-ca3-shadow's seven 256-block packs re-export with new fingerprints; the measured rates stand as the old stream's), and the class v5 lane's pinned string-seed packs move when it merges sub-version 2, so it re-exports them then. 0.3.20's sub-version-1 packs, ids and fingerprints untouched. OBJECT BYTES SETTLED (main, 13:5x UK): byte 5 = class v4 sub-version 1 (0.3.20), byte 6 = class v5 (pinned: class-v5 16afd0a0, class-v5-node 699db5a2, the flip case passed on 6,6,6; the v5 lane stopped), byte 7 = class v4 sub-version 2; the node and hash lanes told. b7cc37e7's MIXED-VERSION GATE: FAIL, the binary not the harness (12:16:39Z to 12:27:21Z, sha256 bc28331abf21f4d5, the string read back). Before the restart step everything held: one digest b0afb2ee on all five nodes, 268 new and 392 old blocks accepted, 0 rejected, header versions plain 2, counts equal on all five at 324 and 502 through both clean joins. At the new node's restart (12:24:19Z) it died at once on its own datadir ("IO error: While lock file: .../datadir/meta/LOCK: Resource temporarily unavailable", conn_builder.rs:167): the previous process was still shutting down, because the listener watchdog added on 6a3432a3 sleeps its whole 10 s poll before checking shutdown, so every node on the line since then takes up to 10 s longer to stop than 0.3.17 (the fleet saw the same shape as "a 12-second timeout does not stop the node"). Three of the four failed checks follow from that one death (counts, the restarted node's resync, the node it served frozen at 502). The fix on the line, one rule: the poll in 250 ms steps returning the moment shutdown is set, with a test that a shutdown returns within a second (the 10 s loop the known-failed shape); the exec suite on build-2, the fifth commit and its build about 12:45Z, its digest and ten-minute gates about 12:50 to 13:05Z, inside 14:30Z. b7cc37e7 is NOT the pin. The node-side re-pin for sub-version 2 (byte 7) once the hash lane's commit lands: the beside-the-fork igneum-pow copy archived from the commit, the two pinned ids moved in the kaspa-pow vector test (sub-version-2's epoch-0 id must-equal; sub-version-1's joins c120d7963abdcd96 as must-differ), CLASS_SIGNAL and tests for byte 7, the daemon's window line: about 20 minutes of edits plus one kaspa-pow suite run on build-2 (about 2 minutes). THE FIFTH COMMIT c4459193 on release-0.3.20-node (b7cc37e7's child, the watchdog poll returning on shutdown; the diff is the poll loop in rpc.rs alone), pairing igneum-pow 8c728ca3; its build on build-1 started 12:30:13Z, sha256 and string to follow. Line A, the shutdown test: rpc::watchdog_tests::a_shutdown_returns_within_a_second_whatever_the_poll green on build-2 at 12:29Z in the exec suite's 31 passed, beside the two other watchdog tests; its known-failed shape the old loop's 10 s stop. Line B, the kept-datadir start: b7cc37e7's fleet read carries to c4459193 since the store code is byte-identical between the two commits; the fleet re-reads on the c4459193 binary only if the shipper's rule wants the string on that line too. The digest gate and the ten-minute mixed-version gate on c4459193's own binary follow its build. THE SHIPPER'S CARRY RULING (14:1x UK): b7cc37e7's kept-datadir read stands as evidence that the store fix is right (the store code byte-identical) but is not the gate line for the pin, because the rule reads the binary, not the diff, and the binary changed (rpc.rs); the gate line is the kept read on c4459193's own binary with its string, which the fleet's canary already runs on c18-1 (wipe, then the kept read, then the restart) before the canary's restart step, at no extra cost; no re-read on p12-vast. THE PIN IS c4459193 pairing 8c728ca3 (object byte 5, sub-version 1); sub-version 2 (byte 7) is 0.3.21's, not 0.3.20's. The shipper's reading of main's F8 ruling: 0.3.20 ships object 5 as it stands because the live floor otherwise flips every node to the OLD stream on 13 October, and the 16:00 BST report tells the founder the floor move is now RECOMMENDED rather than optional, so the chain never flips to a stream that fails the 1.2x gate before sub-version 2 lands. THE FLEET'S CLOCK ON c4459193 (the fleet lane, 12:5x UTC): the kept read on pool-1's 0.3.17 datadir copy and the restart (the old process's stop time on the line) run on c18-1 before the wipe, a few minutes each, so both lines land before 14:30Z; the wipe canary (IBD from the pruning-point proof, 98 minutes on this pod class) starts when c18-1 is free of the 0.3.20 cases (about 13:00Z) and the binary is in hand, so its synced line lands about 14:40Z at the earliest, PAST the 14:30Z checkpoint; the 12 GB settled-claim line: c4459193 starts on p12-vast's kept copy of pool-1's datadir beside the 6a3432a3 IBD node on alternate ports the moment the binary lands, catches up from 129,398 blocks (15 to 20 minutes) and the 12 GB prover claims against it, the line on c4459193 itself. The binary not yet in the fleet's hand (build-1 building since 12:30:13Z); a wait armed on the sha and string, a report by 13:10Z if nothing. THE SHIPPER'S CALL ON THE CLOCK (14:2x UK): the wipe canary is the decisive read by the deploy rule; the pin never cuts without it and b7cc37e7's lineage does not stand in (the binary changed). The fleet rents a second one-shot pod of c18-1's class now and starts the wipe canary on c4459193's binary the moment the build lands, synced line about 14:15Z (15:15 BST), inside the checkpoint; c18-1 keeps the 0.3.20 cases and the pool window. If the wipe line slips past 15:30 BST the pin holds to it and main hears the clock (a slip is a report, not a cut). The set: the node lane's digest and mixed-version gates (12:50 to 13:05Z), the kept read and restart on the new pod, the wipe line on the new pod, the 12 GB settled-claim line on p12-vast. c4459193's BINARY IN THE FLEET'S HAND (12:34:54Z from build-1): igneumd sha256 45be9b02d1b002f5486d0f0108571c3b6042094113ad9da6f3d3d9ffc0072bba with the string c4459193 read back from the file, igneum-miner c7cfc40bc8b0e357. The wipe pod c19-1 (RunPod wpuke4tfu0vr49, RTX 3070 community, c18-1's class, USD 0.13/h, rented 12:37:03Z, one-shot; the day at USD 124 of work plus the 248 leak, 37 percent of the ceiling): the canary form (wipe, IBD from the pruning-point proof, synced, ten minutes mining with the exec poller, the hub read, the restart read) starts the moment the pod answers ssh; the kept read on pool-1's 0.3.17 copy armed behind its synced line on the same pod; the IBD start stamp its own line; synced about 14:20Z if the pod answers by 12:42Z (ten minutes inside the checkpoint), a slip reported the moment a poll shows it. CASES END on c18-1 at 12:37:18Z rc 0 (the relay and poison lines to the shipper); c18-1 and the two case pods destroyed by the run; the ten-member pool window rented its ten at 12:37:36Z. The 12 GB settled-claim line on p12-vast runs against a c4459193 node on the pod's kept copy, up since 12:36:35Z first-try, catching up. THE WIPE CANARY ON c19-1 STARTED: IBD at 12:38:55Z on c4459193 (sha256 45be9b02... asserted on the Mac before the put; the node's own line igneumd/2.1.0-c4459193 and digest eada4bda8aa8368c read back on the pod; a wiped datadir; IBD from the pruning-point proof with 4 peers at 12:39:26Z); synced about 14:17Z by the 98-minute class, thirteen minutes inside the checkpoint; the mining read, hub read, restart and kept read follow on the same pod, each its own line. c4459193's GATE LINES (the node lane): the binary built on build-1 at 12:33Z (1 m 07 s), sha256 45be9b02d1b002f5, the string read back from the binary (strings, two hits) and the worktree HEAD; igneum-miner beside it at /srv/builds/igneum-wt-ca3-v4-node/vendor/igneum-node-0318-release/target/release/. THE DIGEST GATE 12:33:27Z to 12:35:05Z SUMMARY PASS: the thirteen-field object a89be8a7 on both binaries, n0 peering n1 and n2 and the old node peering the new (the compat case); the sixteen-field object db9a85f9, n3 with no peer and the refusal line "consensus params digest mismatch, local db9a… remote a89b…" (the refusal case); the live file's digest on this binary eada4bda, as 5899f603 reads it. THE MIXED-VERSION GATE 12:35:26Z to 12:45:39Z SUMMARY PASS, beside the 5899f603 pair: one digest b0afb2ee on all five nodes; the 5899f603 hub accepted every block the c4459193 node mined, 215 new and 314 old, 0 rejected, no reject line in any log; header versions plain 2 on the thirteen-field file; counts equal on all five at 312 after mining, 441 after the clean join through the old hub and the clean join served by the new node, 529 at the end; the restart step passed: the new node restarted at 12:43:08Z on its own datadir and resynced to 529 with the others (where b7cc37e7 died on the database lock); no panic in any node log; every check green. The node side of the set is complete; the fleet's wipe, kept read, restart and settled-claim lines remain. A SLIP (the fleet lane, 12:5x UTC): the 0.3.20 cases rerun on c4459193 lands about 15:10Z, not 14:20Z: its target c20-1 catches up from pool-1's kept 1026 copy, 22,000 blocks behind a tip the line reaches headers-first (headers 137,405, blocks 129,398 at 12:50Z; the morning's poison pod on the same copy took 50 minutes before its blocks moved), synced about 13:50Z, the 79-minute form after; no faster path exists on a kept copy. The wipe canary on c19-1 holds its clock (29 percent of the headers at 12:47Z on dc141409's curve): synced about 14:17Z, the mining and hub reads to about 14:30Z, the restart and the kept read after; the 12 GB settled-claim line on p12-vast about 14:00 to 14:10Z. The kept read on the pinned binary is already in hand from c20-1's own start at 12:45:46Z (the rewrite line, no panic, sha 45be9b02 and the string read back), with the shipper. MAIN'S RULING WITH THE SHIPPER (14:5x UK): the cases rerun on the pin's own binary gates the cut; the cut word about 15:15Z (16:15 UK) on CASES END, the publish on green right after, the sweep from then with PC 1 first; 5899f603 the fallback until the word. The shipper's reason: the cases are a named gate and the morning's run was on dc141409 (the diff from dc141409 to c4459193 touches the class signal byte, in the cases' territory); the 16:00 BST report carries the clock and the full cut set; everything else staged so the publish is one step at that moment; nothing changes on the pods. AP-F8-1 RE-GATE VERDICT ON SUB-VERSION 1 (the attack-pass lane, census ended 12:55:55Z; igneum-pow 8c728ca3 paired with release-0.3.20-node 8097d600, pairing id 1a4230699a6b9c60 verified by the harness; 64 seeds p2 to p65 at 2^24 nonces each, chain path with era, window-model control, box 2; log /srv/builds/igneum-wt-attack-regate/attack-f8-regate/log/regate-census-64x2e24.log): FAIL the pass line, 53 of 64 PASS, 11 FAIL.
Seed Ratio to the window model Hottest item's predicted source
p31 29.27x 0x74e2b8, 5,365,527 reads, site 4 r4 all-ones, last writer rotl at 3
p11 5.45x 0x0eec66, site 1 r7 all-ones, last writer or at 63 of the previous iteration
p45 4.55x 0x400000, site 1 r4 zero, last writer mulhi at 59
p19 3.32x 0x400000, site 37 r5 zero, last writer load at 32
p6 3.11x 0x3bf40d, site 13 r0 all-ones, last writer load at 12
p23 2.04x site 16 r7 all-ones, last writer load at 14
p4 1.57x
p34 1.51x 0x400000, site 23 r6 zero, last writer rotr at 12
p10 1.50x
p26 1.30x 0x000000, site 10 r1 zero, last writer rotl at 2
p25 1.28x
the 53 passing 0.9915x to 1.16x no predicted source

Three residual classes, all a constant delivered through a writer the rule admits: (1) saturation or zero preserved through rotl, rotr, load or mad (p31, p6, p23, p26, p34); (2) zero from mulhi (p45) and zero preserved by rotates; (3) the iteration boundary, the rule's writer state starting fresh at instruction 0 so an or at 63 feeds a load at 1 (p11). Sub-version 2's dataflow-freshness rule closes all three IF the freshness is computed as a fixpoint over the loop (the state after instruction 63 feeds instruction 0 of the next iteration), with the dynamic (c') count on load sources as the backstop; sent to the hash lane. "No lossy-sourced load by construction" is not true of sub-version 1 and stays held. Chip consequence on sub-version 1 by the 1.4 arithmetic: the hot set is still one item at one site, under 1 percent of rate for a chip caching it, so the ship is safe on the rate side; the auditor's flag is what sub-version 2 removes. F9's hot-set harness cannot be the second re-gate (its metric counts the era's designed half and quarter windows as hot; its chain-path 8.3 percent on sub-version 1 is the window model, verified on its worst seed); F8's census is the single re-gate instrument, re-run on sub-version 2 within the hour of its commit. SUB-VERSION 2 COMMITTED: ca3-v4-amend 07a809a7, 13:01Z (origin and build), the string with the attack-pass lane. The loop fixpoint is in as rule (a') in accept.rs (the freshness run to its fixpoint over base then shadow block; every load's source fresh in the steady state, else the candidate rejected and the next attempt drawn; it closes the iteration boundary the draw's fallback cannot see); (c') counts zero and all-ones alike (v == 0 or v == MAX) per load site over the 16,384 evaluations, rejected at 164 or more; both and the draw rule keyed on the class v4 shape on every draw path, so v2 and v3 do not move; mulhi never fresh. Epoch-0 id a788661687db4bb3 (the devnet seed's attempt 0 rejected by the new rules, attempt 1 accepted); must-differ c120d7963abdcd96 and 1a4230699a6b9c60 pinned; object byte 7 in recheck.rs. The seven fingerprints (Metal = Apple OpenCL on the M5 Max, 13:01:17 to 13:01:49Z, the control 90f794dd556f7a3b unchanged):

Pack Fingerprint
v4-devnet-epoch0 e370fb2080b7dbb1
era-0 b7237555d31fc3cf
era-1 b6b167fa15dfe2c9
era-2 28bdf65eff33f2c4
era-3 e26d38c46f3f1b16
era-4 dd8fdf6ff4f59eed
era-5 8bf40f5cb858d835

Packs zip (eight packs, packs-ca3-v4-sub2) sha256 69c36772cd79e44e2ddd589466d9c64a94a13c9e970e9f27bd76feabb9b4581b. The suite re-runs through master's build-remote on box 2 (the worktree's own script predates --box; the first run died on the flag), line to follow; G1 on PC 2 under --cards-off after it. The sub-version-2 pairing waits on the node lane's re-pin to a788661687db4bb3 and byte 7. For the record, sub-version 1's pairing: igneum-pow 8c728ca3 against b7cc37e7 (8097d600's assert_ne in) 17 passed, 0 failed, rc 0, 12:21Z. 0.3.20's CUT SET AS IT STANDS (the shipper, 14:1x UK): pin c4459193, igneum-pow 8c728ca3 at object byte 5 (sub-version 1), the floor-moved file publishing with it (the founder's word; the floor from the live DAA at the publish plus 604,800, the digest read on c4459193), publish about 15:15Z (16:15 BST) on CASES END, the sweep from then with PC 1 first. 0.3.21's clock tonight: the node lane stages release-0.3.21-node at the shipper's sweep-end word (about 15:45Z, 16:45 BST) with the sub-version-2 re-pin (07a809a7, byte 7, id a788661687db4bb3) as its own commit, held pending the F8 census on 07a809a7; the census's clock about 14:00Z (15:00 BST) by the attack-pass lane's within-the-hour line from 13:01Z; the pass line every one of the 64 seeds under 1.2x of the window model on the chain path. If the census fails or slips past 19:00Z (20:00 BST), main's standing ruling applies (nothing on sub-version 2 is proposed until the census is green): 0.3.21's node ships byte 5 again with the re-pin dropped and the rest of its line kept. CI NOTE (13:1x UTC): master's ci runs since 12dc5c97 (nineteen of mine) sit queued behind one self-hosted runner (igneum-build-1, busy; 31 queued across branches, one in progress); the last completed master runs (439a233f to 5f990a09) are success; no red exists, the conclusions are unread until the queue drains. MAIN'S WORD (14:2x UK): the floor move is the founder's word already and ships with 0.3.20 at the cut; the CI lever is a second self-hosted runner on build-2 plus ubuntu-latest for docs-only pushes, ordered to the CI lane; the rule reads "own a red when the conclusion lands", never holding pushes; the census verdict about 14:00Z (15:00 UK) decides 0.3.21's byte. SUB-VERSION 2's STATIC CENSUS (the hash lane, tools/ca3-v4-uniform on box 2, 13:12Z, 1,024 chain-shaped seeds plus F8's p1 to p3): 0 lossy-sourced load sites of 16,432 (14,329 injecting, 2,103 bijective); 0 programs with an or-, mul- or mulhi-sourced load; the no-era draw path gives the devnet epoch-0 seed the pack's own id a788661687db4bb3, so every draw path reads one stream. Cost of (a') and (c'): 1.99 attempts per seed on average against 0.05 before (p2's seed five), about 2 ms of generation per rejected attempt on one core; nothing a miner or node notices. Ledger entry 715f14be. Master 36e08c80 merged into ca3-v4-amend as f5244ad7 (igneum-pow untouched, re-export 0 differing files), pushed with the gate GREEN, its CI runs queued; the box-2 suite runs through the merged tools (the first attempt died on test initialisers missing the (c') field, fixed in the same push; library and packs unaffected). G1 BLOCKED: PC 2 has not picked up fetch-ca3-v4-sub2-20261007 and run-ca3-v4-sub2-g1-pc2-20261007 (published 13:04:02Z, signature OK); the intake shows nothing from 1ccfe586 since job-update-now-0319 at 10:34:21Z; the PC 2 lock releases when the job closes or in 30 minutes; the run is republished when the app reports. PC 2 READS SILENT on the console (the shipper, 14:4x UK): last seen 2 h ago, app 0.3.19 on node 5899f603, its last line the 0.3.19 update-now at 10:34:21Z; the app went down or stopped polling on that update (the UI lane's update-now; PC 1 took the same update and reports). The build-server lane's PC 2 kept-datadir job (run-20261007-125433, published 12:54Z) is unpicked for the same reason, and it is the Windows kept-datadir gate for 0.3.20's PC 1 step. The sweep cannot bring PC 2 back (the app's poller applies updates; a silent app does not poll); a Windows restart of the app is a hand action, the founder's or by main's word; the shipper has asked main. The hash lane's G1 and the Windows kept-datadir line wait on that answer; the PC 2 lock stays. SUB-VERSION 2's SUITE LINE (the hash lane): ca3-v4-amend 526fa757 (the code; the ledger tip f0fbd9da), box 2 through the merged tools, route line "13:15:07 build-remote: box 2 (build@142.132.249.238) for class suite, priority normal", rc 0, 66 s: 61 lib + 7 derive + 4 mixer + 19 packs + 2 recheck + 7 scratch = 100 passed, 0 failed; the pinned v2 and v3 packs byte-identical; the three v4 ids as pinned (a788661687db4bb3 equal; c120d7963abdcd96 and 1a4230699a6b9c60 differ). The two commits between 07a809a7 and 526fa757 touch tests only (the (c') field in the accept.rs initialisers; the two generator unit tests follow the amended facts); the library, the packs, the id and the seven fingerprints are unchanged from 07a809a7, so the attack-pass re-gate on 07a809a7 stands for 526fa757. CI: the merge commit's run cancelled by the next push (superseded, not red); 526fa757's run queued (37626985216), its conclusion owned by the hash lane. The 0.3.21 re-pin commit is therefore 526fa757 (or the branch tip at the node lane's archive, code-identical). MAIN'S WORD ON PC 2 (15:0x UK): the hand restart of PC 2's app is asked of the founder. If PC 2 has not polled by 15:00Z (16:00 UK), "go PC 1": the sub-version 2 G1 on PC 1 under the runner's --cards-off after the 0.3.20 sweep step lands there, one job, read back, nothing else on PC 1. The PC 1 job publishes only after the shipper's line "PC 1 on 0.3.20" (app 0.3.20, node 2.1.0-c4459193, the published file's digest, synced, the sweep step closed with its lock line), about 15:30 to 15:40Z by the clock, and only if PC 2 is still silent; The PC 1 variant is on ca3-v4-amend at a2714d43 (tools/ca3-v4-amend/pc1-v4-sub2-g1.ps1; CI checks pass; no api/quit, pause, resume or cards call in the script): the RTX 5090 on PC 1 (ae432dc7) by its index-free key nvidia:NVIDIA GeForce RTX 5090 on the runner's --cards-off, restored by the runner after; the AMD card and the Intel Arc not named and mining on; the card confirmed quiet by the process list (90 s wait) and nvidia-smi's compute-apps; the installed worker's --bench on the eight packs (the v3 control and the seven sub-version 2 packs) for the 2^24 fingerprint and self-test, rates a reference only; the kit the same zip (69c36772...), as fetch-ca3-v4-sub2-pc1-20261007 immediately before run-ca3-v4-sub2-g1-pc1-20261007 (--timeout-minutes 20, --expires-hours 12); published only on the go-PC-1 line. AP-F8-2 ON SUB-VERSION 2 (the attack-pass lane, 15:1x UK, before anything is proposed): a chain-shaped epoch seed can exhaust all 32 draw attempts under rule (a'), and the generator treats exhaustion as a consensus fault (panic): seed igneum-f9/331672, "32 consecutive candidates rejected, last: (a') load at 16 reads r6, not fresh by dataflow in the loop's steady state". One such seed in the first 331,672 chain-shaped seeds (300,000 drew clean), a rate of order 10^-6 to 10^-5 per epoch seed; the 10^6-seed measurement with the attempts distribution runs on box 2. Meaning: an exhausted epoch seed is an epoch no node can draw a program for, a liveness halt, the era and epoch seeds being VDF outputs nobody can steer; at one epoch an hour, one halt per 11 to 40 years at the bracketed rate, which the firms would compute from the rule as written and file. Sub-version 1 had 0 exhausted in 10^6 chain-shaped seeds. The fix (to the hash lane): the draw enforces the freshness fixpoint itself so (a') never fires (no exhaustion by construction), or MAX_ATTEMPTS sized to the measured rate with the exhaustion probability stated in the spec. The 64-seed hot-set gate on sub-version 2 is separate: 13 of 64 seeds read, none over 1.2x so far. Sub-version 2 is NOT GREEN until both are settled. MAIN'S RULING ON AP-F8-2 (15:2x UK): the draw must be total and no consensus path may panic; preferred fix a deterministic repair instead of rejection (the draw rewrites the offending load's source to the nearest fresh register, or inserts a fresh mix, so every seed yields a program on the first attempt and (a') becomes a check that can never fire); if the repair changes the stream's statistics, the fallback is a stated attempt bound with a deterministic last-resort draw after it, never a panic, the probability in the spec and the ledger; either way a test walking seed igneum-f9/331672 and the exhausting class, the 10^6-seed exhaustion count at zero, and the 64-seed hot-set gate re-run on the fixed commit; the hash lane builds it now on the coordinator's direction; 0.3.21 ships byte 5 if not green by 19:00Z (20:00 UK). The 07a809a7 kit is not published to any PC.

AP-F8-2 FIXED (the hash lane, ca3-v4-amend 8bdcbdd8, 13:31:10Z, origin and build, gate GREEN): sub-version number unchanged at 2 because the stream is unchanged for every non-exhausting seed (re-export diff 0 on v4-devnet-epoch0, v4-era-0 and v4-era-5; the id a788661687db4bb3 and the seven fingerprints stand; the packs zip sha256 69c36772... holds), so the attack-pass census at 13 of 64 continues on it. The route: the deterministic repair would have rewritten every seed whose attempt 0 fails (a'), about two thirds of seeds, a new stream and a restarted census against the 19:00Z line, so the second route main allowed was taken. The bound: MAX_ATTEMPTS_V4 = 256 for the class v4 shape (v2 and v3 keep 32, keyed on the shape); at the measured rejection rate of about two thirds per attempt, 32 attempts exhaust at about 2e-6 per epoch seed (one undrawable epoch every few decades at one an hour), 256 at under 1e-45, the worst-case draw about half a second on one core. After the cap the draw is total: the seed takes the last-resort program, deterministic and accepted as drawn, the candidate at attempt 256 with every or, mul and mulhi of the base program and the shadow block rewritten to xor, so every register stays fresh from the init words on and (a') holds by construction; no consensus path panics for the v4 shape. The test class_v4_draw_is_total_with_the_last_resort (the last resort on real (a')-rejected candidates, every load fresh after it, no lossy op left, the chain path over 64 seeds without a panic, the cap per class asserted) green on the Mac, the box-2 suite running; the hash lane's 4,096-seed census with the attempt histogram on box 2; the attack-pass lane's 10^6 count is the control; the string with the attack-pass lane with seed igneum-f9/331672 named. CI: 526fa757 success; 8bdcbdd8 queued. The spec and ledger text for the bound and the probability in the ledger entry. The PC 1 variant and fetch job carry 8bdcbdd8's packs (byte-identical to 07a809a7's); the PC 2 kit published at 13:04Z is the same packs. Per tier: a miner never sees the draw (the node draws once an hour, half a second at worst); a chip maker gains nothing from the last resort (a 1e-45 event); the auditor reads the bound and its probability in the spec. SUITE LINE AT 8bdcbdd8: box 2, route line "13:31:21 build-remote: box 2 (build@142.132.249.238) for class suite, priority normal", rc 0, 80 s, 62 lib + 7 derive + 4 mixer + 19 packs + 2 recheck + 7 scratch = 101 passed, 0 failed, the total-draw test included; ledger entry 32e96c9a; CI on 526fa757 success, the newest push's run queued and owned by the hash lane.

THE 12 GB SETTLED-CLAIM LINE ON c4459193 (the fleet lane, 13:27Z): the floor reads right and the card proves, THE NODE REFUSES. p12-vast on c4459193 (sha 45be9b02, string read back) synced 13:22:47Z on the kept copy; first claim 13:23:01Z "segment 164198..164205 (8 shards, fresh) margin=414 tip=287564 settledNumber=0x28185 settledDaa=0x46317 settledBy=finality candidates=5"; proof complete 13:25:19Z on the 3060 (8 of 8 shards, 135.9 s, peak 8,487 MiB); submission refused "statement differs from the node's at hex offset 472 (lengths 616 vs 616); ours ...2b1a81cb413236cf... node ...0000". The node's start line on this binary reads "proving v1: ... shard program id unknown, aggregator id unknown" where 5899f603 on the same override file reads the ids; the statement is built with zeros and every proof fails its check. This blocks the paid line on any card and, after the sweep, every standing prover; with the node lane (the fix) and the shipper (the cut) since 13:27Z; the pod and proof files held for the node lane's read. The cut set is therefore NOT complete on c4459193. THE CAUSE (the node lane, 13:4xZ): no commit on the line lost the ids and the binary is not the difference; on every build including 5899f603 the statement's ids come from the override object's two fields (absent on the live sixteen-field file), else IGNEUM_PROOF_PROGRAM_IDS, else the verifier host's --mode id when IGNEUM_PROOF_VERIFIER is set. hub-1 runs with IGNEUM_PROOF_VERIFIER=/opt/igneum-floor/bin/igneum-prove-host in its process environment, so the host hands it the ids; the pod's c4459193 node was started bare for the kept-datadir read, so program_ids answered None and the statement carried zeros; a bare 5899f603 reads "unknown" too. The start environment, not the binary. What the child commit fixes anyway: the binary embeds the verifying keys it verifies carried proofs with, so it knows the ids it expects; the child resolves them in that order and last from the embedded keys, with a test whose known-failed shape is the bare node's None and the zero-id statement; the diff two files (resolve_program_ids in igneum/exec/src/proving.rs and its call in kaspad/src/daemon.rs; nothing in acceptance, the version check, relay or peer handling); its exec suite running, the string and sha256 about 13:52Z. Gate carry: the digest and mixed-version gates are outside the diff's territory and carry from c4459193, but rule 4a runs every gate on every candidate from its build, so both run again on the child's binary and the fleet's set with them; the re-run that bears on the diff is the 12 GB line itself, the pod's already-proved claim submitted against a node that names the ids. Per tier: a solo miner on a bare node never proves, so feels nothing; a standing prover beside hub-1's environment was never affected; a prover on a bare node could not be paid on any build until the child. THE CONTROL (the fleet lane, p12-vast): the same c4459193 (sha256 45be9b02d1b002f5, string read back) on the same kept copy, killed and restarted 13:30:28Z with IGNEUM_PROOF_VERIFIER=/opt/igneum-floor/bin-0317/igneum-prove-host (sha 71bc2438) and HOME on the floor: the start line reads "proving v1: ... shard program id 0x2b1a81cb413236cf..., aggregator id 0x474678f3...", no panic, synced 13:31:49Z (155,725 blocks, 4 peers); the bare start of the same binary on the same copy at 12:36:11Z read "unknown". The ids are the start environment on the pinned build, not the binary. The submission verdict against the ids-naming node: the prover restarted 13:31:56Z and claims fresh (the 13:23Z proof held as evidence, past its margin), the first chain proof about 2.5 minutes on the 3060, the verdict line about 13:36Z; the bare-child line runs the minute the child's string and sha land (about 13:52Z). THE CONTROL'S VERDICT (13:33:56Z): against c4459193 restarted with the verifier set, the 3060's first proof "RESULT seg 164286 chain ... 8 shard records, chain_len 8, proof 1272909 bytes, shards 44.9 s, aggregation 39.7 s, wall 110.6 s, peak 8423 MiB", "shards accepted 8 of 8", no "FAILED: statement": the statement check passes, so the zero-id refusal at 13:25Z was the bare start's environment and nothing in the binary, the pin included. The submission then read "segment_refused ... segment already paid; end to end 113.1 s": the claim race (a 24 GB box proved the same fresh segment inside the 3060's 113 s, the shape of p2-4070-1 this morning); the settled floor does not reserve a claim per key, so a 12 GB prover on the open devnet wins only when no faster box picks its segment; the prover runs on (claim 164342..164349, settledNumber 0x28208 by finality, margin 470) and the paid line goes out the minute a race is won, minutes to tens of minutes of races, not the floor. Per tier: a 12 GB card proves and verifies on the pin; whether it is paid on the open devnet is the race against bigger cards, which is the settled floor's design today and a question for the claim rule, not this cut. THE PROVING-IDS CHILD: 55768f88 on release-0.3.20-node (c4459193's child; resolve_program_ids reads the override's fields, then the env or the host, then the embedded verifying keys; one call in the daemon), pairing igneum-pow 8c728ca3 at byte 5; the exec suite 32 passed at 13:29Z with a_bare_node_resolves_its_program_ids_from_the_embedded_keys (known failed first: the bare node's None and the zero-id statement), kaspad check green 13:33Z; igneumd and igneum-miner built on build-1 at 13:35Z, sha256 279b1b690e854fc9, the string read back; the node lane's digest and mixed-version gates on it from 13:37Z (lines about 13:52Z); the fleet has the path, sha and string for its full set from the same minute; ledger N14 on ca3-v4-node. MAIN'S WORD THROUGH THE SHIPPER (15:5x UK): THE PIN IS c4459193 (the control showed the environment names the ids on it; the ids commit 55768f88 is 0.3.21's first node commit, with the ids gate on every candidate from then); the publish about 14:55Z (15:55 BST) on CASES END. PC 1 is offline for the founder's cable work, out of the sweep's waves; its app updates on its poller when it returns; the "PC 1 on 0.3.20" line comes after the cable work, not at the publish. PC 2 still silent. The sub-version 2 G1 waits for whichever PC returns first; nothing on either before the shipper's line. 0.3.21's node line stages tonight on 55768f88 with the re-pin held for the census. MAIN'S RULING ON 0.3.21's BYTE (16:0x UK): neither PC is needed for the CUDA half; G1 for 8bdcbdd8 runs on a fleet 5090 now (p1-5090 or a one-shot 5090 pod through the fleet lane; the Linux CUDA worker's 2^24 fingerprints and self-test against the Mac's seven; no --cards-off on a pod; ordered to the fleet lane with the kit's sha256 and the pass line). If that G1, the attack-pass lane's two gates on 8bdcbdd8 and the node lane's re-pin and pairing are all green by 19:00Z (20:00 UK), byte 7 ships in 0.3.21 with the Windows G1 owed and run on the first PC that returns (a Windows-only CUDA mismatch would be a 0.3.22 re-pin; nothing flips before the moved floor); if any is not green by then, byte 5 ships and the re-pin stages for 0.3.22. THE FLEET G1 PACKAGE (the hash lane to the fleet lane, 13:4xZ): the kit packs-ca3-v4-sub2-20261007.zip on the dl host (sha256 69c36772...), the eight packs; the worker proto-cuda/nvrtc/worker.cpp built for Linux by infra/cross/build-workers-linux.sh (dlopens libcuda and libnvrtc, compiles each pack's own text; any 0.3.20-tree build is the right binary, its string from --help); the bench igneum-worker-cuda --bench --pack <dir> --batches 5 --batch-log2 24 --block-warps 1, the pass per pack self-test PASS plus the fingerprint equal; the eight expected fingerprints. THE PC 2 RUN JOB WITHDRAWN: run-ca3-v4-sub2-g1-pc2-20261007 had been live in the signed file since 13:04Z and would have fired the moment PC 2's app polled, before any sweep step; removed and deployed 13:39:54Z, the file verified; the fetch kit stays; the PC 1 variant never published; the PC 2 lock released 13:39:22Z. PC 2 BACK (the shipper, 13:4xZ): polling since 13:38:32Z, app 0.3.19, non-elevated, node synced; the silence from 10:46Z was the whole PC losing power (Kernel-Power 41, no bugcheck), not the update; the build-server lane's kept-datadir job ran on it at 13:38:32Z and passed; PC 2 takes 0.3.20 on its poller in wave 1 at the publish. The Windows G1 on PC 2 ordered now under the PC 2 lock with --cards-off on the 5090, the 0.3.19 worker (nvrtc compiles each pack's text), to close well before the 14:55Z publish (a job under an app relaunch is the shape that killed the 9070 XT on 6 October); if it cannot start by 14:20Z it waits for the shipper's line that PC 2 reads 0.3.20. The fleet 5090 G1 runs regardless. THE LINUX CUDA G1 FOR SUB-VERSION 2: PASS (the fleet lane, p1-5090, the fleet's standing RTX 5090, no rent, 13:43:22Z to 13:44:07Z; kit sha256 69c36772... asserted; the box's igneum-worker-cuda 1.0 of 4 October 2026, sha256 97e036e23f4ace66; --batches 5 --batch-log2 24 --block-warps 1).

Pack Fingerprint on the 5090 Equal to the Mac
mx8-devnet-epoch0 (the v3 control) 90f794dd556f7a3b yes
v4-devnet-epoch0 e370fb2080b7dbb1 yes
v4-era-0 b7237555d31fc3cf yes
v4-era-1 b6b167fa15dfe2c9 yes
v4-era-2 28bdf65eff33f2c4 yes
v4-era-3 e26d38c46f3f1b16 yes
v4-era-4 dd8fdf6ff4f59eed yes
v4-era-5 8bf40f5cb858d835 yes

Self-test PASS on each (FNV-1a 448274a57f508cbc); rates 120 to 142 MH/s with the box's miner loop sharing the card, a reference only; p1-5090's node untouched, its supervisor restarted after. The CUDA half of G1 is green. THE WINDOWS G1 ON PC 2: GREEN (job run-ca3-v4-sub2-g1-pc2-20261007b, published 13:46:33Z under the PC 2 lock taken 13:45:03Z, the runner's --cards-off on the 5090, 15-minute timeout, nothing of the proving lane's running; start 13:46:36Z, end 13:46:50Z, exit 0; lock released 13:47:18Z; app 0.3.19, the installed worker sha256 14b6637e..., the card off before the script and restored on exit, igneum-worker-cuda 0 before and after, the prover untouched).

Pack Fingerprint on PC 2's 5090 MH/s (card alone, 5 batches) Equal to the Mac and the fleet 5090
mx8-devnet-epoch0 (the v3 control) 90f794dd556f7a3b 118.1 yes
v4-devnet-epoch0 e370fb2080b7dbb1 119.3 yes
v4-era-0 b7237555d31fc3cf 115.8 yes
v4-era-1 b6b167fa15dfe2c9 116.7 yes
v4-era-2 28bdf65eff33f2c4 119.3 yes
v4-era-3 e26d38c46f3f1b16 129.5 yes
v4-era-4 dd8fdf6ff4f59eed 115.2 yes
v4-era-5 8bf40f5cb858d835 117.1 yes

Self-test PASS on every pack (cache FNV 448274a57f508cbc); both rows in the ledger entry 43c5bf5b. G1 FOR SUB-VERSION 2 IS COMPLETE on three platforms (Metal, Linux CUDA, Windows CUDA), nothing owed. Per tier: the 5090 rate on sub-version 2 is the same band as sub-version 1 (115 to 130 MH/s), so a miner's rate does not move with the class amendment. The lines left for byte 7 by 19:00Z: the attack-pass lane's two gates and 10^6 count on 8bdcbdd8, the node lane's re-pin and the pairing. THE 64-SEED GATE ON SUB-VERSION 2 IS HEADING TO FAIL (the attack-pass lane, 13:55Z; its earlier "none over 1.2x at 13 of 64" was not read from the log and is withdrawn): 39 of 64 seeds read, 8 over 1.2x of the window model, worst p23 at 4.82x; 44 minutes for 39 seeds, the finish about 14:25Z; the eight seeds' hottest items and predicted sources being read (a residual constant through a writer the freshness rule still admits, or the window model's tail). The 10^6 exhaustion count at 8bdcbdd8: 630,000 drawn, finish about 14:05Z; the 07a809a7 control 880,000 drawn, finish about 13:59Z; the exhaustion and past-31 counts with the ends. The hot-set gate is F8's 64-seed census alone (F9's table serves the attempt histogram and the exhaustion count only). Sub-version 2 is NOT GREEN. THE EIGHT SEEDS (the attack-pass lane, 14:0xZ): three are the window model's own tail at 2^24 nonces with no predicted source (p4 1.22x, p8 1.38x, p10 1.50x); five are constants the freshness rule cannot see because it tracks lineage, not value: p23 4.82x (zero from xor of a register with itself at instruction 0, item 0x000000 at 41,727 reads), p34 1.25x (sub of a register with itself), p15 2.57x (zero through rotl at 0), p18 2.50x and p19 3.32x (a load whose address is constant delivers one word to the next load; p19 byte for byte the sub-version 1 program, untouched by the rule). (c') cannot catch them: its 164-of-16,384 per-site bound (1 percent) is about fifty times coarser than the gate (p23's item is 0.002 percent of all reads and still 4.8x at the top 0.1 percent). Chip side unchanged: one item at one site, nothing to a chip; it is the auditor's uniformity test that fails. THE EXHAUSTION HALF (AP-F8-2) at 8bdcbdd8: 0 exhausted and 0 panics in 650,000 chain-shaped seeds (the 10^6 finishes about 14:05Z), max attempt 35, nobody at the last resort, past attempt 31 about 3.2e-6 (5 in 1.55 million draws, inside the (2/3)^32 estimate), per-attempt rejection 0.67, mean 2 attempts; seed 331672 accepts at attempt 32; the 07a809a7 control's clean evidence one exhaustion in 331,672 (its later chunks contaminated by a rebuild on the same path, not used); FIXED-AND-PASSED at the 10^6 end if the count stays 0. THE GATE QUESTION (the hash lane to the attack-pass lane): three of the eight are the null's own tail at 2^24 nonces, so a 1.2x-on-every-seed threshold sits below the null's spread and no rule can pass it on 64 seeds; the threshold must be set from the null's measured 64-seed quantile or the nonce count raised; the attack-pass lane asked to state that quantile. SUB-VERSION 3 (the fix shape, the hash lane; new ids, packs, fingerprints, the G1s and the census again): (1) the draw forbids a self-operand on xor, sub and mad (dst == src) in the base program and the shadow block; (2) (c') becomes a per-site bound on the MOST REPEATED source value, any value, over the 16,384 evaluations, set from the gate's sensitivity (a uniform source repeats a value two or three times by chance; a bound of 8 is 0.05 percent of a site's reads, 0.003 percent of all reads, 1.02x at the top 0.1 percent), catching the load-after-load constant, the rotated zero and anything a static rule misses; (a') stays for the or, mul and mulhi classes; (3) the attempt cap and the last resort stay, the last resort's rewrite gaining the self-operand guard (a lossy op with src equal to dst becomes add with the immediate). Clock (UTC): build, re-export, Mac fingerprints and the census by about 14:50; the fleet and PC G1s by about 15:20; the attack-pass 64-seed re-gate about 1.5 hours after the string, green by about 16:45 if the threshold question is settled; inside 19:00Z with no slack for a second miss. CORRECTION (the hash lane, from igneum-pow show on p23, p15 and p18 at 8bdcbdd8): the draw already forbids src == dst on every ALU op, so the self-operand ban (1) is void; p23's instruction 0 is xor r2 ^= r1 and site 1 reads r2, so the zero means r2 equals r1 at the start of most iterations, which only the shadow block arranges (a pair of ORs between two registers makes them equal; lossy ops are free in the shadow because only load sources are ruled); p15's rotated zero and p18's load-to-load constant are the same class, a value equality or a constant made upstream that lineage cannot see. The only fix that closes the class is the dynamic bound (2), whose reach the acceptance sample sets: a uniform source repeats a value three times with probability about 4e-8; p23's zero at 3e-4 of its site's reads shows up about five times in 16,384, so "no value three times at a site" catches p23 with about 88 percent probability and misses rarer constants; catching a constant at 1e-4 of a site's reads reliably needs 256 units instead of 64 (four times the draw cost per attempt, about 8 ms), a bigger consensus change. THE COORDINATOR'S PLAN (15:1x UK, to main): 0.3.21 stages on byte 5 (sub-version 1, what 0.3.20 carries); byte 7 goes in only if a sub-version 3 reads green on both gates by 19:00Z; otherwise sub-version 3 is 0.3.22's, built against a gate defined in numbers. The attack-pass lane asked for the gate's three numbers by 14:30Z (the ratio's formula; the single-item read count at 2^24 that still passes 1.2x; the null's 64-seed tail and a threshold defendable to an auditor, or a higher nonce count); the hash lane prepares sub-version 3 uncommitted (the bound and the sample size as parameters, the test with p23, p15 and p18 as the known-failed shapes, the draw-cost line per sample size) and commits on the coordinator's one line once the numbers land; if they do not land by 14:30Z or the census would pass 18:00Z, sub-version 3 is 0.3.22's. THE GATE IN NUMBERS (the attack-pass lane, 14:2xZ, from tools/attack/f8-uniform/src/main.rs lines 289 to 290 and 1240 to 1252). (1) The ratio: the items are the 2^22 dataset items; a census counts reads per item over 2^24 nonces x 128 loads = 2^31 reads; S_f is the share of all reads on the top f of items by measured count (f = 0.1 percent = 4,194 items); W_f the same statistic on a windowed control (a simulated read map from the program's own 16 window draws under the era map, Poisson, no program structure); ratio_w = S_f / W_f, the gate ratio_w at f = 0.1 percent under 1.2; the flat ratio against a uniform map reported beside it; X_f = S_f minus W_f the excess share. (2) The reach: on a typical seed W_0.1 is 0.14 to 0.16 percent of all reads, so 1.2x is an excess of about 0.03 percent, 640,000 reads of 2^31; a single item trips the gate alone only at about 640,000 reads (0.48 percent of its site's 2^27, 78 repeats per 16,384 evaluations), which a per-site most-repeated-value bound sees; the five constants are the tops of low-entropy BANDS: a site whose index has k bits of entropy over its window spreads 2^27 reads over 2^k items, ratio about 45x at k = 12, 6.7x at 15, 2.4x at 17, about 1.2x at 18 (512 reads per item, the uniform level); so the reach is a per-site index entropy of about 18.5 bits of the window's 20 to 22, and the matching dynamic statistic is the count of DISTINCT source values per site, not the most repeated (at 16,384 evaluations every k above 14 reads about 16,380 distinct and is invisible; at 2^20 evaluations a k = 18 site reads about 2^18 distinct against 2^20 uniform). The bound: distinct index values per site over 2^20 evaluations at least 2^19.5 (about 740,000), run once on the chosen candidate (about 10 s per candidate), with the most-repeated-value bound at 16,384 beside it. (3) The null's tail: the Poisson spread of ratio_w at 2^24 nonces is about 0.2 percent, so a seed at 1.22x is hundreds of sigma from the sampling null and a higher nonce count tightens nothing; sub-version 1's 53 clean seeds median 1.004x, p75 1.051x, max 1.156x (p17), then 1.103 and 1.080, the window model's own error, not noise; sub-version 2's three no-source seeds are reproducible under a re-draw (p10 1.5048x on sub-version 1 and 1.5036x on sub-version 2 with the identical program; p4 1.57x to 1.22x with the rule; p8 1.38x): structure the predictor does not name (near-zero or low-entropy sources whose images sit in the 0x40xxxx band), not tail. Defendable to an auditor: 1.2x sits just above the window model's measured error (1.04x over the clean maximum, 1.15x over the clean p75) and far above the sampling null; a seed over it with no named source is reported as unattributed and chased, never absorbed; neither the threshold nor the nonce count moves. Also: F6 closed PASS at 13:57Z (the worst of 10^5 programs 8.708 ms on the half-core proxy); the 64-seed census on sub-version 2 at 46 of 64, 8 over, finish about 14:40Z. THE LINE FOR SUB-VERSION 3 (the coordinator to the hash lane, 15:3x UK): commit now with the dynamic rule in two parts keyed on the class v4 shape: (A) per load site the count of distinct index values over 2^20 evaluations of the chosen candidate at least 2^19.5, run once on the candidate that passed (a') and the repeat bound, a failing candidate rejected and the next attempt drawn under the same 256 cap and last resort; (B) the most-repeated-value bound at 16,384 evaluations at 8 beside it; the threshold stays 1.2x; new ids, packs and fingerprints; the string to the attack-pass and fleet lanes; nothing to any PC. The 0.3.21 re-pin target moves from 8bdcbdd8 to sub-version 3's commit, on the coordinator's word after both gates, before 19:00Z or not at all for 0.3.21. MAIN'S WORD (15:4x UK): the plan accepted as written: 0.3.21 stages on byte 5; byte 7 only if sub-version 3 reads green on both gates by 19:00Z with the gate defined in numbers; otherwise sub-version 3 is 0.3.22's, read green before it is proposed; do not force the clock. AP-F8-2's EXHAUSTION HALF CLOSED: 10^6 chain-shaped seeds at 8bdcbdd8 through the chain path, 0 exhausted, 0 panics, max attempt 35, 4 seeds past attempt 31 (4e-6, inside the (2/3)^32 estimate), none at the last resort, r = 0.67, mean 2.0 attempts; final 14:03:53Z; FIXED-AND-PASSED in the pass record. The hash lane's sub-version 3 commit waits on its known-failed test's result on box 2, then the re-export, fingerprints, suite, census and the three strings. A SEPARATE FINDING ON THE 0.3.20 LINE (the node lane from the fleet's per-node read at 14:05Z, ledger N15 on ca3-v4-node): the exec layer's chain block number is the node's own record index (seeded from genesis, the restart pin or a snapshot, extended one per chain block the follower appends), not a canonical index of the DAG; seven standing provers number the same DAG block 2 to 46 higher than the hub and the five paid boxes, constant since some past follower event, so their segment records name block ranges the carriers refuse ("is not chain block N on this chain"; p1-5090's record for the worked example carried seven times and refused seven times while p1-4090's for the same DAG blocks was paid); a prover on a drifted node is never paid whatever the card or the claim rule. Nothing on chain is wrong and the pin's gates stand; the fleet scans the two worst nodes for the drift point; the fix direction (the number canonical by construction from the pin plus the selected-parent distance, a continuity check at every append, a drift self-check at start, the carrier resolving a record's segment by the block hash it names) in 0.3.21 if the scan names the event in time, else 0.3.22. Per tier: the hub and the five paid boxes are right; seven standing provers earn nothing until their node is restarted on a clean number or the fix lands; a solo miner is untouched. AP-F8-3, THE ROOT OF THE RESIDUAL CLASSES (the hash lane, 15:5x UK; in the attack-pass record c2203b55): accept.rs never runs the latency-shadow block. Its interpreter run_unit was written for class v2 and v3 and executes the 64 base instructions per iteration and nothing after instruction 63, while the hash (verify.rs, the GPU kernels) runs the shadow block 27 times at the end of every iteration. So every dynamic acceptance test on a class v4 program, (c), (c') and the (A) and (B) bounds, judged a program the chain never hashes: the forced equalities and constants that make F8's bands are produced by the shadow's lossy pairs (or r2 |= r1 then or r1 |= r2, the xor swap), which the acceptance never executed. Confirmed on the prepared bounds: p23 at attempt 4 passes (B) at 16,384 and (A) at 2^20 evaluations (492 ms on one box-2 core) because in the shadow-less run its registers are uniform. (c)'s own v4 figures (saturation, bias, distinct addresses) were measured on the wrong program, harmless only because the base program alone is a well-formed v3 program. THE FIX (sub-version 3): run_unit executes the shadow block after instruction 63 of every iteration, reps times with the iteration's sel, exactly as verify.rs does (the shadow holds no load, so its instructions take the same arms); then (B) at 8 repeats over the 16,384 (c) evaluations and (A) the distinct-index floor of 2^19.5 over 2^20 evaluations, both keyed on the v4 shape; (a'), the 256 cap and the last resort unchanged; a new stream and a new acceptance verdict for v4 (new ids and packs), v2 and v3 untouched (their shadow is empty). The known-failed test on p23, p15 and p18 re-runs on box 2 with the shadow executed; its result and the draw-cost line at 2^20 (492 ms per chosen candidate before the shadow, more with it) decide the commit. The attack-pass lane ships a class check beside the fix (the acceptance's program equal to the hash's). Per tier: nothing on the live chain changes (sub-version 1's acceptance is the same shadow-less check and its programs hash exactly as published); the auditor's finding is that class v4's acceptance was checking the wrong program since 6 October, closed in sub-version 3. THE SUB-VERSION 3 BUILD RESULT (the hash lane, box 2, 14:09Z): run_unit now executes the shadow block as the hash does and the test acceptance_executes_the_shadow_block_as_the_verifier_does is green (the acceptance's execution and verify.rs agree on the output bit counts over the 64 units for the devnet epoch-0 program and the six test eras, 8 x 256 x 27 shadow instructions per hash; the same program with its shadow stripped gives different counts, so the two paths cannot diverge silently again). But (A) and (B) do not reach the class even with the shadow executed: F8's exact p23 candidate (attempt 4, id 06263572197875d2, measured at 4.82x) passes (B) at 8 repeats over 16,384 and (A) the 2^19.5 distinct-index floor over 2^20 evaluations (2.08 s on one box-2 core), no low-entropy site. The acceptance now runs the whole program, so the remaining difference from the census is the dataset (the acceptance's seed-keyed closed-form words against the chain's memory-hard items) or the census's consecutive nonces; a band that exists only under the real dataset is outside the reach of any in-acceptance rule unless the acceptance builds the real dataset (a 256 MiB cache fill and a 1 GiB day per candidate: seconds to minutes per attempt). The attack-pass lane localises p23's zero (which iteration, which registers, whether it reproduces on the closed-form dataset; the register history at instruction 38 on the memory-hard day, the closed-form words and random against consecutive nonces), which decides whether the rule is nonce-aware, dataset-aware or structural; neither is a 19:00Z build with a 75-minute census behind it. THE DECISION (the coordinator under main's accepted plan, 16:1x UK): 0.3.21 ships byte 5; sub-version 3 is 0.3.22's. The hash lane commits the shadow fix with the agreement test as sub-version 3's first commit (a new stream, new ids, byte 7 unchanged; AP-F8-2's exhaustion half FIXED-AND-PASSED at 8bdcbdd8 and AP-F8-3 fixed in the ledger entry); (A) and (B) held uncommitted until the localisation lands, with the cost of each form on one line (the dataset-aware form's cache fill per attempt decides it). The node lane and the shipper told: no re-pin and no CLASS_SIGNAL change in 0.3.21; byte 7 reserved for sub-version 3, byte 6 for class v5. Per tier: no miner, pool or chip consequence tonight; the auditor's record carries sub-version 1's 11 of 64, sub-version 2's 8 of 56, AP-F8-2 closed and AP-F8-3 found and fixed, with the uniformity rule open as a named item. THE N15 DRIFT FIX DONE (the node lane, 14:13Z): rides 0.3.21 as two commits after f95178a1, branch numbering-fix on the mirror at d8bceca5 (a6864e36: the chain path's continuity rule, the orphans above the fork point handed to the reorg unwind; d8bceca5: the start-time self-check from the restart pin against the DAG's selected parents, the first break unwound and re-walked, and recordsContinuous and continuityBreak on the status RPCs so a prover claims only on true); the scans named both events (p1-5090's short reorg path at 15:51Z on 6 October, p2-3090-3's inherited snapshot at 21:09Z); two unit tests known-failed first, the exec suite 35 passed, the kaspad check green on build-2 at 14:13Z; the live line is the fleet's restart of the two drifted boxes on the 0.3.21 candidate. Plan 6.9 reads byte 5 with igneum-pow 8c728ca3, no CLASS_SIGNAL change. SUB-VERSION 2's FINAL VERDICT (the attack-pass lane; the 64 seeds p2 to p65 at 2^24 nonces, chain path, window-model control, box 2, 13:10:15Z to about 14:40Z; pairing id a788661687db4bb3): FAIL, 55 of 64 PASS (0.9915x to 1.144x), 9 FAIL.

Seed Ratio Hottest item, reads Site, instruction, share of the site's reads in the top 0.1 percent Source
p23 4.82x 0x000000, 41,727 site 7, instruction 38, 9.43 percent or-then-xor same-operand mask over a mulhi (r6 and not r4)
p19 3.32x 0x400000, 28,114 site 15, instruction 62, 6.64 percent unchanged from sub-version 1
p15 2.57x 0x000000, 12,313 site 2, instruction 12, 4.49 percent
p18 2.50x 0x75f0fd, 13,866 site 6, instruction 30, 5.55 percent
p56 2.01x 0xbeb53c, 6,091 site 2, instruction 10, 3.34 percent unattributed
p10 1.50x site 8, 2.04 percent unattributed, identical to sub-version 1
p8 1.38x site 14, 1.42 percent unattributed
p34 1.25x site 1, 1.35 percent
p4 1.22x site 1, 1.45 percent unattributed, 1.57x on sub-version 1

Every failing seed is ONE low-entropy load site; the mechanism is lineage-blind (AP-F8-1's residual) and the acceptance could not see it because it never ran the shadow block (AP-F8-3). SUB-VERSION 3's FIRST COMMIT: ca3-v4-amend ddacfbd3, 14:20:37Z (origin and build, gate GREEN): the acceptance executes the shadow block as the hash does, the test pins it to verify.rs on the seven v4 programs; PROGRAM_SUBVERSION_V4 = 3; byte 7; (A) and (B) held in a stash. Epoch-0 id a785001687d8688a (must-differ c120d7963abdcd96, 1a4230699a6b9c60, a788661687db4bb3; the devnet seed still accepts at attempt 1, so its program is sub-version 2's under the new id); the seven fingerprints unchanged from sub-version 2 for the same reason (e370fb2080b7dbb1, b7237555d31fc3cf, b6b167fa15dfe2c9, 28bdf65eff33f2c4, e26d38c46f3f1b16, dd8fdf6ff4f59eed, 8bf40f5cb858d835; control 90f794dd556f7a3b; Metal = Apple OpenCL 14:18:41 to 14:19:13Z), so the fleet and PC 2 G1s already read them and the G1 on sub-version 3's packs is a re-run of a known result; packs zip packs-ca3-v4-sub3 sha256 4f2445c50c58d76a5544023492d8b858d0b07c5e372d31f9c90c4ce51f829154; the ledger entry carries AP-F8-2's exhaustion half FIXED-AND-PASSED at 8bdcbdd8 and AP-F8-3 fixed here; the suite and the 4,096-seed census at ddacfbd3 on box 2. THE LOCALISATION (the hash lane): p23's band is dataset- and nonce-independent and reproduces in the acceptance's own execution: site 7 (instruction 38) reads r6 after 25 mulhi, 31 or r6 |= r4, 35 xor r6 ^= r4, which is r6 and not r4, an AND mask the lineage rule counts as fresh because the xor's operand is the or's; over 2^20 evaluations on the closed-form words site 7 reads 874,953 distinct word indices against about 1,046,500 at every other site (0.84 of uniform, 2.2 s on one box-2 core); over 2^24, 8,979,203 against about 16,260,000 (0.55, 35 s). THE COST LINES FOR THE SECOND COMMIT (0.3.22): structural (an abstract value class tracking shared operands) 0 s per attempt, this idiom only; the distinct-index ratio at 2^20 2.2 s per chosen candidate; at 2^24 35 s; no dataset-aware form needed (no cache fill). The hash lane's recommendation: the ratio at 2^20 with the threshold set from the clean seeds' per-site spread (p23's site 0.84; every clean site 0.995 to 1.000), plus the structural rule for the idiom so the ratio is a never-firing check on it. The attack-pass lane's verdict: sub-version 3 is the stream to gate and cannot read green by 19:00Z; byte 5 for 0.3.21 stands on its evidence. THE THRESHOLD NUMBERS FOR SUB-VERSION 3's SECOND COMMIT (the hash lane, box 2, the per-site distinct-index ratio over 2^20 evaluations against the window expectation N minus N^2 / 2W, on the 64 F8 programs as ddacfbd3 draws them, 2.8 s per seed on one core, all sixteen sites): the 55 clean seeds' per-seed minimum 0.9962 to 1.0000 (median 0.9999); over all 880 clean site rows min 0.9960, p1 0.9990, p5 1.0000, median 1.0000. The nine failing seeds' minimum site: p23 0.8361 (site 7), p18 0.9274 (site 6), p19 0.9335 (site 15), p15 0.9432 (site 2), p56 0.9654 (site 2); then p34 0.9927, p4 0.9961, p8 0.9963, p10 0.9963. A threshold of 0.98 sits 0.016 under the clean minimum and 0.015 over the strong five's maximum and rejects exactly those five; the weak four (1.22x to 1.50x in F8's gate) sit inside the clean spread at 2^20 and no threshold reaches them without rejecting clean seeds; a 2^24 run (35 s per candidate) on the weak four, p23 and five clean seeds measures whether they separate there (p23 went 0.84 to 0.55). The structural rule is in and bites where the band was: with the shared-operand relation tracked in the draw and in (a'), p23's attempt 1 draws site 7 from r5 instead of r6 (the or-then-xor on r4 marked r6 lossy); the devnet seed still accepts at attempt 1 (id unchanged); the (a') fixpoint carries the relation. THE COORDINATOR'S LINE: decide by the 2^24 lines: if they separate the weak four from the clean seeds with a gap at least the 2^20 gap, commit (iii), the 2^20 ratio at 0.98 always plus the 2^24 ratio only when the 2^20 per-seed minimum sits under a band edge set from the clean p1 with margin (0.999 fires it on about 1 percent of clean candidates, 35 s once an hour on a node); otherwise commit (i), the 2^20 ratio at 0.98, and name the weak four (p4, p8, p10, p34) as the open tail in the ledger and the commit, unattributed-and-chased, not absorbed. SUB-VERSION 3's SECOND COMMIT: ca3-v4-amend 017e7037 (017e70376489251e18564c0abce7e466e606c8b3; origin and build; gate GREEN; CI run 37639406567 queued), choice (i) by the 2^24 lines: 2^24 does not separate the weak four from the clean seeds (weak p34 0.9181, p4 0.9614, p8 0.9630, p10 0.9612; clean p44 0.9612, p52 0.9613, p3 0.9971, p2 1.0004, p5 1.0004; p23's chain attempt 1 1.0004), two clean seeds sitting on the weak four's value, so any 2^24 floor that reaches them rejects clean seeds. Committed: the per-site distinct-index ratio at 0.98 over 2^20 alone (ACCEPT_UNITS_DISTINCT_V4 = 4096, MIN_DISTINCT_RATIO_V4 = 0.98; expectation per site N minus N^2/2W, window 2^28 >> min(win, 2), the shadow executed), no 2^24 stage, (B) unwired; the structural shared-operand rule in the draw and in (a'); the open tail named in the ledger and the commit: p4, p8, p10, p34 (0.9927 to 0.9963 at 2^20), unattributed and chased.

Threshold line Value
Floor at 2^20 0.98
Clean minimum over the 55 clean seeds' 880 site rows 0.9960 (p1 0.9990, median 1.0000)
Strong five p23 0.8361, p18 0.9274, p19 0.9335, p15 0.9432, p56 0.9654
Margin 0.015 to each side
Cost per chosen candidate one 2^20 pass, 2.1 to 2.2 s on one box-2 core, once an hour on a node

Known-failed test class_v4_distinct_ratio_rejects_the_low_entropy_band green on box 2 (12.95 s): p15 attempt 3 (52638ea2e8b0fd68) site 2 at 0.943; p18 attempt 2 (9a37e9489d8ba698) site 6 at 0.927; p19 attempt 0 (79d7441de0689223) site 15 at 0.933; p56 attempt 2 (486a8ad2701ec3b5) site 2 at 0.965; p23 attempt 1 (d65122675f16a1c7) draws site 7 from r5 and passes, and with r6 put back is refused by (a') UnfreshLoadSource and, run anyway, by the ratio at 0.836. Stream unchanged from ddacfbd3 (re-export diff 0 on all eight packs): id a785001687d8688a, the seven fingerprints and the packs zip sha256 4f2445c5... as recorded. THE SUITE AT 017e7037 on box 2: 103 of 103 (64 lib + 7 derive + 4 mixer + 19 packs + 2 recheck + 7 scratch, 3 diag ignored), rc 0; the lib tests 140.8 s against the 41 s whole-suite line at ddacfbd3, because every class v4 draw in the tests pays the 2^20 ratio pass on its chosen candidate (2.2 s each): a CI-time cost, not a node cost (one pass per epoch draw). CI run 37639406567 on 017e7037 success. THE CENSUS AT 017e7037 (box 2, 4,096 chain-shaped seeds plus F8's p1 to p3, draws in parallel across the cores; tools/ca3-v4-uniform now draws across available_parallelism since the serial run became a four-hour job): 4,099 programs, 0 lossy-sourced load sites of 65,584 (57,322 injecting, 8,262 bijective), 0 exhaustions; attempt histogram 0:1297 1:899 2:609 3:416 4:298 5:197 6:125 7:92 8:54 9:46 10:21 11:14 12:13 13:9 14:6 16:2 17:1, mean 2.086, max 17 (ddacfbd3 read 1328/917/622/409/284..., mean 1.998, max 17): the ratio refuses about 4 percent of candidates that pass every other test, one extra attempt on about one seed in twelve, the worst case unchanged at 17; devnet epoch-0 at attempt 1, id a785001687d8688a; F8's p2 attempt 5, p3 attempt 1. The attack-pass lane's class check: ddacfbd3's shadow-executed verdicts against 8bdcbdd8 on 598,678 chain-shaped seeds move 11,990 (2.0 percent) to a different attempt, 0 exhausted, max 32; on 017e7037 the pairing holds and the 64-seed gate at 2^24 plus the 10^6 exhaustion count run to about 16:05Z. The hash lane's ledger lines 2a111fb1 on origin and build (the GitHub 500s cleared on their own), CI run 37642582140 success at 15:25Z; the hash lane has nothing in flight. Nothing on the hash side stops a cut of sub-version 3 at 017e7037 for 0.3.22; then the attack-pass lane's 64-seed gate at 2^24 and 10^6 exhaustion count. Owed as before: G2, G3, the ladder re-measure, AMD (PC 1), the 2019-class core, the fleet and PC 2 G1 on the sub-version 3 packs (a re-run of a known result). release-0.3.21-node STAGED (the node lane, 16:0xZ): 96161037 on the mirror, at the shipper's sweep-end word, in the final order on 55768f88 (c631c64b, 52e96c94, f067f7c1, b0444f51, 437f0438, 2e32d5f6, f95178a1 cherry-picked, a6864e36 and d8bceca5), pairing igneum-pow 8c728ca3 at byte 5, no re-pin. The whole set on the tip green: consensus-core 126, the consensus crate whole (lib 120, both integration targets), igneum-miner 25, kaspa-pow 17, igneum-exec 36, the three checks, 15:49 to 15:57Z on build-2. Binary built on build-1 at 15:58Z, igneumd sha256 f99340b3cf4ce32e, the string read back; the digest eada4bda on the previous live object and 4bbbe816 on the published floor file (so the 0.3.20 floor file is published), as the pin reads them. The node lane's digest and mixed-version gates on it from 16:00Z; the fleet's set from the same minute; plan 6.9 carries the steps and the two box-input rules the staging added. THE 0.3.20 RECORD (the shipper, UTC). Cases: the dc141409 run on c18-1 CASES END rc 0 at 12:37:18Z (both halves PASS); the c4459193 run on c20-1 CASES END rc 0 at 14:54:02Z with its relay half void (one RunPod host, no hairpin) and the poison half PASS (13 rejected, 0 accepted); main's (b): the publish on the dc141409 cases plus the diff argument (the class byte the only touch in the cases' territory) and c19-1's tip-following, with the separate-host relay re-run on c19-1 on the live digest as the halt condition and the Discord card's gate (CASES END about 16:25Z). PUBLISH 14:54:17Z (15:54 BST): manifest 0.3.20, mac DMG sha256 73796c5f..., Windows installer 45b2f3fb..., the hive tar d9dd12df... on the public alias. THE FLOOR FILE: program_class_v4_activation_daa 900,000 (the live DAA 294,073 at 14:51Z; 294,073 + 604,800 = 898,873 rounded up to the 3,600 boundary), window 86,400 unchanged, file sha256 294f1f80...; the digest 4bbbe8162ea9fff277aa5b16b4ffad9e2262ba5e6a5acac7b697ff77211e7328 read on c4459193's binary before the cut and on the hub's handshake line after. The pin c4459193, igneum-pow 8c728ca3, byte 5; the sweep's node pair a80ed39c / 70a5180f (the build-server lane's native build of the same tree). THE SWEEP complete 15:39Z (16:39 BST): wave 1 the hands (observer-node, node1 at 14:57Z), the Mac (15:23Z on its poller, interface 1.0.1), the hub, pool-1 and the eight heaviest voters (15:04 to 15:21Z); wave 2 the four lighter voters (15:23 to 15:26Z); wave 3 Devnet 2's four pods and bps-seed (digest 4a0b8726 unmoved); the first new-side lock 9313 at 15:28:08Z after a 23-minute split; every lock line "sweep complete before 13 October 09:00 UK (the margin; the floor is now DAA 900,000)". 0.3.17 nodes remaining: PC 1 and PC 2 (offline for the founder's cable work; their apps update on their pollers on return) and the three testnet seeds (on the testnet, not on the devnet's floor); no devnet node of the fleet, the hands or the Mac on 0.3.17. EARLIEST FLIP: the floor at DAA 900,000 is about 7.0 days of DAA from the publish (605,927 DAA at about one a second), so about 14 October 23:00Z (15 October 00:00 BST) at the earliest, and only once the seven 86,400-DAA windows read 95 percent of blue weight signalling byte 5; the live floor of 831,600 (13 Oct 08:00Z) is replaced by the published file on every swept node, so the chain never flips to the 6 October stream. Per tier: a solo miner on the Mac or a swept box mines on; a PC miner on 0.3.17 is refused by digest when it next connects until its app updates (its poller does this on return; nothing by hand); the pool and the hub are on the pin; the auditor reads one object, one digest, one floor.

SUB-VERSION 3 PASSES BOTH GATES (the attack-pass lane, the close line dated 7 October 2026): class v4 sub-version 3, commit 017e703764 on ca3-v4-amend, pairing id a785001687d8688a (verified by the harness). F8's 64-seed census (p2 to p65) at 2^24 nonces each, chain path, window-model control, box 2, 14:51Z to 16:00:20Z: PASS, 60 of 64 under 1.2x (0.9915x to 1.144x); the only four over are the named tail, unattributed and chased: p10 1.5036x (identical to sub-versions 1 and 2, hottest item 0x4004da at 362 reads, no predicted source), p8 1.3776x (0x837de4, 420 reads), p34 1.2505x (0x800010, 541 reads, the one-bit value through sub at 5), p4 1.2167x (0x4000e7, 355 reads); every strong seed gone (p23 4.82x, p19 3.32x, p15 2.57x, p18 2.50x, p56 2.01x all under 1.2x); the worst ratio on the stream 1.50x; the tail's hottest items carry 355 to 541 reads of 2^31 (one to two per 2^22 items above the mean), no chip consequence. The exhaustion gate as it is: the chain-path count on 017e7037 runs slowly (the draw evaluates (c'') at 2^20 per candidate: 20,532 seeds in 59 minutes, 0 exhausted, 0 panics, max attempt 29), so a 10^6 count is two days away and is not waited on; the substance is met by construction (the 256 cap and the last resort unchanged from 8bdcbdd8, 0 of 10^6 there) and by measurement at 017e7037 on 24,631 seeds (0 exhausted, max 29; r about 0.68); the count runs on as a strengthening line. The node's epoch draw now costs about 2 attempts at 2.2 s each, 4 to 5 s per epoch on slower cores, once an hour. The hash lane's ledger at 6941da1d. SUB-VERSION 3 AT 017e7037 IS THE FROZEN GENERATOR FOR 0.3.22 (byte 7), THE TAIL RULED (main, 18:1x UK): the four seeds (p10 1.5036x with its hottest item at 362 reads, p8 1.3776x at 420, p34 1.2505x at 541, p4 1.2167x at 355, of 2^31 reads) are accepted as the window model's unattributed residue at 1.22x to 1.50x with nil chip consequence; the AP-F8-1 row CLOSES with that wording and the hottest-item counts beside it; the 10^6 count on 017e7037 runs on as the strengthening line. The attack-pass plan's start 15 October or the morning after. 0.3.21's FIRST CANDIDATE 96161037 (sha256 f99340b3cf4ce32e, string read back) passed the node lane's two gates on its own binary: the digest gate 15:59:54Z to 16:01:32Z PASS (a89be8a7 with the peers right; db9a85f9 refused, no peer); the mixed-version gate 16:01:53Z to 16:12:05Z PASS (one digest b0afb2ee on five; 252 new and 352 old accepted, 0 rejected; counts equal at 316, 493 and 604 through both clean joins and the restart step; no panic); the node side complete; the fleet's set on the same binary (the kept start with the ids gate, the wipe canary, the cases rerun, the 12 GB line, N15's restarts of p1-5090 and p2-3090-3) is what the shipper's pin word waits on; byte 5 throughout, nothing on the class v4 seam moved. DEVNET 3 NOW (the founder through main, 17:3x BST): 0.3.22 is the Devnet 3 release (a fresh network object igneum-devnet-3 with every activation at 0 and no override file, the era VDF fork, class v4 sub-version 3 at byte 7 from genesis), the node building on build-1, genesis by 17:30Z (18:30 BST). THE HANDOFF (17:3x BST, inside the 17:40 BST line, to the shipper and the node lane): igneum-pow 017e703764 (the audit-freeze-2026-10-07 tag; 2a111fb1 and 6941da1d above it docs only), object byte 7, PROGRAM_SUBVERSION_V4 = 3, devnet epoch-0 program id a785001687d8688a (must-differ c120d7963abdcd96, 1a4230699a6b9c60, a788661687db4bb3), kit packs-ca3-v4-sub3 zip sha256 4f2445c50c58d76a5544023492d8b858d0b07c5e372d31f9c90c4ce51f829154, the eight fingerprints as recorded (equal on Metal, Apple OpenCL, the fleet 5090 and PC 2's 5090), both attack-pass gates GREEN, suite 103 of 103, CI success; the open items stated as open: the four-seed tail under main's ruling (the attribution for 0.3.23), the 10^6 count as a strengthening line, the 4 to 5 s epoch draw, the owed measurements that do not gate Devnet 3. NO FURTHER HASH CHANGE RIDES ON 0.3.22; anything from the tail goes to 0.3.23. The node lane stages the re-pin on the 0.3.21 tip as its own commit (the fork commit and the kaspa-pow suite line owed to this record); the hash lane's sub-version 3 pairing follows it. THE PUBLIC CHIP TEXT REWRITTEN LAUNCH-FIRST (the founder: "I thought we were making it 2.1 from launch?"; master 9b996d06, docs/plans/counter-asic-3-public-text-2026-10-07.md): the testnet and mainnet objects set program_class_v4_activation_daa 0, so class v4 is live from genesis and the launch number is 2.1x to 3.9x on day one; the three texts and evidence row 17 lead with that (labels kept), then class v5, then the 5x to 9x only as the class v3 baseline the work started from, the devnet's activation height a devnet fact only; no em dashes, no prize mention, eight columns; with the site lane to apply in the same deploy as the padding sweep (its commit and deploy time owed to this record). STOP-THE-LINE ON MASTER's POW SUITE (main through the CI steward, 18:4x BST): red since 16:31 BST (runs a4eaf76 and 1210158d; program_ids_differ_between_class_v3_and_class_v4_of_one_seed and cpu_recheck_equals_the_worker_reference_for_class_v3_and_class_v4 fail on packs-ca3-v4/v4-devnet-epoch0) because era-vdf's merge 0e2d6b1c put the sub-version 1 line's generator on master against tests/recheck.rs's pins, never CI-run. Ruling: the hash lane merges ca3-v4-amend's tip 6941da1d to master through merge-to-master.sh within 15 minutes, provided its epoch-0 id equals the frozen object's; the coordinator verified the condition (6941da1d's igneum-pow byte-identical to 017e7037; recheck pins 0xa785_0016_87d8_688a with the three must-differ ids; PROGRAM_SUBVERSION_V4 = 3), so no revert; master is the 0.3.23 line after this, 0.3.22 keeps its pin at 017e7037. EXECUTED: ca3-v4-amend on master as merge cf7d6ccb (pushed 16:45:48Z through merge-to-master.sh, try 1; the branch gate GREEN, 55 checks in 317 s on 874e945d; master ac8ed2f1 merged into the branch first with docs/fud-ledger.md keeping both sides and igneum-pow taken wholesale from 6941da1d, byte-identical to 017e7037); master's CI run 37654633279 on cf7d6ccb in progress from 16:46:10Z, the pow job's conclusion owed. Master's igneum-pow is now the frozen sub-version 3 generator. THE 0.3.22 RE-PIN STAGED (the node lane, 16:38Z): fork commit bd710a36 on release-0.3.22-node (igneum-pow 017e7037 archived beside the fork as igneum-pow-amend, byte 7, epoch-0 id a785001687d8688a must-equal, the three must-differ ids, PROGRAM_SUBVERSION_V4 read as 3); the line's candidate fa7f854f (the re-pin, the era VDF merge f2ecf452, the igneum-devnet-3 object with program_class_v4_activation_daa 0 and a one-day signal window, so byte 7 is stamped and hashed from genesis); the kaspa-pow suite on build-2 from 16:38Z, its line owed; the hash lane has the commit for its pairing run. THE kaspa-pow SUITE ON THE 0.3.22 CANDIDATE 21d8f454 (build-2, 16:47:10Z): GREEN 17 of 17; the pairing test reads PROGRAM_SUBVERSION_V4 = 3, epoch-0 id a785001687d8688a, the three must-differ ids hold, the chain draw at attempt 1 against class v3's 0 on the test header; the candidate's digest for igneum-devnet-3 ab9af79f...ed23; the node stamps object 7 (block version 1794) from genesis. MASTER GREEN ON THE POW FIX: CI run 37654633279 on cf7d6ccb success at 16:54:51Z, the igneum-pow job success; master's igneum-pow the frozen 017e7037 byte for byte; build-1's amend checkout synced to 874e945d (its packs-ca3-v4 carries the sub-version 3 kit). THE CHIP TEXTS LIVE (the site lane, site-ui-5): sections 1 to 4 applied verbatim in b34d1932, master cc593483, live on igneum.network at 16:47Z (home row 03 "under class v4 from the first block"; /litepaper#chip-model the new paragraph and the reordered table with the class v3 row last; /miner the new line; /evidence row 17 "2.1x (k = 1) to 3.9x" in eight columns); the litepaper's abstract rewritten launch-first too; tools/ci/ledger-text-check.mjs X35 asserts the launch-first sentence on the home page and "so the launch number is the class v4 row" on the litepaper; no prize mention. /claims (the litepaper's limits section) rewritten launch-first by the coordinator in the litepaper's chip bullet (2.1x to 3.9x under class v4 from the first block with its labels, class v5, then the class v3 baseline "never the launch state", the recompute chip under 1x, the X9 history), /claims rebuilt from it, the ledger text check 61 of 61, the padding and overlap sweeps green in the 56-check gate, master 0a999646 at 17:01:47Z. DEVNET 3's FIRST GO (the fleet lane): dn3-g1 on 21d8f454 up 16:50:21Z from an empty datadir, digest ab9af79f matching the build-1 read, genesis a6fa348e executed (chain id 4463), object 7 / block version 1794, era VDF from DAA 0, no override file, mining from 16:50:42Z; the dn3_ observer running since 16:38:29Z; DN3_GO_DATE=2026-10-07 in /srv/hands/dn3/dn3.env, the hash-origin timer's first dn3_ report 8 October 08:30Z. BUT NO BLOCK ACCEPTED: dn3-g1 refuses every block its miner finds with "the block timestamp is too far into the future: block timestamp is 1791417600001 but maximum timestamp allowed is 1791392281213" (16:57:51Z): 1791417600001 ms = 2026-10-08T00:00:00.001Z, the template stamping genesis + 1 ms, so the igneum-devnet-3 genesis object carries 8 October 00:00Z, one day after the intended 7 October 00:00Z; every block is seven hours in the future and refused before PoW on any node with any miner or pack; the pack is not the suspect (the node draws the epoch's program under its own igneum-pow and hands the pack to the worker; the exported kit is for G1 and recheck only). The fix is the node lane's (a past genesis timestamp, moving the genesis hash and the digest) and a rebuild; the fleet reruns the go within the minute of the new pair; if the corrected build lands by about 17:20Z the pair lock is about 17:35Z (18:35 BST). Spend at 17:00Z about USD 410 of 1,000. GITHUB SUSPENDED (17:0xZ): every push to origin refused with "Your account is suspended" (403); the API reads 404 for the user igneum-labs and the repo (the shape of a suspended account, not a revoked token); with the founder (the ticket route given by main); until GitHub answers, every lane pushes to the build-1 mirror (/srv/igneum.git over ssh) and the mirror is the record, merges landing through the box gate stamp under the shipper's exception window. This branch is on the mirror at a33a7859 (17:09Z); master's last origin landing 0a999646 (17:01:47Z). DEVNET 3 MINES (the fleet lane, 17:08Z): dn3-g1 on the corrected candidate 69d1b56e (genesis 7 October 00:00Z, hash 4020cb43..., digest 83eb50cdf2eda4cb...) accepted its first block at 17:06:19.920Z, 3 blocks by 17:06:44Z, 0 rejected; dn3-g2 joining, the pair's first common lock about 17:15Z (18:15 BST), then the late joiner and the canary's ten minutes; the hands pair for 69d1b56e landed 17:05:54Z, the shipper ruling whether the genesis bytes are the node lane's or the hands'. Per tier: the first chain that hashes class v4 sub-version 3 (byte 7) from genesis is live on the fleet; the launch-first chip texts describe it exactly. DEVNET 3's EPOCH-0 PROGRAM ID (the node lane): fce15bf61030be57 on igneum-devnet-3 (genesis 4020cb43...b925), read in the 0.3.22 miner's "cache ready" line on build-1 at 17:10:39Z and on dn3-g1 at 17:12Z, the node accepting 85 of 85 GPU blocks; a785001687d8688a stays the shared devnet's epoch-0 id (genesis edc4fa84) and the kaspa-pow pairing pin; the pairing is unchanged, the id follows the seed; the fleet's pack-id gate reads fce15bf61030be57 at epoch 0 and the node's per-epoch value after; the exported kit's eight packs are the shared devnet's seeds, so a Devnet 3 kit, if the hive wants one, is a re-export over 4020cb43's seeds (the hash lane's, on request). DEVNET 3's PAIR AGREES (the fleet lane, 17:19Z): dn3-g2 up 17:17:58Z on the same bytes, digest and genesis, synced from dn3-g1 and mining from 17:18:15Z; the pair agrees on every determined finality checkpoint (20, 21, 22 on identical blocks in both logs); 702 blocks, 0 rejected on either, by 17:19:08Z. The first LOCK lands about 19:10Z (20:10 BST): the object's finality window is 7,200 DAA ("window filling, 681 of 7200") at about 1 block/s, the object as cut, nothing wrong. Two independent nodes agree on the chain since 17:18Z; finality signatures start two hours in; the hash-origin daily (dn3_ tables, DN3_GO_DATE 2026-10-07) counts from today once the observer units are enabled on the shipper's go. The shipper rules whether the genesis is declared on the pair's agreement or on the first lock; the late joiner, the empty-datadir canary (ten minutes) and the spare placing on the hands pair; the standing boxes' second nodes after the joiners on the shipper's word. Spend 17:20Z about USD 412 of 1,000. GITHUB RULE (main through the shipper, 18:02 BST): no push, fetch or poll of GitHub from this lane or its sub-lanes, not even a retry; the box mirror on build-1 and build-2 is origin and the box gate stamp the verdict until it lifts. DEVNET 3's EPOCH-0 PACK EXPORTED (the hash lane): program.json 0xfce15bf61030be57, attempt 0, sub_version 3 (dn3-g1 drew the export path's seed); igneum-pow at 874e945d (byte-identical to 017e7037 and master's), --epoch-hex and --era-hex the genesis 4020cb43...b925, class mx8-eraaf3a9139+sh256x27, day bytes "igneum-day/" || le64(20733) (the chain's rule day = timestamp_ms / 86,400,000; the program and id day-independent, the dataset and fingerprint rolling with the UTC day); Metal fingerprint e510ad92b4d24846 at 2^24 from base 0, Apple OpenCL equal, vectors 3 of 3; on build-1 /srv/artefacts/packs/v4-devnet3-epoch0/ and .zip sha256 e025750f71175ed14d6e2a24e387ebbf1979b1cd0faee9139c41a7671165b334, the sub3 kit zip beside it (4f2445c5...); in the 0.3.22 hive package order with the kit. THE FOUNDER'S THREE ORDERS (through main, 18:3x BST), with his correction (18:4x BST: everything in-house, nothing external): (1) BUILD CLASS V5 NOW on the 0.3.23 line (program class v5, its own activation height, object byte 6): the generator and verifier in igneum-pow (+0.2 ms per warp against the 10 ms gate), the node side (the state commitment into the dataset derivation, the stateless/stale-chip rule known-failed first on a stale dataset), the hot-set, weak-day and shadow-redundancy rules routed to this class, the attack-pass families re-run on v5, the kit for Metal, CUDA, OpenCL/AMD and Intel with fingerprints equal, the crossing on Devnet 3 by height after its gate, miner cost rows per card; the v5 lane resumed with the order, owing tonight the design-to-code gap in one list and a UTC clock for the first v5 pack. (2) CRYPTANALYSIS IN-HOUSE: no outside firms, no paid lots, no briefs to anyone; the three targets (the mixer M_r, the chained cache, the acceptance rule) attacked by three adversarial lanes that have never worked on the hash code, each given only an outsider's inputs (the public kit, the frozen object, the spec, the attack-pass harnesses), a written attack plan first, a budget of box hours, a report in the attack-pass shape (the claimed break or the bound reached, reproducible); the Counter ASIC lane the defender, main ruling disputes; plans within two hours, first results by tomorrow evening; a coordinator lane spawned for it (docs/plans/cryptanalysis/in-house-pass.md, funding.md's lots rewritten to the internal pass). The served sentence "the cryptanalysis plan buys three external lots" rewritten on the litepaper, /claims and evidence row 17 to the internal adversarial pass, labelled internal, the one outside check staged on its escrow and the publish word (the served text never names the prize or the founder, by the forbidden-strings gate). (3) OWED MEASUREMENTS on PC 1: released tonight after the shipper's 0.3.21 host build (the line "PC 1 released" about 18:05Z, the window to 17:30Z on 8 October, an elevated job allowed under the standing rules); the hash lane prepares the three job files on the sub-version 3 kit (the 9070 XT G1 and ladder rows, item 6's step costs on AMD, the 5090 clock rows elevated, dr736 if it fits), published one at a time on the coordinator's relay of the line, --cards-off on the measured card alone, the desk left usable; the rows land in the public table with their labels. Nothing in (1) or (3) reaches outside the fleet, the boxes and the PCs. DEVNET 3's PROOF WINDOW OPENED 17:57:05Z (the fleet lane): coverage from 17:44:23Z (dn3-x1, an RTX 3060 12 GB, the sm_86 SP1 floor, from DAA 0; the first segment 1024..1031 submitted 17:45:49Z, 86.1 s end to end); the first records PAID by dn3-x1's key, segments 1256..1263 (0.7036 IGN) and 1272..1279 (1.5993 IGN) in block 1403, paidShards 10 at 17:57Z; the 24 hours run to 17:57Z on 8 October; sizing: a 3060 proves a segment in 84 to 86 s (about 42 an hour) against 450 segments an hour at 1 block/s, 11 cards for a share of one, 15 placed (14 more 3060 12 GB pods on distinct Vast machines, USD 1.07/h together); a runbook rule found: a Devnet 3 block builder carries a proof record only after its own node verified it, so every Devnet 3 miner node needs IGNEUM_PROOF_VERIFIER on the host verifier (the four miners ran bare for 11 minutes, 72 records pending and 0 carried; dn3-j1 restarted with it at 17:54:37Z and carried the first). THE UTILISATION TABLE (the fleet lane, 18:00Z, for the founder): 36 rented boxes plus the Hetzner seed, 37 GPUs, USD 197 a day at this size, today's total about USD 432 of 1,000; idle in the hour 12 by the letter, 9 of them Devnet 3 boxes rented in the last 15 minutes and syncing, 3 the 0.3.21 warm set standing between windows; the fleet's recommendation: stop Devnet 2's four boxes (USD 59.76 a day; Devnet 3 is now the staging chain) on the shipper's word, fold the 0.3.21 warm set (USD 12.72 a day) into Devnet 3's relay trio when 0.3.21's last line closes. THE PUBLIC BENCH TABLE (main's order): /miners now carries every measured card, 37 rows, with watts, MH per watt, the class v4 cost per card and the tuned state (the 5090 stock 136.1 MH/s at 350 W and tuned 127.71 at 226.8 W; the 4070 at its tune point; the 9070 XT, the M5 Max (no lever), the 5060 Ti, the Arc B580, and the fleet's rented-card sweep of 7 October: the 5080 71.16 at 143.4 W, the H100 248.70 at 385.6 W, the B200 416.35 at 855.6 W, the 4090 hands row 52.25 at 183.1 W, down to the 4060 Ti 20.10 at 77.5 W; every fleet row stock, bench only, labelled measured by the fleet or reported by the fleet). CLASS V5's DESIGN-TO-CODE GAP (the v5 lane, 19:00 UK; section 13 of docs/design/class-v5-stored-state.md at c17bc04b): igneum-pow's class v5 rebased onto the frozen sub-version 3 (v5 and its rungs draw under (a'), (c''), the shared-operand rule, the 256 cap and the last resort by merge); the fork rebased onto release-0.3.23-node with class v5 pinned to object byte 6 counted EXACTLY (byte 7 is v4 sub-version 3; the bytes are no longer ordered by class); the gap about 40 agent hours (17 the v5 lane's): the +0.2 ms per warp on the Mac (1 h), the AP-F4-1 and AP-F1-1 rules with their known-failed cases (3 h each), the attack-pass families on the v5 stream (4 h), the kits (Metal and CUDA hosts uploading leaves.bin, 2 h each; OpenCL/AMD and Intel 3 h), G1 on the 5090 and the Mac (2 h), the Devnet 3 crossing by height (3 h), the miner cost rows (3 h), the snapshot wire's day streams (3 h), the pool's per-epoch state fetch (2 h), the proof witness (4 h), the spec text (2 h); the first v5 pack's clock (Devnet 3's genesis as epoch and era seed, day 20,733) follows the suite and the day-stream bin. THE IN-HOUSE ADVERSARIAL PASS (the crypto lane, 19:05 UK): crypto-engage deb0011e on the mirror; docs/plans/cryptanalysis/in-house-pass.md (outsider inputs and withheld files, the three lanes, the budget 8 box-hours each and 24 total with a ceiling of 48 on the coordinator's word, the review roles, the clock, the label rule); funding.md's lots rewritten to the internal pass with no cash row and every firm name removed; the three lanes adv-mixer, adv-cache and adv-accept spawned 19:1x UK with outsider-only inputs, plans due 21:10 UK, first results by 18:00 UK on 8 October; the Devnet 3 epoch-0 pack added to their inputs. THE PC 1 QUEUE PREPARED (the hash lane, c1a1f1d7, nothing published): the kit fetch (zip sha256 1d441f5a..., the 8 sub-version 3 packs plus the ladder packs sh256x13/27/53/88 and sh64x52); the class v4 efficiency pass on the 5090 (elevated, --cards-off, a 17-step clock-lock grid from unlocked to 1,400 MHz with the four Ember caps on it, v4 then v3 at each step for about 60 s, the fingerprint on every step, nvidia-smi at 1 Hz, -rgc in finally; nvidia-smi has no voltage-offset lever, the lock walks the driver's V/F curve; about 40 minutes; the owed 5090 clock rows subsumed); the same on the 5080 (its unlocked row the stock point against the fleet's 71.16 MH/s); G1 on the 13 packs and the AMD ladder rows on the 9070 XT (the ladder packs' Mac fingerprints sh256x13 ff8f707210659eb1, sh256x27 892b6d55a7ddcfcb, sh256x53 663c73c61f62cc54, sh256x88 ec7ca430a061fa59, sh64x52 9dd010f79d8ca9f4); item 6's step costs on AMD (run e); the 5080 full Ember Tune (not elevated, the Power Helper carries the rights); the 9070 XT tune pass (the tune_line before and after on RESULT lines); dr736 not in the queue (its packs are not in this tree). The protocol: each exit line to the shipper, the next published on its ack, the shipper's "PC 1 released" line (after the 0.3.21 window host build) opens the queue. THE FOUNDER'S STANDING RULE (through main, 19:1x UK): no gaps between tasks, the builders run continuously, no lane idle while another has queued work; the Counter lane reports exceptions and clock readings only. THE FOUNDER'S WORD ON CLASS V5 AND THE CRYPTANALYSIS (19:2x UK): push both tonight. Class v5 split across six parallel lanes: (a) the v5 lane, the generator and verifier with the verifier cost against the 10 ms gate (the first v5 pack cut 18:06:39Z on build-1 under igneum-pow b4059975: Devnet 3's genesis as epoch and era seed, day 20,733, the genesis state's 11 leaves under state root 7e37a9fb19b154d32daf5bf30a50d339a75029fbc9eec9ea20e95439dba5a311, generator 5 attempt 0, program id e5a4ac5978462156, Metal fingerprint 82b19cbde8557ea5 at 2^24 from base 0 on the M5 Max at 18:07Z, the three vector warps bit-exact, the cache FNV 7334fa46e5d972eb, 70 unit tests green, the v5 chain draw equal to the amended v4's instruction for instruction; the pack proto-cuda/packs-ca3-v5/v5-dn3-epoch0 with state.igsd1 and leaves.bin); (b) the node lane, the state commitment into the dataset derivation and the stale-dataset test known-failed first, the digest-compat fields, the day streams, the proof witness; (c) a new kits lane, Metal, CUDA, OpenCL/AMD and Intel with fingerprints equal and a kit zip on build-1; (d) the attack-pass lane, F1, F4, F8 at 2^24 and F9 on the v5 stream on both boxes (held for main's own line to it, since it takes tasking from main only); (e) a new fast-time lane, the ladder climb plus the v5 crossing with a stale node, the digest-compat and the restart cases; (f) the shipper and the node lane, the Devnet 3 crossing as class v5 by activation height on the 0.3.23 node with the apps' kits in the same release, every gate kept; the target the v5 crossing on Devnet 3 tonight, the clock a reading when (b)'s fork draws e5a4ac5978462156 for Devnet 3's epoch 0 and (e)'s cases pass. The cryptanalysis: the lanes tripled (three per target on different question classes), CPU and GPU pods rented within the fleet's ceiling through the fleet's warm-pod shape, the sweeps back to back, first results by 23:00Z (00:00 BST) with the box-hours and pod-hours spent and the bound reached stated honestly (the crypto lane's rule set at crypto-engage 921ea607 carries the no-gaps rule). THE EVENING's EXCEPTIONS AND PLACEMENT (19:2x to 19:5x UK): build-2's mirror master was stale (a4bca198, without the pow fix) until the hash lane fast-forwarded it to build-1's 001e32ec at 18:25:42Z; the three adversarial branches cut from the stale tip are ordered to merge build-1's master before any run or report (master's igneum-pow 017e7037 byte for byte on both mirrors). The founder's read: build-1 at 11 percent CPU, build-2 at 56; the word both to near max, the lease pool to about 88 cores a box; the cryptanalysis sweeps, the attack-pass family runs on v5 and the v5 kit builds placed on build-1 explicitly, back to back, both boxes above 80 percent until the queues empty. The cryptanalysis tripled: seven of nine lanes running (the three originals re-scoped to one question class each, plus mixer day-key, mixer statistical distinguisher, cache hot-set, acceptance header-grinding); adv-cache-3 (chain-break) and adv-accept-3 (draw exhaustion) blocked by the session's 20-concurrent-subagent cap (only the founder raises CLAUDE_CODE_MAX_CONCURRENT_SUBAGENTS), re-spawned as slots free; plans by 20:25 and 21:10 BST, first results by 00:00 BST; the sweep queue on build-2 live. Pods: no CPU-only pod type exists, and the fleet lane rents none for the pass until the founder's word reaches it on its own channel; the boxes' idle cores at nice 10 carry the sweeps; adv-accept-2's GPU locality row stays an analytic bound tonight. MAIN's RULINGS (20:0x UK): pods cleared, the fleet lane holding the founder's word with a USD 200 cap for the pass tonight, each request as purpose, lane, hours and pod type, adv-accept-2's GPU locality row first; the 20-concurrent cap stays (the Mac crashed under agent load this morning; the standing rule keeps running agents near ten), the two unspawned lanes take slots as they free and their questions queue as sweeps on the boxes meanwhile. PC 1: released 18:04:37Z, the kit fetch landed 18:16:36Z, the MSVC host built and off; main's word 19:5x UK: publish the class v4 efficiency pass this minute, then the queue in order. THE EVENING's READINGS (19:3x to 19:5x UK). THE SITE: deployed from the box mirror (GitHub dark) by the build-server lane's tools/site-deploy-from-mirror.sh (a git-less export of the site tree at the mirror commit, node site/build.mjs, vercel deploy from the export; reads nothing from GitHub): master 04c4d9bc live at 18:45:40Z with the 37-row bench table; the sortable table (every header sorts, default MH per watt; the current class as the table, 31 rows; the six earlier-class rows collapsed; the note on why the rate fell from the genesis program to class v3 and v4) landed on the mirror's master at ee5214dc at 18:46Z, its deploy ordered. THE PC 1 EFFICIENCY PASS: the first publish (18:27:57Z, elevated) failed exit 251 at 18:31:14Z, the UAC prompt unanswered in two minutes (nothing measured, the card restored); republished as -b at 18:39:23Z through the installed app's Power Helper task (the founder's one approval of 6 October, the same channel as the app's Ember tune; the verbs dev, lgc and rgc only; rgc in the finally; the fallback measured-only rows if the helper is absent). THE FOUNDER'S STANDING RULE (through main, 19:4x UK, recorded): no PC job may raise a UAC prompt or need a click, ever; elevation only through the installed app's Power Helper task; without it the job reports "no elevation path: Power control off on " with the measured-only rows and never prompts; the "no prompt" assertion goes into the job runner's publish check (a job with --elevated and no helper path refused at publish; the hash lane commits it); the Arc driver retry cancelled tonight under the same rule; the founder away until about 20:40Z (21:40 BST), one table to him then through main. CLASS V5 KITS (lane (c), 18:34Z to 18:41Z): 82b19cbde8557ea5 read on Metal (M5 Max, 14.163 MH/s GPU time, the build 30.6 ms GPU with the 11 leaves), Apple OpenCL (15.265 MH/s wall), the Metal one-click serve path (a v5 job mined at 18:37:32Z) and the CUDA worker's CPU emulation (--check PASS, 96 of 96 lanes); the fleet 5090 or 4090 card reading asked of the fleet lane; the kit zip packs-ca3-v5-20261007T183921Z.zip sha256 e6c088bb34fecdc3ff297dbb06438a14ade7d8c55273357726d28f7a1334a25e (919,129 bytes, 56 files: three packs with leaves.bin, Linux and Windows NVRTC and OpenCL workers, both bench scripts, SHA256SUMS) on build-1; branch v5-kits 3c9ee884; the hosts upload the leaves and free them after the build, no igneum-pow change; the 9070 XT bench placed on PC 1 right after the 9070 XT G1; the Intel row deferred tonight (no B580 on a PC, the Arc path needs a click). THE IN-HOUSE PASS: all nine lanes started (adv-cache-3 at 19:41 BST, adv-accept-3 as a slot freed); plans on the mirror from adv-mixer 1d720654, adv-cache 476e4516, adv-accept d2bc4dc8, adv-cache-2 3d9bcece, adv-accept-2 9b86d4e2; first results from adv-cache (2c7bb6b4: the storage-against-recompute curve monotone toward the full store, f = 1/2 at 0.875x of the full-store chip's rate under equal silicon and 1.26x the ops; batching loses to the stride store from 8 MiB; Q1a, Q2 and Q3 bounds clear; 0.2 box-hours) and adv-mixer (e35556af: Q1 algebraic structure BOUND, no composition cheaper than 8x, algebraic degree at least 16 after one application and saturated after two, 9,360 ops per item stand; the 2^24 day census' best day a 1.17x FPGA multiply-datapath day, 1 in 2^24; 0.4 box-hours); adv-accept-2's reading from the code: the header reaches the hash only through the init words and never the program or the dataset, so a grind cannot amortise across a stream, its bound analytic, the GPU confirmation on the fleet's A5000 pod (rented on the fleet lane's own authority under the word it holds). The crypto lane's rulings: the SIGSTOP yield retired (it kept every sweep stopped while suites held the slots), nice 10 on cores 8 to 95; logs and pid files outside the worktree mirror after build-remote.sh's sync deleted adv-cache's first logs; the lanes' doc paths added to the export exclude list. The crypto lane originates no pod rent on an agent relay (a purchase needs the founder's own turn); nothing waits on it. Every lane's numbers are the lane's until the defender checks the logs. Box reading: build-1 at load about 161 on 96 cores at 18:45Z, the near-max the founder asked for; the 8 reserved cores protect the release builds. THE NO-PROMPT RULE IN CODE (the hash lane, ca3-v4-amend 6d84e99f on the mirror): packaging/ota/publish-jobs.sh refuses --elevated at publish (exit 3, the rule and the helper path named); tools/ci/playbook-quit-check.sh rule 3 fails any job script launching with -Verb RunAs or runas /user outside a comment; self-tests (a RunAs launch fails, a Power Helper task start passes, the publisher refuses the 18:27Z line as published, the known-failed case); the pre-push gate carries it. THE CLASS V4 EFFICIENCY PASS, MID-RUN (run-ca3-pc1-v4-eff-5090-20261007-b, PC 1, the 5090 alone, the Power Helper task running with no prompt, every fingerprint matching, 60 s steps, memory 13,801 MHz throughout; rows at 18:51Z):

Core clock v4 MH/s v4 W v4 MH/W v3 MH/s v3 W v3 MH/W
unlocked (sm 2,838 to 2,850) 136.84 475.5 0.288 136.59 330.2 0.414
2,850 lock 136.89 478.9 0.286 136.61 330.3 0.414
2,781 136.87 457.6 0.299 136.62 317.9 0.430
2,700 136.85 443.2 0.309 136.54 312.4 0.437
2,550 136.77 402.9 0.340

Reading so far: the class v4 premium at the unlocked clock is +145 W on this card tonight (against the +80 W of the 6 October measurement at a different cap state), and 73 W of it is recovered at the 2,550 MHz lock for 0.05 percent of rate; the rate is memory-bound and flat as the clock falls, so the founder's thesis holds so far; the steps 2,472 down to 1,400 run to about 19:20Z, the TABLE at the close. THE IN-HOUSE PASS's FIRST FINDING (adv-accept a22d5ba0, 19:51 BST, 1.6 box-hours; the defender's review: confirmed and bounded, no dispute on the numbers): one accepted class v4 sub-version 3 program (seed 100767 in the F8 label space, program id 9d68e6286fc817d4, attempt 2) passes every part of the frozen rule including (c'') (its distinct-index ratio 0.9988 at 2^20, inside the clean spread) and on the live dataset at 2^24 nonces reads a hot set: the top 0.1 percent of items take 2.05x the window model's share (X_f +0.155 percent, X_f/f 1.55; the largest 64-item bucket +294.8 sigma), attributed to one site (instruction 23, source r6, a quarter window; r6 last written by a mad at instruction 4, zero in 0.0126 percent of evaluations, under (c')'s 1 percent) whose hot items are the images of small source values under the era stride at multiples of 2^19; the other sites 0.00 to 0.21 percent against 0.10 expected. The chip price, the lane's and the defender's alike: a 1 MB on-die copy of the hot items serves 0.31 percent of loads instead of 0.15, a 1.002x gain, no chip-model row moves. What is new: the stand-in ratio is a cheap seed selector (the four lowest-ratio seeds of 4,600 accepted programs all beyond 1.2x live, 1.29x to 2.05x; 23 random accepted programs at most 1.043x), and the finding attributes one of AP-F8-1's unattributed tail by value. Routing (main): FINDING (bounded) on sub-version 3, published whole, no change to the frozen object or Devnet 3; MAIN'S ORDER: class v5's acceptance rule carries the fix before tonight's v5 object freezes (a per-site hot-item test at live scale, or a value-level source test, whichever reaches the lineage-fresh constant; known-failed first on seed 100767's shape under the v5 state-derived dataset; the selector's false-positive rate read); if it cannot be in tonight's object with the suite green, the v5 crossing clock moves with the reason. adv-cache FINAL (49ef7747, 0.55 box-hours, 0 pod-hours): every row BOUND (the defender's review: Q1b, Q1c and Q4 BOUND, the Q1b curve equal to its log row for row; Q2 and Q3 readings for adv-cache-2 to confirm); its three sibling definitions implemented as a harness for adv-cache-3, not run. Plans on the mirror from all eight started lanes; adv-accept-3 spawned as the cap gave way. CLASS V5 TONIGHT, THE READINGS (19:0x to 19:2x UTC). The site: aacbcd24 (the sortable table) live at 18:53:41Z; the Hive flight-sheet column landed on the mirror's master at fc32ecf3, its deploy ordered. The kits: every measured platform reads 82b19cbde8557ea5 on v5-dn3-epoch0 (Metal 18:34:47Z, Apple OpenCL 18:34:59Z, CUDA on a one-shot RunPod 4090 at 18:57:45Z, driver 580.159.04, 62.76 MH/s over five 2^24 dispatches, the pod destroyed 18:57:51Z); AMD placed on PC 1 after the 9070 XT G1; Intel deferred (no card without a click). THE ACCEPTANCE FIX (main's order, the cheapest first): (c''') at class-v5 ab6f980b, the per-site distinct-index floor raised from 0.98 to 0.995 on the ratio pass's own 2^20 run, keyed on the state flag (no class v4 verdict moves, no new sample, no 2^24 run; the verdict at attempt 2); the known-failed test first on adv-accept's exemplar (seed 100767: class v4 accepts it, class v5 names site 6 under 0.995 and moves past attempt 2, both genesis draws clear the floor); the box build and test running; the 4,600-seed census (the clean spread, the count under floors 0.98 to 0.999, the attempts histogram v4 against v5, the seeds whose v5 draw moves) on box 2 after it; the per-site hot-item test not needed if the floor's clean rejection rate reads under 1 percent (the two statistics are the same distinct count; adv-accept read the exemplar at 0.9919 closed and 0.9920 live at the acceptance's own sample). TWO EXCEPTIONS: (1) the flip-stale harness re-run (18:58 to 19:02Z) read FAIL on v5_ids_equal_the_cli_v5_id, sinks_agree and block_counts_agree, binary skew not a rule defect (the fork binaries of 17:56Z predate the AP-F4-1 and AP-F1-1 rules of 18:27Z and 18:37Z; the ids differ at epochs 9 and 10, equal at 11); the fork rebuilds once on the (c''') tip and the harness re-runs on the matched pair. (2) class_signal.rs decide() with the v5 object set and both floors at 0 read epochs under the window as class v3 regardless of the v4 floor (e0:v3 e1:v3 e2:v4), which on Devnet 3 would have made a node re-read day one as v3 and refuse the chain; FIXED by the node lane at b1680b57 on class-v5-node-wire (19:14Z): the under-window base takes the floor's class and never a bare v3 (unfull_window_base), the known-failed test first (v4 floor 0 with the v5 object set reads v4 at epochs 0 and 1; the v4 floor at never reads v3; at or past the v5 floor, v5), kaspa-consensus 123 of 123 on build-2 at 19:13:16Z; the branch also carries the snapshot wire's day streams (7737ebd9), the day-state witness (6d827c5d) and the stale-chip unit test (40c03806), all green; nothing reaches Devnet 3 before the v5 object commit on release-0.3.23-node, which waits on the (c''') tip; the 0.3.23 line at a4415ab2 with its gates running, Devnet 3's digest 83eb50cd restored at a099594f. THE IN-HOUSE PASS: adv-accept Q2 (the stand-in gap) BOUND on 54 accepted programs (closed-form and live per-site ratios agree to 0.0004 at 2^20, 0 verdict disagreements; no steering through the gap); the selector widened and honest: 6 of the 8 lowest-ratio seeds beyond 1.2x live, 2 not (103378 at 1.157x, 105756 at 0.9996x), the random control 0 of 4 beyond, so the stand-in ratio is a noisy selector at the 0.996 level; 2.6 box-hours. adv-accept-2 (header grinding for locality): the two real and 8 drawn programs match the windowed random baseline at the mean, minimum and 1e-3 to 1e-5 tails for rows, lines and items; one-bit header flips move 100.00 percent of the 4,096 unit addresses; 2 to 4 of 16 load sites header-predictable in iteration 0, none later; both plants fire; the one GPU confirmation on the fleet's A6000 pod due about 21:45Z, pod spend USD 1.59. The crypto lane's per-box sweep lock (one sweep per box under flock, up to 88 threads on cores 8 to 95, nice 10) after the boxes read loads of 496 and 527 on 96 cores at 18:55Z. THE CLASS V4 EFFICIENCY PASS, THE TABLE (run-ca3-pc1-v4-eff-5090-20261007-b, PC 1, the RTX 5090 alone, driver 617.14, app 0.3.20, every lock through the Power Helper task with no prompt, memory 13,801 MHz throughout, every fingerprint on every step equal to the Mac's, exit 0 at 19:16:27Z after 2,165 s; measured 18:40 to 19:16Z, 60 s steps):

Core lock MHz v4 MH/s v4 W v4 MH/W v3 MH/s v3 W v3 MH/W sm MHz read
unlocked 136.84 475.5 0.288 136.59 330.2 0.414 2,838 / 2,850
2,850 136.89 478.9 0.286 136.61 330.3 0.414 2,833 / 2,842
2,781 136.87 457.6 0.299 136.62 317.9 0.430 2,767
2,700 136.85 443.2 0.309 136.54 312.4 0.437 2,692
2,550 136.77 402.9 0.339 136.43 288.5 0.473 2,542
2,472 136.62 391.2 0.349 136.38 276.0 0.494 2,460
2,400 136.67 382.8 0.357 136.29 269.8 0.505 2,392
2,250 136.43 366.5 0.372 136.07 255.0 0.534 2,242
2,163 136.33 361.3 0.377 136.11 252.4 0.539 2,152
2,100 136.25 359.3 0.379 136.04 251.4 0.541 2,092
1,950 135.99 350.1 0.388 135.78 244.6 0.555 1,942
1,854 135.85 341.4 0.398 135.56 239.6 0.566 1,845
1,800 135.75 337.1 0.403 135.48 237.4 0.571 1,792
1,650 135.37 328.1 0.413 135.10 235.1 0.575 1,642
1,500 135.22 320.5 0.422 134.90 232.1 0.581 1,492
1,400 134.98 316.3 0.427 134.68 228.0 0.591 1,387
unlocked, end 136.75 473.0 136.5x 329.7 2,843 / 2,850

Reading: the class v4 premium is 145.3 W at the unlocked clock (not the 80 W of 6 October, which was read at the app's tuned cap) and 88.3 W at the 1,400 MHz lock; v4's rate is +0.18 percent over v3 unlocked and +0.23 percent at the lock; the rate is memory-bound on the whole grid (136.8 to 135.0 MH/s from 2,850 to 1,400); the best MH per watt sits at the lowest lock on the grid, so the knee is below 1,400 MHz. the founder's thesis holds in part: 57 W of the 145 W premium comes back by the lock alone; 88 W stays as the shadow's ALU work at the floor clock. Throttle reasons: the SW power-cap governor (0x400) from unlocked to 2,163, the lock itself (0x4) from 2,100 down on v4 and 1,650 down on v3; 75 C at the top, 59 C at 1,400. The owed 5090 clock rows (2,781 / 2,472 / 2,163 / 1,854) are in this table. Per tier: a 5090 owner on class v4 who locks the core at 1,400 MHz pays 316 W instead of 476 W for 1.4 percent less rate, MH per watt up 48 percent, the v4 premium down from 145 to 88 W; the lever is NVIDIA's -lgc through the helper; AMD has the helper's ADLX tune line or nothing; the Mac has no lever. MAIN'S ORDERS ON IT (20:2x UK): (1) the second pass now, 1,400 MHz down to the driver's floor in 100 MHz steps on v4 and the v3 control, to find the knee and the premium at it, then the same grid on the 5080; (2) the knob into Ember Tune for 0.3.23 (after the power-cap search, a core-clock search downward from the cap's point until the rate falls more than 1 percent, taking the best MH/W, the fingerprint on every step, stored per card; the Mac stated as no lever) through the UI lane; (3) the bench table's 5090 row gains the locked point and the class v4 cost column reads the locked premium beside the unlocked one (done: the 1,400 MHz row 134.98 MH/s at 316.3 W, 0.427 MH/W, the Hive values 1,400 / 13,801 / 575 as the driver's default limit). DEVNET 3's FIRST LOCK (the fleet lane): 19:02:46Z, checkpoint 235 LOCKED on block 50266abe... (blue score 7,050), identical on dn3-g1 (signed 98.4 percent of active) and dn3-g2 (100.1 percent), at DAA about 7,298 (the 7,200 window filled at 19:01Z); wave 1 of the second nodes GREEN on all five at 19:17:00Z, wave 2 from 19:17Z; the 0.3.22 pin candidate 34a2dbaa passed its last gate at 19:07Z (the join-and-restart read on dn3-c1 with the N15 line) and the Devnet 3 sweep to it runs. The fleet's 19:03Z table: 43 rows, 44 GPUs, USD 257 a day, today about USD 460 of the ceiling at 19:20Z; dn3-twin (a broken CUDA host) and dn3-q02 (never answered) destroyed; p12-vast, w-target and w-poison repurposed to Devnet 3. THE SITE: a0e0c83a deployed 19:17:28Z with the Hive column. THE BOXES: build-1 read 601 / 552 / 471 and build-2 401 / 417 / 400 at 19:17Z, the sum being adversarial binaries started by hand over ssh at 64 to 89 threads each (the crypto lane's one-sweep lock not holding the sum); MAIN'S RULE for every lane under this one: no run starts on a box except through the build-server lane's lease pool <threads> -- cmd (landing within the quarter hour); hand-started runs killed by their kill files and re-queued through the lease; the release builds and the v5 suites outrank the sweeps. THE SHIPPER cuts class v5 as 0.3.24 the minute every v5 gate is green, at any hour; this lane's gate board is the only clock. THE (c''') CENSUS NUMBER (the v5 lane, 21:03 UK; 4,600 f8 seeds, box 2, 48 cores, 1,256 s; log docs/design/class-v5-harness/v5-census-4600-0.log): the 0.995 per-site floor rejects 112 of 4,600 class v4 sub-version 3 accepted programs (2.435 percent); the same 112 move to a later class v5 attempt; the attempts mean 2.174 to 2.248 (+3.4 percent; the tail unchanged, max 24 on both); 0 class v5 accepted programs under the floor. The spread of the v4-accepted programs' minimum site ratio at the 2^20 sample: min 0.9807, p0.1 0.9831, p1 0.9906, p5 0.9962, median 0.9999; under 0.98 none, under 0.99 43 (0.935 percent), under 0.995 112, under 0.998 517, under 0.999 868. Two corrections to the relayed premise: the clean spread is not "0.9960 minimum, p1 0.9990" on the chain's own draw (a smaller sample), and 0.99 would NOT refuse the exemplar (0.9919). So 0.995 is the lowest round floor that refuses seed 100767 with the model's spread under it, at one extra draw attempt on 2.4 percent of epochs (about 0.3 s of acceptance each, no consensus cost, no change to the hash or the kits); the band it rejects is where every measured program so far is a weak hot-set program (adv-accept's live-low20 row: the first read, seed 3664 at 1.31x, beyond the 1.2x gate; its four measured lowest-ratio seeds all beyond). The per-site hot-item test is the same statistic at the 2^20 sample and costs 30 s per candidate at 2^24 against the floor's 0 extra, so it is not a competitor. The defender's call: keep 0.995; the freeze commit carries the number into accept.rs and section 14 and goes the minute the full suite and the gate read green (f17849eb staged). THE PRE-PUBLIC SCRUB: master's text pass (9b8eb23a, 3b4b6c63) names the founder as "the founder" in every tracked text file and the CI check founder-strings refuses the name; this record follows it from here (three lines of the efficiency pass reintroduced the name through a merge and are fixed). THE V5 FAST-TIME LINES ON THE FIRST MATCHED PAIR 959b57c9 (igneumd 519ee6c4..., igneum-pow ab6f980b; harness v5-fasttime 6de9cf74): (1) the ladder climb plus the v5 crossing with the stale node: rung 1 by miner signal from epoch 6 at 19:56:38Z; class v5 by signal from epoch 8 (DAA 480) at rung 1 at 19:58:31Z on 3 of 3 honest nodes, byte 6 at 9,985 bps, before the floor; the prelude reads v4 at epochs 0 and 1 (b1680b57 verified); honest nodes 0 PoW rejections; the stale node 122 of 122 refused by its own node; the SUMMARY FAIL at 20:04:00Z on line 3 alone. (2) Digest-compat SUMMARY PASS 20:08:30Z (one digest c0d6998e with the v5 key absent on the new binary and on the pre-v5 control 2720d8d2; the set key moves it to 8d8f6208 with no peer and the refusal line; 180 s of mixed mining, 79 new and 101 old blocks, 0 rejected). (3) THE RESTART STEP FAILED: n2 stopped at DAA 457 and restarted on its own datadir at DAA 500 (19:59:10Z), the IBD catch-up engaged and did not complete: the relay flow treated the engine's "class v5 needs the execution state" on a relayed epoch-8 block as a rule refusal twelve seconds in, the flow error tore down the peer's flows and the catch-up's body sync with them, the block went into the N6 refused memory, the peer was banned 600 s at 20:00:09Z, and the deferred headers were never validated; n2 on its own fork to the end (600 against 660). FIXED by the node lane at a3b2049d on class-v5-node-wire (20:0xZ): the relay flow holds off a block in the v5 state-wait class at its three validation sites (no strike, no N6 memory, the flow stays up; the next inv or the catch-up's deferred chunk brings it back once the executor has the state), is_v5_state_wait shared with the IBD catch-up, kaspa-p2p-flows 38 of 38 at 20:08:23Z. (4) One program id per epoch equal to the CLI's v5 id: 11 of 11 (v4 at rungs 0 and 1, v5 at rung 1 with the window's stream), the Devnet 3 genesis pack's e5a4ac5978462156 reproduced; the known-failed shape FAIL as it must at 19:04:01Z. THE SECOND MATCHED PAIR 63524e28 landed 20:16:49Z on build-1 (/srv/artefacts/v5-pair-63524e28/, igneumd sha256 4f93697f5b97c30205b7e1c8e521924ba85f849a5d35f1470ff0a1b2a17cbbae; fork v5-object-0323 = 959b57c9 + the relay hold-off a3b2049d + the pool lane's tag rename 7455b8d5 + main's chain id by height, Devnet 3 chain id 4464 from the v5 floor; igneum-pow ab6f980b; suites consensus 126, core 154, pow 19, exec 46, p2p-flows 38, miner 25); the fast-time lane re-runs the crossing with the restart step on it; the v5 object commit waits on that PASS, the freeze commit and dn3-g1's DAA at the cut. THE IN-HOUSE PASS: adv-accept's tally at 2^24: of the 16 lowest stand-in-ratio seeds, 9 beyond the 1.2x gate and 3 hot sets (100767 at 2.05x; 4346 at X/f 1.78, 2.24x; 5245 at 1.29, 1.86x); of 17 random accepted programs 1 beyond and 0 hot sets; the selector's false-positive rate 7 of 16 on the gate, 13 of 16 on the hot-set test; each hot set about 1 MB of items at 0.3 percent of reads, 1.002x; whether the 0.995 floor refuses 4346 and 5245 is a measurement in hand (their minimum-site ratios at 2^20), not a given. adv-accept-2 at its natural end (92168536): header grinding BOUND by measurement and by tail (1e8 hashes per real program on the windowed random baseline down to the 3e-7 tail, net gain 3e-7x); the rotate-identity repeat class present in 21.0 percent of 300 drawn programs at under 0.1 percent of loads on the worst, absent from the two real programs, a rule question for the next class. Lanes at a natural end: adv-cache, adv-accept-2. THE SITE: b8f501e9 deployed 20:17:42Z with the compact table; its 1600 px capture read five columns clipped at the article column's edge (about 900 px against a 1,400 px table), so the table now fits the column (nine columns, the generator in the detail row, the text columns wrapping and the numbers not, no forced width). THE FOUNDER'S QUESTION ON THE CLASS V4 PREMIUM ("we need a solution, deep research, other methods, something must be doable even if it is revolutionary"; a research lane, counter-asic-4, on the literature and the alternatives by 23:30Z). THE ONE COMPUTATION FROM THIS LANE (chip-model-v3 section 5.10, on the mirror's master at aa829826): class v5 ON and the shadow at ZERO leaves the strongest chip, the f = 1 stored-dataset chip, at 5.1x (GDDR7, the 5090's own 16 devices without the GPU: 166 MH/s at 78 W with a farm-shared node) to 9.1x (HBM3 eight stacks: 666 MH/s at 175 W) per joule over the 5090's 0.417 MH/W, the class v3 figures of 5.6 less a rounding, because the node is a farm cost and not a chip cost (class-v5 2a.2: one node serves a farm, the leaves ship at 16.5 KB/s to 10,000 members, the rebuild is the same 32 ms per window every GPU pays); only a chip forced to carry its own node (85 W, approximate) falls near 2x, and only the small ones (one HBM3 stack 1.8x, the GDDR7 board 2.5x; the eight-stack package 6.2x). So the shadow stays the only lever in the model that reaches the memory-system chip, and the premium is its price; what class v5 buys is the recompute and stale chips gone as categories and every miner holding and following the chain. THE RESEARCH LANE's READING of the three shapes (21:4x UK; its identity edge = (E_card + F) / (E_mem + k F), F the GPU's premium per hash, k the chip core's energy per op over the GPU's): at the 1,400 MHz lock (v3 1.69 uJ per hash, v4 2.34, the premium 0.65 uJ = 6.5 pJ per counted op) the premium-free edge is 3.6x on GDDR7 and 5.3x on one HBM3 stack, 2.1x at F = 0.65 and k = 1, the asymptote 1/k; the premium needed for 2x at k = 1 is 0.76 uJ (103 W) at the lock and 1.41 uJ (175 W) at the stock point; at k at or under 0.5 no premium reaches 2x; a premium of zero is impossible by any hash-side lever (a joule the chip must spend is a joule the GPU spends first). Shape 1 (the shadow at the floor clock): correct and measured by the 1,400 row; it halves the premium and leaves k as the whole question (the edge's derivative in F at F = 0 is minus 5.7x per uJ at k = 1 and minus 0.2x per uJ at k = 0.3; the family mix with the highest k, shuffles and multiplies, is the right content; the tensor block has k near 1 but 0.056 pJ per MAC, so it forces no joules without 26x the verifier). Shape 2 (per-read work a chip cannot amortise): no construction found (the chip's lane count is set by its own latency, lane state is SRAM at pJ per access, extra reads scale both rates; row, bank, refresh and burst shaping have no asymmetry); one candidate for a measurement, not a claim: a hot table kept L2-resident through cache-policy hints (dataset loads evict-first, hot loads evict-last), since a 64 MiB SRAM read on a chip is not cheaper than a GPU L2 hit (the 3.0 layer 5 measurement used no hints and lost 13 to 16 percent). Shape 3 (the refresh as the cost): dead by arithmetic (a 1 GiB rebuild about 0.1 J on a chip against 280 kJ of hashing an hour). What lowers the premium-free floor is the card's own E_card: the 5090's idle 74 to 91 W plus its memory system's 55 W bound the floor near 2.0x on GDDR7 at any operating point; the two measurements that read how much of the 100 W between is reachable are the knee below 1,400 MHz (the floor pass, on PC 1's queue) and an SM-sparse kernel (the hash on a fraction of the SMs with 4 to 8 chains per thread, the rest clock-gated), both ordered to the hash lane with the L2 cache-policy hot table as PC 1 queue tail items (worker launch shapes, --bench only, no consensus change). THE FIVE RATIOS (adv-accept, 21:35 BST, at the acceptance's 2^20 sample, closed form and live to 1e-4): 4346 (bbb38e847011c354) minimum site 2 at 0.9840 REFUSED by (c''') at 0.995; 5245 (beaad44840bb9e4e) site 8 at 0.9831 REFUSED; 106924 at 0.9821 and 107022 at 0.9877 REFUSED; Devnet 3's epoch-0 class v4 program (fce15bf61030be57) site 0 at 0.9992 (live 0.9993) MISSED; era-fixed-20 (11f9f955b21d56c9) site 11 at 0.9997 MISSED; era-drawn-2 (7ceb797d31eedb3e) site 13 at 0.9992 MISSED. THE DEFENDER'S RULING: the (c''') floor at 0.995 closes the HOT-SET HALF of the class (every program with X_f at or above f that any lane measured, 100767 included) and NOT the class; the residual is the shadow-block-written value-level concentration below a ratio floor's resolution (1.26x to 1.45x of the top 0.1 percent share, 0.03 to 0.1 percent of a hash's reads each, minimum sites 0.9992 to 0.9997, which no floor reaches without sitting inside the clean seeds' own spread), chip gain under 1.001x, its lever a value-level source test at live scale or a per-site hot-item test, routed to the next class as a named item; section 14 of the v5 design says so with the five numbers verbatim; the freeze proceeds on the suite's green, both the floor's number and its reach measured. adv-mixer-2 (49656c2e) confirms AP-F4-1's class from outsider inputs (model A an FPGA LUT-area gain for a per-day build, 1.0 on every GPU, verifier and chip with a general multiplier; P(A at or above 1.1x) = 2^-10.8 per day on the exact median 226; model C under 2^-20 at 1.1x), the two censuses' medians (226 against 231) to be reconciled side by side in the record; its redraw rule to the v5 lane as a second independent statement. The kits lane's box-side body moved to tools/class-v5/kits-on-box.sh run by path under the inline-rm rule (v5-kits 4f9d96d2); the kit zip stands. MAIN'S RULINGS (21:4x UK). (1) The class v5 freeze does not wait on the three milder concentrations the 0.995 floor misses (Devnet 3's first program among them): their chip gain is bounded under 1.002x by their size, so the freeze proceeds with the floor as it is, the record names them as the residual, and the fix question (a value-level source test at live scale) is a 0.3.25 item. (2) The weak-day census reconciled at median 226 (F4's NAF weight had counted the carry digit at position 32, which a 32-bit multiplier never pays; 0.333 digits per word, 5.3 adders per day, the whole of 231 against 226 and of 12 against 15 days a century, the same worst day in both; F4's record section 9 carries both medians side by side, mirrored in adv-mixer-2's report): 5.69e-4 of days (2^-10.8), 15 days a century over 1.1x on FPGA LUT area, worst 2050-04-28 at 1.113x, the DSP-bound readings at 0 for k at least 2, F4's PASS against class v4 unchanged; every public text saying "12 days a century" becomes "15 days a century" (done in this landing on the litepaper table, /claims through it, evidence row 17 and the public text file, the sentence now "at most 12 percent more multiplier area on an FPGA's per-day build on 15 days a century, nothing on the other days and nothing for any chip"); the site audit lane told. (3) THE HALVING, ruled to the fleet (21:4x UK), neither (a) nor (b) as written: on every standing box the OLD shared-devnet miner stops and the Devnet 3 miner keeps the card at full rate (one miner per card, the exception over); hub-1, pool-1 and the live seed stay on the old chain as its voters and miners until every poller has moved; the old-chain nodes on the boxes stay up as voters without mining; no 3070 fallback; the fleet reports per-box restore lines. THE IN-HOUSE PASS, MORE CLOSES: adv-cache-3 COMPLETE (bc2d01d5, 0.23 slot-hours; every row BOUND or PASS, every plant fired; the exhaustive w = 2 image census at all 64 depths equal to the random-function recursion to 2 x 10^-5; the flip-table ladder at 2^18 lines no single-bit bias from two double rounds up). adv-accept-3 (aa359962): a correctness FINDING for the rule's owners, no chain consequence: the deterministic last-resort program (after 256 failed attempts) FAILS the real rule in 223 of 2,500 seeds (209 by part (a), a cyclic stale load) yet is handed to the chain unchecked, unreachable at 4.6e-44 per epoch; ruled to class v5's generator as the commit after the freeze (the last resort passing the rule by construction, known-failed first on one of the 223 seeds; sub-version 3's stated as unreachable and unverified, class v5's as verified); also the 256-unit stand-in ratio is noise as a selector (the three lowest of 4,975 clean live at 1.0002x worst), the selector working only at the 2^20-unit read. Lanes complete or at a natural end: adv-cache, adv-accept-2, adv-cache-3; adv-mixer on its last solve. The kits lane's box-side body moved to tools/class-v5/kits-on-box.sh by path (v5-kits 4f9d96d2) under the inline-rm rule. THE SECOND 5090 PASS, THE KNEE (run-ca3-pc1-v4-eff-5090-floor-20261007, exit 0 at 20:41:14Z; the 5090 alone, 60 s steps, memory 13,801 MHz, every fingerprint matched):

Core lock MHz v4 MH/s v4 W v4 MH/W v3 MH/s v3 W v3 MH/W sm read
unlocked 136.84 473.7 0.289 136.50 329.9 0.414 2,842 / 2,850
1,400 135.02 320.0 0.422 134.85 229.0 0.589 1,387
1,300 134.76 312.5 0.431 134.62 223.3 0.603 1,290
1,200 133.80 305.1 0.439 129.54 215.7 0.601 1,192
1,100 122.43 287.3 0.426 118.70 209.4 0.567 1,087

The knee by main's rule (more than 1 percent lost against unlocked): 1,300 MHz on both classes (the rate within 1.5 percent of unlocked down to it; v3 falls 5.1 percent at 1,200, v4 10.5 percent at 1,100); the best MH per watt one step past it: v4 at 1,200 MHz (133.80 MH/s, 305.1 W, 0.439 MH/W, 168.6 W recovered for 2.2 percent of rate), v3 at 1,300 (134.62, 223.3 W, 0.603, 106.6 W for 1.4 percent). The v4 premium 143.8 W unlocked, 81.8 W at the best points; the v4 rate 0.25 percent over v3 unlocked and 0.61 percent under at the best points; the residual at the floor is the shadow's ALU work, not the clock. Per tier: a 5090 owner on class v4 locked at 1,200 to 1,300 MHz draws 305 to 313 W instead of 474 for 1.5 to 2.2 percent less rate, MH per watt up 49 to 52 percent; the Ember knob (0.3.24, the hash lane on the engine side, the UI lane's drawing) carries these as its reference rows. A FAULT FOUND AND FIXED: the steps 1,000 down to 300 and the closing reset got no answer from the Power Helper and the card sat at the 1,100 lock for about five minutes after the job (118 to 122 MH/s live); the installed app's own Ember tune on the 5080 wrote the same cmd.txt with higher sequence numbers while the script wrote lower ones, and the helper skips any sequence at or under the last run; the restore job run-ca3-pc1-clocks-restore-20261007 (exit 0 at 20:45:58Z) put the 5090 back at 2,865 MHz; the fix 45f9497f on the mirror (the sequence base from helper.log and cmd.txt, re-based after a timeout, an unanswered lock stops the grid, the task restarted before every reset); the rule for the knob: it takes its sequences from the engine's counter and no script shares the file with a running tune. The driver's floor below 1,100 is unmeasured. THE PC 1 QUEUE after the shipper's 0.3.23 host job (main, 21:5x UK): the 5080 full grid with the fix; the research lane's SM-sparse kernel job (the hash on a fraction of the SMs, several chains per thread, the rest clock-gated; the research lane hands the kernel to the hash lane); the third 5090 pass from 1,100 down to the driver's floor at the tail; then the 9070 XT G1 and ladder, the v5 AMD bench, item 6 on AMD, the 5080 and 9070 XT tunes, the L2 cache-policy hot table; each exit line to the shipper and the coordinator; the honest site sentence (the premium at the knee and the floor it buys, labelled measured, the Ember knob named as how a user gets there) once the 5080 reads. THE DERIVATION FINDING FIXED (the hash lane, 15008aca and 0f45c8be on the mirror): one byte recipe (generator::IdRecipe) builds the id and the printed text; program.json states the generator 4 suffix and the rung form; spec 1.4.6 corrected (class v5 = generator 5, no suffix); tests/derivation.rs re-derives all 18 pinned packs from their own text (the plain text gives 8aa9f185d63f269e for the devnet v4 pack, the known-failed case); 38 packs' program.json re-exported with ids, kernels and fingerprints byte-identical; the full igneum-pow suite green on box 2. CLASS V5 FROZEN: class-v5 1c420786 on both box mirrors at 21:53 UK (the (c''') floor with its number; section 14 with seven of seven live hot sets refused at 0.9821 to 0.9919, seed 170 at 0.9880 the seventh, and the three mild residuals at 0.9992 to 0.9997 named at about 1.0004x; the pinned pack unchanged; the flip-stale harness PASS on the matched binaries at 21:03 UK; the AP-F4-1 first form and the AP-F1-1 shadow rule, the latter's measured trigger 11 permille maximum over 6,000 first draws against the 30 bound, 0 redraws; the igneum-pow suite green on box 2: 73 unit, packs 20, derive 7, mixer 4, recheck 2, scratch 7; the gate GREEN at 58 checks). The kits lane: the 0.3.24 kit is packs-ca3-v5-20261007T183921Z.zip sha256 e6c088bb34fecdc3ff297dbb06438a14ade7d8c55273357726d28f7a1334a25e, byte-identical to the frozen 1c420786 (state.igsd1 included), fingerprint 82b19cbde8557ea5 on Metal, Apple OpenCL and a CUDA 4090; AMD on PC 1's queue, Intel deferred; the shipper has the line. The attack-pass lane runs F8 at 2^24, F9 at 10^5 and F1 on 1c420786 under class v5. The v5 lane's next commit on the freeze: AP-F4-1 in the agreed form (cost at most 205 against the median 226, w32 without the position-32 digit, k >= 1 and all-ROT-equal rejected, the known-failed day 29,337 = 2050-04-28) and the verified last resort (part (a) repaired by re-sourcing stale loads, then the whole rule over a 256-candidate scan, known-failed first on adv-accept-3's adv3/steer/2); both move the stream only on days and seeds the chain never reaches. THE FOURTH EXCEPTION ON THE RESTART STEP (the fast-time lane's held-miner run on the third pair 63524e28, 20:4xZ): the IBD catch-up's body sync anchored on the node's own sink and moved only on a whole chunk's successful join, so with the honest headers arriving as one chunk failing on its v5 tail it fetched nothing and the executor never reached the seed block; the relay hold-off and the mining hold from the earlier fixes read green on that run. FIXED by the node lane at f0c56f50 (the refused chunk split by consensus's own record, the anchor moved to the highest validated header, the honest v4 prefix through the seed block, only the unvalidated headers deferred; kaspa-p2p-flows 38). PAIR 4 = v5-object-0323 c8f9b383, re-archived from the frozen 1c420786 (generator.rs and accept.rs moved since ab6f980b, memhard.rs not), building on build-1 at gate priority since 20:54:32Z with the line's gates beside it; the restart step's PASS must come from pair 4; the object commit lands the minute it does, with dn3-g1's DAA at the cut plus 7,200 rounded up to the 3,600 boundary and its UTC clock named; the testnet lane told to pair its re-cut with 1c420786. The crossing clock is not yet a reading: about 22:15Z (23:15 BST) at the earliest if every line reads green on its first pass. The site audit lane: no other "12 days" form served; its row-17 edit keeps main's outside-check clause and adds the 5090 efficiency numbers. THE CHIP TEXTS, THE X9 WORDING RETIRED (main's order from the counter-asic-4 research file d7721ebe, 22:0x UK): the withdrawn Antminer X9's claimed ratio ("a third of a CPU's energy per RandomX hash") is against a CPU core (about 100 pJ per instruction, Horowitz and Dally, claimed), not a GPU lane (6.5 to 10.4 pJ measured), so a chip three times better than a CPU is worse than a GPU lane per op and the X9 is not a pessimistic chip core against us. The served texts (the home line, the litepaper's lead, chip table, ladder sentence and chip bullet, /claims through it, the miner line, evidence row 17) now give the floor and the premium as measured numbers at the 5090's knee: the chip at 2.1x per joule with a core as good as a GPU lane (k = 1) and 3.4x with one three times better (k about 0.33), no core below about 1.8 pJ per op in the model's range, the shadow's premium 81.8 W at the best points (class v4 at the 1,200 MHz lock 133.80 MH/s at 305.1 W against class v3 at 1,300 MHz 134.62 at 223.3 W, 7 October 2026), Ember Tune's core-clock knob named as how a user gets there; the ledger text check's pins X35 and X36 moved with the wording; no "3.9x" remains on any served page. One number stated against main's wording: main's line read "2.9x with one three times better", which in the research file is the figure for the RE-WEIGHTED op mix (row 3, held by the coordinator until the SM-sparse read); today's mix at a core three times better reads 3.4x in the same file, so the served text carries 3.4x and the 2.9x waits for the re-weight to ship. THE RESEARCH FILE's TWO ORDERS: (1) the texts as above; (2) one zero-code measurement at the PC 1 tail after the third 5090 pass: the 5 October hot-table packs (packs-ca2-hot, 32 and 64 MiB) with the worker's --variant ldcs (dataset loads streaming, evict-first; the hot loads plain and L2-resident) against base on the 5090, the rate ratio g and the watts (the 5 October rows without the hint g 0.84 to 0.87); the one class where a chip's cost per op (a 64 MiB SRAM read, 0.2 to 0.5 nJ approximate) may exceed the GPU's (an L2 hit, 0.1 to 0.3 nJ); Metal has no such hint. The shadow stays at rung 0; the op-mix re-weight waits for the SM-sparse read (the research lane's worker variants sp170/85/43/21/11-w32, one block of 32 warps per SM, run through the hash lane's efficiency script in its ca4 mode at 4f3a064e; the no-prompt and sequence rules hold by the same code). THE 0.3.24 PAIRING RULED (the shipper, 22:1x UK): the v5 object commit pairs with the frozen class-v5 1c420786 as it stands (the gates and the attack-pass lines run on it); the post-freeze fix 8ca66afa is 0.3.25's pairing. 0.3.25's FIRST ROW: class-v5 8ca66afa (both mirrors, 22:10 UK, on 1c420786): (1) AP-F4-1 in the agreed form (decc7c17): the day's draw rejected when cost A = 64 + sum(w32(MUL_i) - 1) is at most 205 against the median 226, w32 over bit positions 0 to 31 (the position-32 carry digit dropped), any MUL with w32 at most 3 rejected (k >= 1), the eight ROT all equal rejected, a rejected block redrawn whole from the continuing stream; known-failed first on chain day 29,337 (2050-04-28): the sub-version 3 block of that day read cost 203, rejected at 205 and redrawn under class v5. (2) Class v5's verified last resort: the rewrite, then repair_stale_loads (a stale load re-sourced to the lowest register written since its last load, to a fixpoint), then the whole rule over a 256-candidate scan from the cap; the unchecked fallback past the scan under 1e-300; known-failed first on adv-accept-3's adv3/steer/2 (the sub-version 3 rewrite fails part (a) at instruction 47 reading r3; the repair restores (a) moving only load sources; class v5's last resort passes at attempt 256, id 9b29c9481f6941d4; steer 11, 33, 56, 58 and 77 pass too); sub-version 3's path untouched. The stream moves only on days and seeds the chain never reaches: the pinned v5 packs byte-identical, the fingerprint 82b19cbde8557ea5 and the epoch-0 id e5a4ac5978462156 unchanged; the igneum-pow suite green on box 2 (74 unit, packs 20, derive 7, mixer 4, recheck 2, scratch 7), the gate GREEN at 58 checks. The harness's class-walk case (v4 floor 0, v3 never) read FAIL on the unfixed fork 546fe4b5 (the known-failed shape, 22:08 UK) and runs on pair 4. THE IN-HOUSE PASS, THE EIGHTH HOT SET (adv-accept, 22:06 BST, the wider sweep over 88,051 accepted programs): seed 122960 (id 4be7393ab6c84802, the lowest 256-unit ratio at 0.9885) reads live at 2^24 X_f +0.111 percent, X/f 1.11, 1.54x the window model, with the heaviest single item measured tonight (0x81ad88 at 475,616 reads, 0.022 percent of all reads, 16x 100767's hottest) from an all-ones source at instruction 4 (writer shfl at 3); site 12's saturated-source share 0.353 percent, a third of (c')'s limit; the other four lowest 256-unit proxies clean live, so the 256-unit proxy is noise at its own extreme and the 2^20 ratio is the selector; the tally 8 hot sets in 30 tail seeds against 0 in 20 random; the price unchanged (0.34 percent of reads on 1 MB, 1.002x); its minimum-site ratio at 2^20 against the 0.995 floor OWED (ordered first), deciding whether the freeze record reads eight of eight refused or names the first hot set the floor misses. THE 5080 AT STOCK (run-ca3-pc1-v4-eff-5080-20261007-b, exit 0 at 21:03:02Z, the card alone, 60 s, both fingerprints matched): class v4 71.43 MH/s at 255.1 W (0.280 MH/W, sm 2,958, mem 14,801 MHz); class v3 71.30 at 170.7 W (0.418); the v4 premium 84.4 W (49 percent over v3's draw), the rate 0.18 percent over v3; against the fleet's rented 5080 (71.16 MH/s at 143.4 W on class v4, driver 580) the rate agrees to 0.4 percent and the watts do not (255 against 143), a question to the fleet lane (its sampler, a cap on the rented card, the memory clock) before either row enters the public table; the lock grid did not run in -b (a PowerShell function defined below its first call left the script without the helper path; nothing set, nothing to restore), republished as -c at 21:07:10Z with the full grid (unlocked to 300 MHz, about 58 minutes). The site audit lane's row 17 and litepaper paragraph carry the 1,400 MHz rows labelled measured, with the best-points clause asked beside the 88 W at 1,400. THE 0.3.24 OBJECT COMMIT AND PIN: v5-object-0323 774f16c9 (21:26:35Z, both mirrors; the fork 432ea3d6 + f0c56f50 + 9ad1d9c6 + 294e3670 + the pool lane's 95ae3e50), paired with the frozen igneum-pow 1c420786: program_class_v5_activation_daa 28,800 (the Devnet 3 seed node at virtual DAA 16,208 at 21:22:24Z; the publish minute 22:30Z = DAA 20,264; plus 7,200 = 27,464; the next 3,600 boundary 28,800, epoch 8), byte 6 counted exactly, the window 86,400; the crossing on Devnet 3 by height about 00:52Z on 8 October (01:52 BST) at 1.0 DAA/s; the constant holds while the publish DAA stays at or under 21,600 (22:52:16Z), past which the node lane re-reads dn3-g1 and re-cuts to 32,400; chain id 4463 below the floor and 4464 from it; the three heights stay, the pool split never. Its gates: core 155 of 155, miner 28 of 28, pow 19 of 19, p2p-flows 38 of 38, exec 46 of 46, consensus 126 of 126 on the gate-priority rerun at 21:44:24Z (the earlier one red at 205 ms on the latency bound under a box load of 127, the known load class); the canary set on build-1 (21:29:38Z to 21:31:18Z): the digest moves to 4a284b1d on igneum-devnet-3 as the v5 arm requires, "this node stamps object version 6 into its headers (block version 1538)", the override file refused, two empty nodes handshake on 4a284b1d, the shared-devnet node refused on network mismatch, a 0.3.23 node refused on the digest both ways; every Devnet 3 node restarts inside one minute at the fleet's named clock on pre-placed binaries. release-0.3.24-node OPEN at 774f16c9 on both mirrors (21:45:19Z, the shipper's word), artefact /srv/artefacts/0324-774f16c9/node-lane (igneumd ed36f246...); the testnet staging 47b9b229 on the pin all green (consensus 134, core 175, exec 47, miner 28, p2p-flows 38, pow 19, digest b2e856ed). THE FAST-TIME GATE CLOSED: SUMMARY PASS (cross-c8f9b383-2) at 21:36:35Z on the matched pair c8f9b383 (igneumd f1b5b32c..., igneum-pow 1c420786), every check green, none skipped: class v4 sub-version 3 from genesis at rung 0; rung 1 by signal from epoch 6 at 21:29:39Z; class v5 by signal at byte 6 counted exactly from epoch 8 (DAA 480) at rung 1 at 21:31:33Z on 4 of 4 nodes, 9,985 bps, before the floor; the second rung at epoch 12 the rule's earliest allowed; 11 of 11 program ids equal to the CPU verifier's; 0 PoW rejections on the honest nodes; the stale node 69 of 69 refused; the restart step: n2 stopped at DAA 455, restarted on its own datadir at DAA 500 at 21:31:56Z, no lock fault, no IBD refusal, "class v5 catch-up done: 19 deferred headers validated after 6 s", nothing of its own accepted during the catch-up and 75 after, at n0's sink 12.1 s after its start; four sinks equal at 660; the digest-compat PASS from 20:08:30Z stands; records on v5-fasttime 4419e8d3. The three earlier pairs (959b57c9, 63524e28, 432ea3d6) each failed the restart step on a node defect fixed in the next (the IBD refusal, the catch-up's anchor at the node's own sink, the node mining while its catch-up waited). THE FLOOR READS EIGHT OF EIGHT (adv-accept, 22:41 BST): seed 122960 (the deepest live hot set) reads minimum site 12 at 0.9824 at the acceptance's 2^20 sample (live 0.9822), REFUSED by (c''') at 0.995 (its site 12 puts 1.31 percent of its reads on word indices read 8 or more times, the largest repeated-index share measured; 100767's site 6: 0.17); every live hot set by X_f at or above f found in the tail of 88,051 accepted programs is refused (minimum sites 0.9821 to 0.9919) against 0 hot sets in 20 random programs; the floor misses the three mild concentrations at 0.9992 to 0.9997 (Devnet 3's first program among them), about 1.0004x; the v5 design's section 14 and the ledger's AP-F8-1 carry the line. THE 0.3.24 CUT waits on the attack-pass verdicts on 1c420786 alone (F8's two halves on build-2 since 21:17:41Z, about 22:20 to 22:35Z; F9 at 10^5 and F1 on build-1); the lease pool now pre-empts adv holders at any size for a v5 or release waiter after 120 s (lease ce30e357). PC 1 EXCEPTION: the Power Helper task dies within seconds of each start since 21:08:34Z (six starts, zero commands, the task Running while no helper process exists; the last good command the 20:45:52Z rgc, its idle exit clean at 21:05:52Z); the suspect the shipper's 0.3.23 host job at 20:51Z replacing the install folder's exe under the registered task, the second a panic in the helper's start path; a read-only diagnostic plus a 20 s unelevated probe placed; the locked grids (the 5080 full grid, the third 5090 pass), the SM-sparse job and the tunes wait on the helper; the lock-free jobs run (the 9070 XT G1 and ladder from 21:27:41Z, then the family run and the v5 AMD bench); nothing raises a prompt to get round it. THE 5080 AT STOCK (two runs agreeing, -b and -c): class v4 71.42 MH/s at 254.5 W (0.281 MH/W, sm 2,960, mem 14,801), class v3 71.30 at 170.8 W (0.418), the premium 84 W; against the fleet's rented 5080 (71.16 MH/s at 145.4 W busy mean, cap 350 W not binding, 1 Hz power.draw instantaneous on Linux driver 580, bench batches with host gaps) the rate agrees to 0.4 percent and the watts do not (110 W apart, the sampler field on Blackwell under two drivers or the load shape); the public table carries the method per row and takes neither as the card's figure until both power fields are sampled on both sides (the fleet's re-measure, PC 1's next NVIDIA pass). THE CA4 SECOND PASS (bca23f96, sections 15 to 19): the tensor-tile k column (2.1x at k = 1, 1.6x at k = 1.5, the k 0.3 column removed for a tensor shadow; a design candidate needing a SIMD byte-dot verifier) and the capex column (the f = 1 GDDR7 chip USD 2.8 per MH/s, at most 4.3 with the hot table, the shadow core and an interposer; capex-dominated 7x; the break-even cap moving only through the project cost) carried into chip-model-v3 as section 5.11. THE PUBLIC TEXTS (main's two orders, 22:3x UK): the served sentence "the one outside check is staged and waits on its escrow and the publish word" read as an escrowed prize to a reader and is replaced everywhere it is served (evidence row 17, the litepaper and /claims through it, the public text file) by "no outside review has run yet", the in-house pass sentence kept; the forbidden-strings gate gains the phrase class ("outside check", "waits on its escrow", "staged and waits", "the publish word"; the bare words stay allowed, since the proving pool's escrow and a staged build are ordinary). THE /miners DESIGN PASS is on the mirror's ca3-coord at e88edae4 with the full gate GREEN (the overlap check clean at 390 to 1600 px after two fixes: the phone grid gives every cell its own area; the desktop row is six columns with the class v4 cost and the date as the muted second line under the card name, the card layout below 1,100 px, the wrapper scrolling as a safety); the 1440 and 390 dark captures go to main for the word on the look; nothing deploys from the branch before it. The in-house pass: four lanes complete (adv-cache, adv-accept-2, adv-cache-3, adv-mixer; adv-mixer's Q1 BOUND on the commutation probe at 0 in 1,454,080,000 over 1,024 days, its SAT row a solver-reach bound at the one-hour cap); adv-mixer-2 one row from complete; adv-accept, adv-accept-3, adv-cache-2 and adv-mixer-3 sweeping to 00:00 BST. F8 ON CLASS V5: PASS (the attack-pass lane, 22:03Z; the frozen igneum-pow class-v5 1c420786, binary sha256 0f5c98dc41a1b3aa...; the pairing bit for bit on 66 validation lines, the library drawing Devnet 3's epoch-0 program as e5a4ac5978462156; 64 seeds p2 to p65 at 2^24 nonces each, chain path, the v5 dataset from v5-dn3-epoch0's state.igsd1 on day 20,733, window-model control, build-2 under lease pool class v5 as two halves of 32, ended 21:58:43Z and 22:03:21Z): 61 of 64 under 1.2x of the window model (0.9919x to 1.144x, p75 1.0024x); 3 over, all inside the named four-seed residue and none new: p10 1.5047x (hottest item 0x4018f5 at 346 reads of 2^31, no predicted source), p8 1.3787x (419 reads), p4 1.2166x (363 reads); p34 reads 0.9997x under the (c''') floor; every strong seed of sub-versions 1 and 2 at 0.9997x to 1.0001x (p23 1.0000, p19 0.9997, p15 0.9998, p18 1.0001, p56 1.0000); seed for seed the ratios equal sub-version 3's within 0.001 except where the floor moved a draw: the state leaves change the words, not the read addresses. F9 (10^5 exhaustion) and F1 (10^5 redundancy) on 1c420786 and F4's 2^24 on 8ca66afa hold or wait in build-1's pool as strengthening lines. THE 0.3.24 NODE PIN MOVED on the shipper's word to 47b9b229 (the object 774f16c9 plus the testnet re-cut 34892a36) after the Devnet 3 canary set read clean on its own binary (21:59:04Z to 22:00:43Z: digest 4a284b1d, byte 6, the override refused, shutdown 725 ms, the handshake, the shared-devnet dialler and a 2720d8d2 node refused); release-0.3.24-node at 47b9b229 on both mirrors (22:01:05Z), igneumd 6bc18ac2..., pairing 1c420786; the build-server lane builds the pairs and the hive from it; the Devnet 3 digest 4a284b1d, the testnet b2e856ed; the floor 28,800 and its slip rule, the dn3-g1 re-read armed for 22:30Z. THE AMD HALF OF G1 PAID (run-ca3-pc1-v4-sub3-amd-g1-20261007, exit 0 at 21:46:14Z, the RX 9070 XT alone): 14 of 14 fingerprints equal to the Mac's Metal and Apple OpenCL and to the 5090's (the control, the seven sub-version 3 packs, the five ladder packs), self-test PASS on all; the ladder rows flat within 2.3 percent from 930 to 330,700 ops per hash (18.8 to 19.2 MH/s; the installed worker's control cross-check 18.96), the card latency-bound on the whole ladder; the watts row owed (the ADLX sampler read 0 samples in the per-pack windows). THE HELPER FAULT READ: not the shipper's; the task's exe is the install folder's 0.3.20 (mtime 12:24:42Z, sha256 0443ae17..., untouched by the host jobs); the helper's code path runs (an unelevated probe answered a dev line in 4 s); the scheduler refuses the ELEVATED instance from a non-interactive start (Last Result 0x800710E0, the task's logon mode interactive only); at 21:41:32Z the 0.3.20 engine's own tune took its legacy "task not registered" branch (the old sweep.rs helper.ps1 written, cmd.txt truncated), the prompt path, so whether a prompt stood on the desk is for the founder's screen in the morning; the class (the engine's registered() check and its fallback, the scheduler's logon mode) is the update-return lane's for 0.3.24; the locked PC 1 jobs stay parked. THE CA4 PROTOTYPES (the research lane, counter-asic-4 6404f62b): two experimental classes behind the pack, no consensus change: +shlx (the shadow's 256 instructions and 27 passes split into 16 sub-blocks of 16, each run after its load) and +mm (R int8 mma u8 tiles per iteration after the shadow; CUDA native PTX, the shuffle reference on Metal and OpenCL; the verifier scalar plus AVX2, SIMD pinned equal to scalar on 64 seeds); the suite green (64 + 7 + 4 + 19 + 2 + 7), the pinned packs byte-identical; packs exported with every OVERALL PASS (mx8_sh256x27 control, mx8_shl256x27, mm128, mm512, mm1430 at 11,440 tiles per hash); their card rows on PC 1 behind the helper; by construction neither lowers the premium (the per-load placement moves the chip's capex, the tile block its k floor). THE LEDGER CLOSE landed the chip rows on the mirror's master at b94a77ad (22:56 BST): X35 and X36 restated, AP-F8-1 with the eight-of-eight sentence, X37 new (the class v4 premium: measured, levers in flight). THE RECORD LANDED (23:24 BST): the regroup 2336a3c5, the outside-check rewrite and chip model 5.11 (6c19c790) and the status 015cc839 picked onto ca3-coord-record from the mirror's master and merged as ddfaf7a7 through the gate (GREEN, 7 checks in 30 s on f252b514); the first pick hit the audit lane's best-points clause in the litepaper, claims and evidence pages and the resolution keeps master's text with only the escrow sentence replaced by "No outside review has run yet." (main: the right sentence); the design pass stays on ca3-coord for its own landing on main's word after the captures. ADV-ACCEPT-3 CLOSED (the v5 lane, 23:12 UK): 8ca66afa closes its class as stated (the 9.0 percent of rewritten 256th-attempt programs the rule refuses are repaired for part (a) and re-drawn under the 256-candidate scan; the known-failed test on adv3/steer/2, five more steer rows passing); ledger row AP-F8-3 written (sub-version 3's last resort recorded unreachable and unverified, class v5's verified) at class-v5 7f58af97 with the v5-kits branch merged (the OpenCL, NVRTC and Metal hosts with the leaves upload, the kit scripts); the kit zip rebuilt from the merged tip, /srv/artefacts/packs/packs-ca3-v5-20261007T221001Z.zip sha256 4aaf9b9edfad0e466f6b6b59051250afad6a8e0a340728ec068bec48113c0fc9, the packs and the fingerprint 82b19cbde8557ea5 unchanged; Metal, Apple OpenCL and CUDA agree; AMD and Intel fingerprints owed. A GAP: tools/ledger-page.mjs renders only [A-Z]\d+ ids, so no AP-* row (AP-F8-1 to AP-F8-4) reaches /ledger; the site audit lane widens the regex tonight as its own commit with a known-failed case. THE SPEC SPLIT: the site audit lane holds 1.4.3, 1.4.6 and 1.13 (the acceptance-rule rewrite on spec-accept-23) and builds tools/ci/spec-constants-check.mjs, a constants table in the spec parsed against the crate's pub consts (known-failed first) with the class v4 test vectors stated in 1.4.6, since the attack-pass lane has no read-back test and writes none; the hash lane sent it the file and line of every constant from 017e7037 (= master's igneum-pow byte for byte, cf7d6ccb) plus ACCEPT_TAG, the window cap literal in distinct_ratio_pass and the full Devnet 3 genesis hex, no wrong values, one text quirk: the (c) reject prints "limit 163" while MAX_SATURATED is 164 (the first refused count); main's ruling: the spec words the constant, the message string is corrected on the post-freeze line, never in the frozen 1c420786. The v5 lane's 1.4.7 and 1.8.6 are on both mirrors at class-v5 73daadc2 (23:23 UK; full gate GREEN 58 checks at 066c9cbb): class v5's load class, generator 5 and the id, (c''') with the 0.995 floor and the census, the verified last resort, AP-F4-1 and AP-F1-1, the activation object byte 6 and the seven-window 95 percent signal, the test vectors (the three pinned packs, seed 100767, day 29,337, adv3/steer/2), 1.4.7.6 the constants table in the audit lane's shape (Constant, Value, Where); the state leaves (IGSD1 stream, leaf derivation, keyed sample, the leaf line before M_0, the per-epoch refresh and the witness, the measured cost). THE ERA-DRAW MECHANISM (the crypto lane's adv-cache-2, 6e34ebe3, 23:1x to 23:3x BST; report-chained-cache-2.md section 2.3, the 61-program table: 2 real, 27 drawn-era with epoch and era hex, attempt, id, R, site and ratio, 32 devnet-era controls): the mild residual class has its mechanism; a product's biased low bits (P(bit 0) = 1/4, measured exactly) survive the odd stride multiplier and the stride rotation places them at address bits R and up, inside the 28-bit item index unless R is 28 or more; the devnet era draws R = 29 and cuts them off, so 2 of 32 devnet-era programs carry a site over 1.04x while 13 of 27 drawn-era programs (R 3 to 22) do, 8 over 1.2x, worst era-drawn-28 site 15 at 1.7451x and era-drawn-25 site 11 at 1.3571x; under the 2 GiB genesis dataset (D = 29) R = 29 would show it too; the devnet's cleanliness is an era-draw accident, the chain prevalence is the drawn-era figure. The price to a partial-store chip stays under 0.1 percent of a hash's reads per site, so no chip number moves. Disposition: the class v5 (c''') census was already across drawn eras (each of the 4,600 f8 seeds carries its own era bytes), so the 2.435 percent and the eight of eight stand; the pointed reading runs on box 2 (the v5 lane, about 20 minutes from 23:3x): the 2^20 floor read on the 27 drawn-era programs plus era-fixed-20 and four devnet controls, reporting how many of the eight over 1.2x and the band 1.04x to 1.2x the 0.995 floor refuses; the value-level question (biased product bits feeding an address, independent of the distinctness ratio) and the era draw's R range go to the CA4 file as a named requirement with this reading as its evidence, and the research lane's per-load census gains a drawn-era split; nothing in class v4 or v5 moves without main's word. THE ATTEMPTS CENSUS on the frozen sub-version 3 rule (adv-accept row 90, 23:24 BST, 10,000 seeds): 21,119 rejected candidates, by first failing part (a') unfresh 83.3 percent, (a) stale 11.7, (b) no injecting write 3.1, (c'') low-entropy site 1.1, (c) constant bit 0.4, (c) saturated 0.3, (c') 0.1, the distinct-address floor 0.04, lane-constant and bias 0; per-candidate rejection 0.6787, flat at 67.5 to 68.7 percent over attempts 0 to 3 (independent draws); accepted-attempt mean 2.112, max 24; 0 exhaustions; P(256 consecutive rejections) 8e-44 per seed, so the last-resort draw is unreachable by chance and the attempt index is no lever for a seed-steering attacker; accepted programs' distinct-item mean 127.95 of 128, minimum 123.67; spec 1.4.6's 5.14 percent (the class v3 census) is stale against it, the audit lane rewrites; the second 10,000 queued on build-1. Also PASS: the line census at 2^35 + 3 x 2^33 and the 16,384-day weak-day scan. THE PC 1 QUEUE TONIGHT (the hash lane): run-ca3-pc1-amd-family-20261007-e exit 0 at 22:09:25Z (the 9070 XT alone, gfx1201, driver 3683.0, 32 CUs, three runs every row exact against the alu chain; step costs as a ratio to alu 741 G steps per second: rotr 1.05, shflx 0.89 (bperm native), shl 0.92, shr 0.99, bfe 1.03 native and 0.83 C sequence, andn 0.93, perm 1.21 emulated (perm_amd refused), popc 0.85, clz 0.83, sel 0.72, shfla 0.77 (bperm), dot4 0.75 native (dot4_khr refused), mm8 1.20 (gfx12 path, unverified); the khr and intel shuffle builds refused as on 6 October); the shipper's 0.3.24 host slot holds PC 1; on its "slot closed": fetch-ca3-v5-kit-20261007 (the 4aaf9b9e zip), then run-ca3-pc1-v5-amd-bench-20261007 (the v5 lane's script, the 9070 XT by name, beside the miners, about 3 minutes), lock-free and non-elevated, quiet. The Intel fingerprint: main first routed it to PC 1, the hash lane's device lists (the 22:09Z --list, the kit README) show no Arc on PC 1, and main's second word places the Arc B580 as PC 2's eGPU (tonight's PC 2 crash was an Intel driver install over that card while it mined); the job (tools/class-v5/pc1-intel-v5-bench.ps1 at a4b08245) moves to PC 2 by job after the shipper's 0.3.23 take 3 smoke and the update-return lane's scheduler proof have reported on that box, never concurrent with an install or a build there, the same lock-free class; a fingerprint that differs from 82b19cbde8557ea5 holds that card's v5 kit out of 0.3.24 and the crossing time is stated on its page row. PC 2 carries the RTX 5080 since about 15:00Z (tonight's stock row is that card). THE HASH LANE'S LANDING (the derivation fix, the no-prompt rule, the PC 1 job scripts, the Ember core-clock knob 74585c91: the ladder below 45 percent in 100 MHz steps to a 20 percent floor, the stop rule at the knee or on a faulted row, lock_result and the card's lock_* fields, 18 Ember tests and the app crate's 158 green on box 2, the 1 percent tolerance landing the 5090 at 1,854 MHz on tonight's rows and 1.5 percent at 1,300, the tolerance the manifest's; ledger row AP-F8-4) went RED once on the pre-public scrub (the founder's name in a ledger row and two script comments), fixed, the mirror's master merged in again, the gate rerunning from 23:2x; the merge commit follows. THE FLOOR'S FULL TALLY (adv-accept gap-deep4, 23:25 BST): the four deepest remaining 256-unit seeds all read under 0.995 at the acceptance sample (148927 at 0.9814, 150347 at 0.9896, 34501 at 0.9929, 29307 at 0.9912); the first three clean live (0.9998x to 1.0028x), 29307 at 1.29x on one item from a non-saturated source, no hot set by X_f. Over everything the lane read at 2^20: 8 of 8 live hot sets refused; 6 clean-live programs refused (false refusals) and 1 clean passed among the 9 deepest 256-unit seeds; 3 mild residuals missed at about 1.0004x. The lane's reading of why both sides exist: (c'') counts repeated word indices on the stand-in, which the live set usually spreads thin rather than concentrating, so a low ratio is not a hot set; that is the 2.4 percent clean rejection the floor pays, and a true hot set needs the value-level source test to be caught without it (the CA4 requirement). THE SPEC REWRITE committed on spec-accept-23 (the audit lane, 23:3x UK): 1.4.3 and 1.4.6.1 to 1.4.6.6 to the shipped rule at 017e7037, the shadow block in 1.7, the ninth era draw in 1.13.1, ledger AP-F8-5 (the stale spec text) with the public ledger regenerated, the two tables in the check's shape (Constants of the shipped rule: Constant, Value, Where, 17 rows; Pinned program ids: Seed, Attempt, Id, Note, 6 rows with Devnet 3's full genesis hash and the three must-differ ids); the full gate running; it merges the mirror's master after the hash lane's landing so the check and the text arrive together. THE PER-LOAD FIX (the research lane, counter-asic-4 2f718001, pushed 22:24Z; the fixed pack mx8_shl256x27_v2 22:29Z, attempt 3, id bd64b207a30413fb, the first export 854050a4293f0615 kept as the known-failed record): known-failed first at 22:16Z (tests/ca4_trace.rs on build-2): the first export derived 10,728 distinct items of 12,288 over three units (the class v4 shape 12,286), 1,482 same-iteration duplicate lanes at sites 8, 10 and 15; the mechanism from the 64-seed census (29 of 64 seeds failing, up to 620 duplicate lanes a seed, sources collapsed to 1 to 17 distinct values in 32 lanes): a lossy base writer (mulhi, mul, or) followed by 27 passes of the 16-instruction map collapses the register before the next load, so the static last-writer rule catches only part of it. The fix in two layers: the static redraw (a sub-block writer of the next load's source drawn from the injecting families when it is mul, mulhi or or) and the dynamic acceptance test stepping the per-load sub-blocks in the order the class executes (accept.rs alu_step inside run_unit) with a new rejection DuplicateLanes (any load reading one address in two lanes of a unit), a rejected candidate redrawing the attempt. After, 22:23Z: 12,287 of 12,288 and 0 duplicate lanes on the genesis seed; the census (64 seeds x 2 units on a second dataset, 16,384 load rows) 1 duplicate pair in all (seed ca4-census/49 site 3, the chance floor of a 2^24 index space, about 0.5 pairs expected; the class v4 shape's own trace shows 2 of 12,288 from the same floor); the suite 64 + 2 + 7 + 4 + 19 + 2 + 7 passed on build-2. Owed: the Metal fingerprint (the Mac, one at a time under the measure lock), the F8-form uniformity on the fixed export through the attack-pass harness, the drawn-era split of the census (R 3 to 22 against 28 to 31) and the biased-low-bits requirement row from adv-cache-2, the PC 1 card row on both exports. Nothing in class v4 or v5 moves. THE "LIMIT 163" FIX (the hash lane): the one-line fix on a post-freeze branch off the mirror's master, pow-reject-text-24 at 79c5c07d (pre-push GREEN): the (c) saturated reject text prints its limit as MAX_SATURATED - 1 and names 164 as the first refused count, with the test the_saturated_reject_text_prints_its_limit_from_the_constant reading the printed limit back (green on box 2); the frozen 1c420786 line untouched; it lands with 0.3.25's line. The derivation fix's landing: the second gate run RED on the public-ledger check (AP-F8-4's last paragraph must start with one of the six status words), the row now closing "Status: Fixed (7 October 2026, night)" and docs/ledger-public.md regenerated; the third gate run from 23:3x UK. PC 2's Intel job prepared as run-ca3-pc2-v5-intel-bench-20261007 (the kit fetch to PC 2 first) behind the shipper's "PC 2 clear"; the CA4 packs job on PC 1 runs both per-load exports (dir and id on every row). THE FLOOR RE-CUT (main's ruling, the shipper 23:3x UK): the 28,800 floor lost to the clock (the pairs, the hive kits, the fleet's fetches and the ten minutes after the last FETCHED cannot land before 23:52 BST, past the 22:52:16Z slip point), so the node lane re-cuts program_class_v5_activation_daa to 32,400 (epoch 9) on release-0.3.24-node, the same object otherwise (pairing 1c420786, chain id 4464 from the floor, the testnet re-cut inside); the new pin and its gates about 25 minutes from 23:3x; the crossing on Devnet 3 by height then about 01:52Z on 8 October (02:52 BST) at 1.0 DAA/s; the move minute after F9 and F1 PASS and the last FETCHED. THE ERA READING ON THE FLOOR (the v5 lane, box 2, 23:3x BST, igneum-pow at 73daadc2, the 2^20 acceptance sample): 0 of 29 of adv-cache-2's programs are refused by the 0.995 floor at their listed attempt, and the class v5 draw lands on the same attempt as class v4 for all 29; the six over 1.2x read minimum sites 0.9965 to 0.9997 (era-drawn-15's 1.51x site 14 at 0.9965 the lowest), the 1.04x to 1.2x band 0.9986 to 0.9998, the clean ones 0.9999 to 1.0000, the devnet-era controls 0.9996 to 0.9999. So the floor's statistic does not reach adv-cache-2's class: the distinct-index count at 2^20 reads concentration on FEW items (adv-accept's hot sets put 3 percent of a site's reads on 512 word indices, moving the collision count by thousands), not a diffuse excess over the top 0.1 percent of items (era-drawn-15's 1.51x is about +0.08 percent of the site's reads spread over 16,384 items, a few hundred collisions, inside the clean spread). Two classes, two instruments: the floor closes the few-item hot sets (8 of 8); the era-stride diffuse class needs the per-site item-share test at live scale or a draw rule on R and the shadow block's last write (the next class's row); its chip value is bounded by its own diffuseness (a 1 MiB hot table of the top 0.1 percent of items serves about 1.0024x at the worst site read so far, under the AP-F8-1 bound by an order). The v5 design's section 14 gains this paragraph with the 61-row log (era-drawn-25 to -28 and the 32 controls running; era-drawn-28 at 1.75x the one to watch) and its bound sentence corrected (the "top-0.1-percent share under about 1.3x" form, never served, lived in section 14 only); a ledger row for the miss asked. Nothing in the freeze moves. MAIN'S ROW WORDING for Devnet 3: a 0.3.23 node that has not updated falls off at the digest move minute (the fleet's named minute, about 00:52 BST at the latest), not at the 02:52 crossing; the row reads "update before or the node stops following Devnet 3; class v5 begins at DAA 32,400, about 02:52 BST". F4 ON CLASS V5 PASS (the attack-pass lane, 8ca66afa, build-1 under class adv, 379 s, ended 22:3x UTC; the agreed w32 convention, median 226, 2^24 chain days from 20,729): M1 0 of 2^24 days over 1.1x, the minimum cost 206 (day 27,016, 1.097x), so the bound holds with no margin and no day over the line, mean 225.79, sd 6.07 (the pre-rule census 5.69e-4 over, min 203); M2 0 days with k >= 2; day 29,337 redrawn under the rule (203 to 228), day 20,729 at 219 unchanged; AP-F4-1 FIXED-AND-PASSED; F9 and F1 under class release on build-1, lines within the hour. THE CA4 FILE (the research lane, 22:3x UTC, sections 20.2a and 20.2b): the drawn-era split of the per-load census: 16 eras over the fixed class, 2 units each, R under 28: 12 eras, 3,072 rows, 0 duplicate pairs; R 28 and up: 4 eras, 1,024 rows, 0 pairs; every era accepted at attempt 3; the adv-cache-2 reading written as a named requirement (value-level bit-bias of the index at a product-sourced site, judged across drawn eras split by R, owed for every CA4 class and the same item as class v5's acceptance; the per-load dynamic rule covers distinctness, not bias). Metal fingerprints (22:30 UTC, M5 Max under the measure lock): the fixed per-load pack ee5d7c71180e5ea7, vectors 3 of 3, 26.88 MH/s against the control's 27.01 (the placement costs Apple nothing); the tile packs bit-exact against the Rust verifier on the Metal reference path (mm128 270e4ae36b37e9a1, mm512 a1c1ff3148d775d1); the Apple cost is the finding: 1,024 tiles per hash take 35 percent of the M5 Max's rate, 4,096 take 78 percent, so a tile shadow at the ALU shadow's premium would take the Apple tier out unless Metal gains an integer matrix path; the tile class moves from rank 3 to beside rank 5 until that path is measured. Main's rule: no served number mentions the per-load fix before its F8-form uniformity and drawn-era split (the split now read; the uniformity owed). THE PUBLIC SENTENCE ON THE FLOOR (main's wording, 23:3x UK): "eight of eight hot sets refused; the diffuse era-stride excess, bounded under 0.1 percent of a hash's reads per site, is not caught by the floor and is the next class's test", the same words on ledger row AP-F8-1 (landing from ca3-coord-record 6d09d96e with the two-instrument reading and the AP-F8-6 pointer), on AP-F8-6 and in the v5 design's section 14 (the v5 lane, class-v5 54e52b8a at 23:36 BST carrying AP-F8-6, F4's PASS in the attack row and its clock corrections: build-2 prints CEST, every page time re-read to BST); no served page carries a hot-set sentence tonight, so the sentence reaches readers through the ledger once the AP-* regex fix lands. F4's no-margin hold (the minimum accepted cost 206 against the 205 bound at day 27,016) is a record sentence, not a served number. ADV-MIXER-2 CLOSED (the crypto lane, 2a632579 on build/adv-mixer-2, 23:37 BST; 0.31 box-hours, 0 pod-hours): the redraw rule (continue the stream and redraw all 40 draws when the LUT cost A is 205 or less, or a 2-adder MUL, or all ROT equal) over 2^24 and 2^28 days leaves 0 days over 1.1x; 6.0e-4 of days redrawn once, 3e-7 twice, never three times; the mean cost unchanged; verdict BOUND for every chip, GPU and the verifier (gain 1.0 every day at 9,360 ops per item), FINDING on the per-day FPGA LUT-area reading only (2^-10.8 of days over 1.1x, worst 28 April 2050 at 1.113x), closed by the redraw rule or by the spec's O-1.10 day derivation; five lanes closed (adv-cache, adv-accept-2, adv-cache-3, adv-mixer, adv-mixer-2), four to the 00:00 reading (adv-accept, adv-accept-3, adv-cache-2, adv-mixer-3). THE HASH LANE'S BRANCH ON MASTER: da2fc101 at 23:37 BST (ca3-v4-amend a7ff10a2; the full gate GREEN, 69 checks in 351 s): the derivation fix with AP-F8-4 and the regenerated public ledger, the no-prompt rule (publish-jobs.sh refuses --elevated; playbook-quit-check rule 3), the PC 1 and PC 2 job scripts, the Ember core-clock knob for 0.3.24 (ember.rs, state.rs, engine.rs; 18 Ember and 158 app tests green on box 2), the ca3-v4-uniform parallel census; igneum-pow against 017e7037 differs in generator.rs (the recipe refactor, every id and pin unchanged), emit.rs (the one print) and tests/derivation.rs only; the shipper's tip for 0.3.24's engine work is this master. THE 0.3.24 NODE PIN RE-CUT (the node lane, every gate green at 22:39:31Z): c9e385eb on release-0.3.24-node (47b9b229 with Devnet 3's class v5 floor at 32,400, epoch 9, the same object otherwise; pairing 1c420786): build 22:34Z rc 0 (igneumd 7a841b20..., /srv/artefacts/0324-c9e385eb/node-lane), consensus 134 at gate priority, core 175, exec 47, miner 28, p2p-flows 38, pow 19; the Devnet 3 canary set with the new digest d0d6a4754f3bfc4a173aeaddbab0e151583047283932b70cbb8e27878c115e91 (byte 6, override refused, handshake, the shared-devnet dialler and a 2720d8d2 node refused); the testnet canary on b2e856ed unchanged. The floor from the 22:30:17Z read (DAA 20,268, 1.0 DAA/s): about 01:52:29Z on 8 October (02:52 BST), holding for a move minute up to a publish at DAA 25,200 (23:52:29Z, 00:52 BST). The fast-time SUMMARY on c9e385eb asked; the fleet lane asked whether its hub or any reader depends on build-1's three old-object Devnet 3 nodes (the seed on 27632, the observer node, node1), whether they join the move or retire, and which 0.3.24 node the DAA is read from after it; the crossing read at 32,400 and the TESTNET_PARAMS v5-at-0 re-cut follow on that node. THE FAST-TIME GATE ON THE RE-CUT: SUMMARY PASS (cross-0324-c9e385eb) at 22:49:32Z (23:49 BST) on the shipped 0.3.24 re-cut c9e385eb (igneumd 7a841b20..., igneum-miner 1e209b9e..., igneum-pow at the freeze 1c420786), build-1 under lease pool class v5, 22:36:25Z to 22:49:32Z, every check green: rung 1 by signal at epoch 6 (22:42:54Z), class v5 by signal at byte 6 from epoch 8 at rung 1 (22:44:54Z, 4 of 4, 9,985 bps), 11 of 11 ids equal to the CPU verifier's, the stale node 86 of 86 refused with 0 accepted after the first refresh, the restart step across the boundary on a kept datadir resynced in 28.1 s with the catch-up done after 10 s and 0 of its own blocks during it, four sinks equal at 660, honest nodes 0 PoW rejections; record on v5-fasttime 76276be6, docs/design/class-v5-harness/fasttime/cross-0324-c9e385eb.json. The 0.3.24 move's gates left (the shipper's correction of this record): not F9 and F1's full 10^5 PASS (landing about 00:40 BST, too close to the 00:52 ceiling) but an F9/F1 interim line from the attack-pass lane read inside the five minutes before the minute showing 0 exhausted, 0 panics and 0 redundancy failures over everything drawn so far (16,003 seeds at 23:35 BST, max attempt 25), any non-zero holding the move, the full 10^5 the record line after; the minute named by the fleet on the last FETCHED plus ten once the build-server lane's c9e385eb pairs land. THE 61-ROW ERA READING (the v5 lane, box 2, 23:4x to 23:5x BST, docs/design/class-v5-harness/v5-listed-adv-cache-2-full.log): 0 of 61 refused by the 0.995 floor at the table attempts (the two real programs, 27 drawn-era, 32 devnet-era controls), every class v5 draw on the class v4 attempt; era-drawn-28 (id 5e9eb01efbbf653e, attempt 6, R 15, the worst of adv-cache-2's census at 1.7451x) reads its biased site 15 at 0.9969, over the floor by 0.0019; era-drawn-25 (1.3571x, R 21) site 11 at 0.9994; the eight over 1.2x span 0.9965 to 0.9997 while the eight few-item hot sets sat 0.003 to 0.013 under the line. Main's sentence opens AP-F8-6 and section 14 verbatim with the two-instrument reading under it. THE CLASS V5 ATTEMPTS CENSUS for 1.4.7 (1,000 f8 seeds through the chain draw, v5-attempts-census-1000.log, the crypto lane's form): 3,219 candidates, 2,219 rejected, per-candidate rejection 0.6893 (sub-version 3: 0.68), accepted attempt mean 2.219, 0 exhaustions, P(256 consecutive) 4.4e-42; first failing part (a') 83.4 percent of rejections, (a) 10.7, (b) 3.0, (c'') 1.2, (c''') 1.0 (0.7 percent of candidates, one in 140: the floor's own share, 0.045 on the attempt mean), (c) 0.7 together, (c') none; the 5.14 percent of class v3 that 1.4.6 quotes is the audit lane's to replace. Both on class-v5 at 3b1dffd6 with main's sentence (891dd008), the mirror's master merged (e0471019: AP-F8-1's update and AP-F8-4 taken, the program-id recipe form with the state tag, no conflict), the design page's pre-public scrub (the founder's name six times, gone), M35's status word and the regenerated public ledger; the push waits on the full gate and the pinned-packs test on the merged tree (the proof that e5a4ac5978462156 and the other ids still derive under master's recipe form). THE 00:00 BST READINGS (the crypto lane; the verified roll-up of all nine lanes in section 13 of in-house-pass.md on crypto-engage, every branch tip read from the mirror and igneum-pow identical to 017e7037 on each). adv-accept, tip a7c49399 (about 5.5 box-hours, 0 pod-hours): 182,646 distinct accepted programs drawn (18 percent of the 10^6); eight pass every part of the frozen rule and flag the live hot-set test at 2^24 (X at 0.1 percent +0.102 to +0.221, 1.54x to 2.24x), all in the lowest 34 stand-in-ratio seeds against 0 in 20 random; each about 1 MB of items holding 0.26 to 0.41 percent of reads, 1.002x at the largest; the mechanism a near-saturated source at one site mapped by the era stride to one fixed item (plus two lesser shapes); the exemplar reads the same under the class v5 dataset. Against the class v5 floor: 8 of 8 refused; 3 mild residuals missed (adv-cache-2's rotation class, a load_index question not a floor question); 6 clean programs refused among the 9 deepest (the 2.4 percent). Q2 BOUND (54 programs plus 17 reads, 0 disagreements). Row 90: 0.6787 per candidate, (a') 83.3 percent, 0 exhaustions, P 8e-44. Partial named: 18 percent of seeds, 54 live rows, row 90 at half; a longer pass adds rows of the same shapes, not a different answer, unless a seed reads a hot set over 1 percent of reads, which 182,646 draws did not produce. THE PER-LOAD CLASS CLOSED (the research lane, for main; clock readings UTC): the per-load shadow fix held for distinctness and then met the value-level requirement from adv-cache-2, and the construction did not survive it; the per-load 16 x 27 class is dead as a chain class. 22:44 the attempt verdicts on four seeds (igneum-genesis 0 of 32 accepted); 22:47 the 64-seed census under the full rule (duplicate lanes at a load row plus the one-count of every index bit per site over the 64 units, 6-sigma band): 22 of 1,621 candidates accepted (1.4 percent), 42 of 64 seeds exhaust the chain's 32 attempts (an epoch without a program); the first failing test per candidate: biased index bit 775, duplicate lanes 643, the base rule 110, (b) 43, (a) 28; candidate 0 of the class carries index bit 0 set in 40 of 1,024 addresses (z 29.5); 22:52 the suite green (64 + 5 + 7 + 4 + 19 + 2 + 7); the acceptance rule with BiasedIndexBit for this class and the tests pushed as the record, the file's 20.2a closed. The structural reason: 27 passes of a 16-instruction map right before a load is an iterated small function and collapses or biases the load's address register before any base instruction re-randomises it; the class v4 shape has 64 base instructions and 16 loads between its block and every load. Both exports were accepted only because the rule did not model the placement; their PC 1 rows stay as an energy reading of the placement, labelled unsound. Rank 4 and the USD 200 M capex row rest on a construction not shown to exist (chip model 5.11's clause marked so in this landing); the sound form is one pass of a 432-instruction sub-block per load (a program segment, not an iterated map), a new class to draw, accept and measure, not tonight's. Replicated by a second instrument: the class v4 shape on this pre-amendment generator carries the adv-cache-2 product bit at address bit R exactly in 14 of 17 drawn eras (one-count 250 or 780 of 1,024, z 15 to 19), 0 duplicate pairs across the eras. What stands from the two prototypes: the tile block (bit-exact on the Metal reference, the AVX2 verifier at 0.047 us per tile, the Apple emulation cost 35 to 78 percent) awaiting its 5090 rows; the per-load placement closed. THE SPEC REWRITE ON MASTER (the site audit lane, 8b834634 at 23:56 BST; gate GREEN on 64e2a91b, 71 checks; the igneum-pow suite green on the box for that commit with derivation.rs and spec_readback.rs): spec 01 sections 1.4.3 and 1.4.6.1 to 1.4.6.6 rewritten to 017e7037 with the 20-row constants table (ACCEPT_TAG, the window-cap literal, MAX_SATURATED as the first refused count with the 163 message noted) and the 6-row pinned-ids table with Devnet 3's full genesis hex; the shadow block in 1.7; the ninth era draw in 1.13.1; tools/ci/spec-constants-check.mjs in the gate (known-failed first, every Constant | Value | Where table, pending rows skipped while absent); igneum-pow/tests/spec_readback.rs (ids derived through the crate, each class v4 row drawn to its attempt); ledger AP-F8-5 after AP-F8-4; the ledger-page fix (both heading forms, the pass as its own section, known-failed self-test in the gate; AP-F8-1, AP-F8-4 and AP-F8-5 render on /ledger); the fud-ledger's two prize clauses and "paid independent cryptanalysis" removed at the source so the regenerated page carries neither (commit 90424d5a, merge 64e2a91b). A HARDWARE FACT IN DISPUTE, for main: tonight's 5080 efficiency rows came from PC 1 jobs (run-ca3-pc1-v4-eff-5080-20261007-b and -c), the audit lane's record reads the RTX 5080 and the Arc B580 on PC 1, the hash lane's 22:09Z device list on PC 1 shows the 5090, the 9070 XT and the 4070 only, and main places the 5080 and the B580 on PC 2; identity-check.sh's "PC 2" substitution text names cards and is left card-free until the PC 2 job's own --list settles which cards sit where. THE IDENTITY CHECK'S PC 2 TEXT (the CI steward, 00:05 UK on 8 October): tools/ci/identity-check.sh rewrites "PC 2" card-free as "the second Windows rig" (commit 40f2be54, merge 0d2cf334, gate GREEN 71 checks, identity grep 0 hits over 306 export files and 52 served pages); line 69's PC 1 list untouched; the reason recorded in a bash comment above the perl call. THE 32,400 FLOOR LOST (the node lane, 00:0x UK on 8 October): dn3-g1's chain read DAA 25,126 at 23:52:03Z and 25,169 at 23:52:38Z, so the publish DAA passed 25,200 at about 23:53:09Z with no 0.3.24 move made (build-1's three Devnet 3 nodes last restarted about 21:31Z on the 0.3.23 move; the old seed holds 38 peers on ba75bf6f; no move minute was named). The next boundary is 36,000 (epoch 10), about 02:52Z on 8 October (03:52 BST) at 1.0 DAA/s, holding for a publish up to DAA 28,800 (about 00:53Z, 01:53 BST). Two routes put to the shipper and main: the same re-cut script on release-0.3.24-node (program_class_v5_activation_daa 36,000, nothing else, the same gate set, about 20 minutes to the pin line), or the fleet names its minute first and the floor is cut from it in one go (publish DAA plus 7,200 to the next 3,600) instead of a fourth chase; the pin c9e385eb stands meanwhile. THE FLOOR RE-CUT FROM A NAMED MINUTE (the shipper, 00:1x BST on 8 October, under the slip rule main set with the object commit): the floor re-cuts once more to 39,600 (epoch 11, about 04:52 BST) from a move minute the shipper named: 02:00 BST on 8 October, or the fleet's last FETCHED plus ten if later but before 02:53 BST (DAA 32,400, the ceiling); the node lane's pin line in about 20 minutes with the new Devnet 3 digest; the F9/F1 interim read at 01:55 BST; the publish minute equals the move minute (the apps' entries at or after it); the fast-time SUMMARY PASS reruns on the new pin as part of its gate set; the cause of the lost floor named: the c9e385eb pairs and the two PC jobs unreported for forty minutes, so the fleet had nothing to point its move file at. "slot closed" on PC 1 still waits on the host job's exit. THE 0.3.24 NODE PIN AT 39,600 (the node lane): dfbd1e10 on release-0.3.24-node (both mirrors, 23:54:13Z) = c9e385eb with program_class_v5_activation_daa 39,600 (epoch 11), nothing else; pairing igneum-pow 1c420786; every gate green at 00:01:52Z (build 23:56Z rc 0 at gate priority, igneumd 4870ccf2..., igneum-miner aa8c2978..., /srv/artefacts/0324-dfbd1e10/node-lane; pow 19, consensus 134, p2p-flows 38, exec 47, core 175, miner 28); the Devnet 3 canary set (23:56:33Z to 23:58:13Z): digest b1ba78229b069dc395fa666638a686a66615eb760d251798adfa6a654a415f82 on igneum-devnet-3 from ba75bf6f, object version 6 stamped (block version 1538), the override file refused, shutdown 2,015 ms, two empty nodes handshaking on it, the shared-devnet dialler rejected, a 2720d8d2 node refused on the digest both ways; the testnet canary b2e856ed unchanged (byte 7, a live old-object testnet node refused). The cut's read: dn3-g1 at DAA 25,169 at 23:52:38Z (1.0 DAA/s), the publish DAA at the named minute 01:00Z about 29,211, plus 7,200 = 36,411, the boundary 39,600 about 03:53:09Z on 8 October (04:53 BST), holding for a publish up to DAA 32,400 (about 01:53:09Z, 02:53 BST). The one gate running: the fast-time pair on dfbd1e10 (about 13 minutes from its start). c9e385eb is void as a pin; the F9/F1 interim read armed at 00:55Z. THE TWO PC QUEUES AT 01:03 BST (the hash lane): PC 1's "slot closed" has not come (the shipper's 0.3.24 host job, the build-server lane's, took the slot at 22:13Z for an expected two to three minutes; nothing reported in 110 minutes); nothing of the hash lane's has run on PC 1 since 22:09:25Z; the v5 kit fetch and the 9070 XT v5 bench are prepared and unpublished (tools/ca3-v4-amend/pc1-publish-20261007.sh, steps v5-kit and v5-amd), so no 9070 XT class v5 fingerprint exists yet; the lock protocol holds unless main says the lock-free pair goes ahead of the silent host job. PC 2's "clear" has not come either (the 0.3.23 take 3 smoke and the scheduler proof unreported by either lane); the Intel job is prepared and unpublished. THE HARDWARE FACT, read from tonight's PC 1 lines: nvidia-smi on PC 1 lists GPU 0 RTX 5090 (bus 01:00.0) and GPU 1 RTX 5080 (bus 0D:00.0); its OpenCL list carries the RX 9070 XT (gfx1201) and the integrated gfx1036 and no Intel platform; so the 5080 is on PC 1 (the audit lane's record right, the 22:09Z device-list summary short by one card) and the Arc B580 is not, which agrees with main's word that it is PC 2's eGPU; the kits row, the bench notes and identity-check's card-free PC 2 text stand on that. The locked PC 1 jobs stay parked (the 5080 full grid, the third 5090 pass, SM-sparse, the microbench and packs knee states, the two Ember tunes, the hot-table ldcs rows); the lock-free CA4 rows queue after the v5 bench on the same "slot closed". THE 00:00 BST READINGS, THE OTHER THREE (read by the crypto lane from each branch's report on the mirror at 01:03 BST; the roll-up section 13 of in-house-pass.md at crypto-engage c84ba51b with adv-accept's reading at 1b4e07ff; all nine branch tips read back from the mirror and igneum-pow IDENTICAL to 017e7037 on every one: adv-mixer d2ba3134, adv-mixer-2 2a632579, adv-mixer-3 4ebe2455, adv-cache 555c3e42, adv-cache-2 9384ee09, adv-cache-3 9452c0bf, adv-accept a7c49399, adv-accept-2 92168536, adv-accept-3 0c150e3c). adv-accept-3 (exhaustion or steering of the draw), tip 0c150e3c, every sweep ended 23:05 BST, about 3.3 box-hours, 0 pod-hours: Q1 exhaustion BOUND (per attempt accept 0.323, reject 0.677 ((a') 0.568, (a) 0.079, (b) 0.022, dynamic parts about 0.009), geometric histogram, P(exhaust) 0.677^256 = 4.6e-44, 0 of 16,337 seeds at the cap); Q1b the last resort FINDING (correctness; the mirror fired at cap 256 byte-identically; of 3,000 last-resort programs the real rule rejects 271, 9.0 percent: 251 by (a), 14 by (b), 6 by (c) distinct sum; handed out unchecked; unreachable; closed in class v5 by 8ca66afa, AP-F8-3); Q2 steering BOUND (45 of 48 planted rows fired, the real rule rejects every effective plant by (a'); 975 seeds at the first part, min ratio 0.998, 18 of 18 chain re-draws equal); Q2b the price of a seed property at 1 in 10^6 tries is a shadow block with 38 multiplies of 256 against a mean 74, about 2 to 3 percent of the f = 1 chip's energy per hash, the load critical path worth nothing at the memory activate ceiling; Q2c the 256-unit ratio is noise as a selector; Q3 program id FINDING (documentation: the "sub/" || 3_le16 suffix omitted from program.json and spec 1.4.6; a text-derived implementation computes 30956569d8f3d8d7 for Devnet 3 against the pack's fce15bf61030be57; 0 collisions over 10^7 pairs; fixed as AP-F8-4 at da2fc101); Q4 determinism DONE (the (c'') f64 compare never disagrees with the integer rule on any of the 2^20 + 1 values, margins 0.32 to 0.44 counts; a second interpretation agrees on 5,748 of 5,748 verdicts of 1,792 seeds); Q5 the era lever BOUND (400 eras, no stride under NAF weight 7, all 31 rotations, 354 distinct interleaves; epoch 0's accepted attempt is 3 under every era, so the era moves the address map, not the program). Partial named: the steering sweep at 975 of a planned 10^5 seeds (about 8 box-hours more at 32 cores). adv-cache-2 (the hot-set attack), tip 9384ee09 at 23:52 BST, about 2.2 box-hours by wall times threads over 96 (the boxes at load 400 to 600 for the first two hours), 0 pod-hours; two shards still queued at 00:00 (lines-2e30-s2c, warps-devnet-2e25-v2), named partial: Q1 the line index PASS (pooled 16 days; segments max +4.84 sigma against a control's +4.24, lines +5.61 against +5.35, chi2/dof 0.99937, top 0.1 and 1 percent of lines 1.0003x and 1.0002x of control; the 2^35 + 3 x 2^33 census all PASS; 0 mirror mismatches); Q2a the real programs PASS on the hot-set test (devnet at 2^26 1.0002x; Devnet 3 at 2^26 items 1.0071x, lines 1.0000x) with the FINDING at Devnet 3 site 0; Q2b all 64 programs done, every one clear on the hot-set test (items 0.9993x to 1.0075x of the windowed control) but the site class as recorded above (13 of 27 drawn-era over 1.04x, 8 over 1.2x, worst 1.7451x; the v5 floor refuses 0 of 61; AP-F8-6); Q3(1) steering by t PASS (worst cell 3.95 sigma in 2 x 2,112 cells); Q3(2) the weak-day scan PASS over 16,384 days (2^30 derivations in 707 s; worst per-day max bucket +8.13 sigma against the control's +7.78; the plant fired at +1,090); Q3(3) the window layer: the exact distribution matches the 4,096-program census to four digits (top quarter mean 0.3382, top half 0.5811), with a FINDING against the chip model's table: the f = 0.25 and f = 0.5 partial-store rows overstate the recompute share by up to 1.8x at f = 0.5, the full-store (f = 1) verdict unchanged (a correction owed in chip-model-v3's partial-store rows; no served number rests on f under 1); Q4 the prices: the only measured excess over f is the window layer's and the line reference multiplicity (a hottest-lines half store hits 57.8 percent instead of 50 at a higher miss cost than the stride). adv-mixer-3 (the statistical distinguisher and round margin), tip 4ebe2455 at 00:41 BST, still RUNNING at 01:03 (Q3 and Q4 at k = 8 on day 20729, queue 07 in the pool, the SAT ladder at k = 3 timed out; the total box-hours the lane's to give): Q1 the exhaustive round-0 line-index census over all 2^32 t PASS to k = 8 on days 20729 and 20733 and at k = 2, 3, 4, 8 on 20730 (z within 1.5); Q2 single-bit avalanche FINDING at k = 1 (354 and 266 holes, 130,000 cells beyond 6 sigma, the known one-application diffusion), PASS from k = 2 at 2^24 (0 holes, worst z under 5.3 through k = 8); Q2b the t-bit avalanche the same shape; Q3 differential multiplicity over 576 low-weight differences FINDING at k = 1 (695 and 537 deterministic output bits), PASS k = 2 through 7, k = 8 running; Q4 and Q4b linear correlations PASS from k = 1 (worst c 0.00046 to 0.00062, z under 5.1); Q5 rotational-XOR PASS from k = 1; Q6 SAT: k = 1 SATISFIABLE in 137 s (t = 0x49880000 verified through the real code), k = 2 and 3 TIMEOUT at the one-hour cap. The round margin as it stands: no statistic survives 2 of the 8 applications between reads; a chip gets nothing from the k = 1 findings because every read sits behind 8. The lanes' own lines go into section 13.1 as they arrive. THE LANES' OWN 00:00 LINES (adv-accept-3 and adv-mixer-3, 01:0x BST, in section 13.1 of in-house-pass.md): adv-accept-3's P(exhaust) refined to 1.0e-43 per epoch seed from 62,240 full-rule candidates plus 3.0e6 static candidates; Q2 steering BOUND over 19,975 full-rule and 1e6 static seeds, no property buying over about 1.03x at 1 in 1e6 tries; a second documentary FINDING: an implementation written from the spec text (not the code) at 017e7037's spec differs on 264 of 400 epoch programs, the same text-against-code gap as the id suffix (the audit lane's rewrite 8b834634 with spec_readback.rs is the fix; the proof that it closes this is a re-run of the text-derived implementation against the rewritten text, asked); a plant note: the floor-0.97 known-failed variant did not fire because the (c'') ratios are bimodal (accepted 0.989 to 0.999, rejected 0.814 to 0.966), replaced by a single-pass (a) variant that did; 3.3 box-hours, nothing running. adv-mixer-3: about 3.0 wall-hours of sweep plus 4 single-core CaDiCaL hours; the round margin stated as 6 of 8 applications between reads and 70 of 72 per item on every measured statistic, the k = 1 effects one mechanism (the lowest-set-bit trail through one application, dead once both addends carry a difference), nothing saving one application against 9,360 ops per item; still running at 4 cores on build-1 (2^27 and 2^28 avalanche rows, finish about 03:00 BST) and the day-20733 SAT ladder on build-2 (about 03:45 BST); not attempted: multi-bit linear masks and a MILP trail bound. adv-cache-2's own line still owed. ADV-CACHE-2'S OWN LINE (01:05 BST, tip 3f50d6c4; section 13 of in-house-pass.md now carries every lane's reading in its own words plus the verified roll-up): the drawn-era prevalence read on the SAME 32 base programs is 2 of 32 under the devnet era against 16 of 32 under drawn eras (8 over 1.2x, worst 1.75x), the mechanism carried by rotl(x times M, R) into the item index unless R is 29 or 30 (2 of 31 rotations), with a sub-class of warp-uniform sources once in 16,000 warps; the window layer's price restated: a chip holding the hottest f of items serves 0.4219, 0.7188 and 0.8907 of reads at f = 0.25, 0.5 and 0.75, so the chip model's partial-store rows overstate the recompute share by up to 2.3x on these programs, the f = 1 verdict unchanged (the correction to chip-model-v3's partial-store rows is the coordinator's next commit); partial named (the drawn-era windows census of 4,096 and one line shard in the pool); the longer-pass line: the biased-site rate per era in closed form (the R in {29, 30} rate 2 in 31) and a 2^28 read of the worst site. Nothing of the pass stands between the pool and a higher-class job except two pre-emptable shards on box 2. THE SPEC-TEXT RE-DERIVATION ORDERED (01:06 BST): adv-accept-3 re-derives its 400 epoch programs from the rewritten spec text alone at master 8b834634 (1.4.3 to 1.4.6 grown from 79 to 198 lines with the constants and pinned-ids tables), lease pool 16 --min 8 class adv, row Q4c in its report; the expected reading 0 of 400, any non-zero naming the diverging sentence to the audit lane; the proof that AP-F8-5 closed the text-against-code gap. THE CHIP MODEL'S PARTIAL-STORE ROWS carry a second correction (section 5, 8 October 2026) from adv-cache-2's window-layer reading: a chip holding the hottest f of items serves 0.4219, 0.7188 and 0.8907 of reads at f = 0.25, 0.5 and 0.75, so the uniform-store rows overstate the recompute share by up to 2.3x; the f = 1 row, the SRAM column and the full-store verdict unchanged, no served number on f under 1. THE CLASS V5 PACKS TEST ON THE MERGED TREE (the v5 lane, 01:0x UK): the job ran on box 2 the minute two adv-accept holders ended (65 cores; no lease fault, plain starvation before); 19 passed, 1 FAILED: v5_pack_is_the_v4_program_over_the_state_leaves (tests/packs.rs:977), the byte-for-byte compare of every pinned pack file with the crate's export. The ids are EQUAL (v4-genesis exports a217c7f698880830 as pinned; the state tag rides in master's recipe form unchanged); what differs is the program_id_derivation TEXT in program.json, which master's export (the hash lane's AP-F8-4 read-back form) now writes as "... || attempt_le32 || 'sub/' || sub_version_le16" for generator 4 while the pinned packs carry the pre-suffix wording. Disposition: the three pinned packs re-exported from the merged crate (text only; the ids, kernel texts, leaves and the fingerprint 82b19cbde8557ea5 must come out byte-identical, proved by the same test); the CLI rebuilding on build-1 from 51aa5bc4, the export from the box's IGSD1 streams, the packs test and the full suite on box 2 at 16 cores, then the push; readiness about 01:35 UK. The 0.3.24 kit zip (packs-ca3-v5-20261007T221001Z.zip) carries the old derivation text in its program.json files: a text field only, no id, kernel or fingerprint change, so the kit stands for 0.3.24 and the shipper is told; the re-exported packs go in the next kit. THE ONE 0.3.24 KIT, NAMED for the shipper (01:1x BST): packs-ca3-v5-20261007T183921Z.zip, sha256 e6c088bb34fecdc3ff297dbb06438a14ade7d8c55273357726d28f7a1334a25e, byte-identical to the frozen 1c420786 the pin pairs with; the fleet keeps placing it. The 23:11 zip packs-ca3-v5-20261007T221001Z.zip (sha256 4aaf9b9e..., /srv/artefacts/packs/ on build-1, from class-v5 7f58af97) carries the same packs, ids, kernels, leaves, fingerprint and derivation text and differs only in the merged kit host code and scripts beside the packs; it is the bench lanes' kit for the fingerprint jobs. The coordinator's earlier line naming 4aaf9b9e as the 0.3.24 kit was wrong and is corrected here. THE SPEC-TEXT READ-BACK RUNNING (adv-accept-3's Q4c, 01:11 BST on build-2, lease pool 16 --min 8 class adv): the same 400 epoch seeds re-derived from the spec text at master 8b834634 alone (1.3, 1.4.2, 1.4.3, 1.4.6, 1.6, 1.7, 1.13.1; a fresh text interpretation), compared field for field with the chain draw; the count about 01:21. One sentence already named divergent before the count: 1.4.6 part (c) cites dataset_elem(idx, S[0], S[1]) "of verify.rs" without stating its six operations, so part (c) cannot be computed from the text alone and the derivation takes that one function from the crate; the audit lane is to state the closed form's six operations in the text or the constants table, else 1.4.6 stays code-dependent on that line. A NINTH LIVE HOT SET (adv-accept, 01:12 BST): seed 228763 (id 2c4be0f6dc44c423, stand-in 0.9820) at 2^24 (X at 0.1 percent +0.118, 1.82x the window model), its single hottest item 0xe2cc96 at 1,218,380 reads, 0.057 percent of ALL reads, the largest single item of the pass (40x 100767's), from a NON-saturated source r0 at site 9 (the sel register), saturated-source share 0.000: the third shape at scale, a value-level concentration neither (c') nor a saturation test can see by construction; its 2^20 ratio against the 0.995 floor lands in minutes and decides whether the floor's instrument reaches it (if missed, the exemplar for the next class's non-saturated case). 638990 reads 1.51x beyond the gate with one item at 0.027 percent (r0, no saturation), no hot set; 623492 clean. Tally: 9 hot sets in 37 tail seeds against 0 in 20 random, 269,250 programs drawn; the price unchanged at 1.002x (0.27 percent of reads on 1 MB; one item 64 bytes). The public sentence's "eight of eight" moves to "nine of nine" or gains the first miss when the ratio reads. THE FLOOR REACHES THE NON-SATURATED SHAPE (adv-accept gap-tail3, 01:13 BST): seed 228763 reads minimum site 9 at 0.9809 at the 2^20 sample, the lowest of the pass, REFUSED; 638990 site 2 at 0.9872, REFUSED; 623492 (clean live) site 0 at 0.9922, REFUSED, a seventh false refusal. Final tally over everything the lane read at 2^20: 9 of 9 live hot sets refused (0.9809 to 0.9919), both single-item programs refused, 7 clean-live programs refused and 1 passed among the 12 deepest 256-unit seeds, 3 mild residuals missed at about 1.0004x. The reading: the distinct-index ratio reads any few-item concentration whatever its source, saturated or not, and misses only the diffuse era-stride excess; the class v5 floor closes the hot-set class entire at the 2.4 percent clean-rejection cost; the next class's value-level test is for the diffuse class alone. The public sentence reads "nine of nine hot sets refused" from here (the v5 lane's follow-up cfce57ea rides its push; AP-F8-1 on master updates with the next record commit). THE FAST-TIME GATE ON dfbd1e10: SUMMARY PASS (cross-0324-dfbd1e10) at 00:12:57Z on 8 October (01:13 BST), the shipped re-cut's binaries (igneumd 4870ccf2..., igneum-miner aa8c2978..., igneum-pow 1c420786), build-1 under lease pool class v5, 23:58:56Z to 00:12:57Z, every check green: rung 1 by signal at epoch 6 (00:05:37Z), class v5 by signal at byte 6 from epoch 8 at rung 1 (00:07:46Z, 4 of 4, 9,985 bps), 12 of 12 ids equal to the CPU verifier's, the stale node 95 of 95 refused, the restart step across the boundary on a kept datadir resynced in 36.2 s with the catch-up done after 11 s (4 IsInIBD refusals of its own miner during it, 0 of its blocks accepted), four sinks equal at 661, 0 PoW rejections on the honest nodes; record on v5-fasttime 0a09eb78, docs/design/class-v5-harness/fasttime/cross-0324-dfbd1e10.json. Every gate on the pin is green; the move waits on the pairs on the dl host, the last FETCHED plus ten, and the F9/F1 interim read. THE RE-EXPORT READ (the v5 lane, box 1 with the merged crate ac285733): the three pinned packs' only difference was program.json's program_id_derivation text (generator 4 now "|| 'sub/' || sub_version_le16", generator 5 the class recipe "igneum-program-rw/ ..."); ids, kernel texts, leaves.bin, vectors and the fingerprint 82b19cbde8557ea5 byte-identical; the pinned packs carry the merged text; the full gate and the full igneum-pow suite with the packs test and spec_readback running on that tree, the push and commit string about 01:45 UK; main's sentence at nine of nine on AP-F8-6, section 14 and spec 1.4.7.2 at class-v5 b5d6368d (nothing with eight of eight reached the mirror). AP-F8-1's two eight-of-eight lines on master move to nine in this record commit. THE MOVE'S SOURCE (the shipper's ruling at 01:05 BST, corrected to this record at 01:1x): the 02:00 BST move does not wait on the build-server lane's pairs; that lane is dark (nothing published since 23:05 BST, nothing answered since 00:17), so the fleet moves EVERY Devnet 3 node from the node lane's dfbd1e10 pair at /srv/artefacts/0324-dfbd1e10/node-lane on build-1 (igneumd 4870ccf2, igneum-miner aa8c2978, the pair every gate ran on, native glibc 2.39 on every fleet box), the way dn3-g1 and g2 moved at 22:30; the fleet's puller fetches from build-1, not the dl host. The move waits on the fleet publishing the dfbd1e10 move file and naming the minute (asked 01:05) and the F9/F1 interim at 01:55. The hive and the Windows pairs are the dark lane's loss for tonight unless main gives the shipper the word to build them (asked 01:06); the Mac entry publishes at the minute regardless; if the fleet has not published the move file by 01:40 BST, main and the coordinator hear it with the clock. THE PC 1 LOCK VOID, THE V5 AMD BENCH PUBLISHED (the hash lane, 01:1x BST): the shipper's 0.3.24 host job was never published to the jobs file, so the slot was void (the shipper's "slot void" at 01:05 BST); the v5 kit fetch landed on both PCs at 00:12:06Z (919,273 bytes, sha256 ok); run-ca3-pc1-v5-amd-bench-20261007 published 00:14:19Z (the 9070 XT by name, about 3 minutes, lock-free), its start line printing app_version, so the 0.3.20 or 0.3.23 reading of PC 1's app comes with the fingerprint; PC 2's Arc job needs only the shipper's "PC 2 clear". PC 1's app had NOT taken the 0.3.23 kit as of the last reads (every job log through 21:46Z app_version 0.3.20; the install folder's exe igneum-app 0.3.20, mtime 12:24:42Z, sha256 0443ae17...). The update-return lane (a22d765a2e0355a9f) last spoke at 23:0x BST: the helper workaround for 0.3.20 scripts (truncate cmd.txt, restart the task, wait for helper.alive, then write; or four leading " dev " padding lines), the locked jobs held as they are, power-helper-24 b9a72b9b merged into release-0.3.24 (daa7427b: a silent change becomes a logged line, the helper writes its exit reason), install-close-23 4ad6c199 for 0.3.23's take 3, the re-probe job when PC 1's app has taken the 0.3.23 kit; nothing since. THE SPEC-TEXT READ-BACK PASS (adv-accept-3 Q4c, 01:11 to 01:15 BST on build-2 at 16 cores; report section 6.5 on build/adv-accept-3, log 983-textderive-8b834634.tsv, pushed): the spec text at master 8b834634, implemented fresh without the crate's generator or rule, reproduces the same 400 class v4 epoch programs as the code with 0 of 400 differences (every instruction, the chosen attempt, the id, the rejection sequence); the 264-of-400 divergence against the text at 017e7037 is closed, so AP-F8-5 reads fixed on a measurement. The one remaining gap: 1.4.6.4 names dataset_elem "of verify.rs" without its six operations, so parts (c), (c') and (c'') still take that function from the crate; the audit lane's one-sentence closed form (asked 01:1x) closes it, and the read-back re-runs on the new text. THE AMD CLASS V5 FINGERPRINT (PC 1's RX 9070 XT, gfx1201, beside the miners, lock-free): 82b19cbde8557ea5 at 01:16:14 BST, equal to the kit e6c088bb's on Metal, Apple OpenCL and CUDA, self-test PASS, the v4-genesis control 892b6d55a7ddcfcb PASS; the 0.3.24 kit stands on four platforms; Intel waits on PC 2 (held until main's word, since the 0.3.23 take 3 never ran there); PC 1's queue continues with the CA4 unlocked rows. The kits row reads: Metal, Apple OpenCL, CUDA, AMD equal; Intel not measured tonight. THE UPDATE-RETURN LANE'S THREE READINGS (01:17 BST, from the live manifest and the intake): (1) 0.3.23 take 3 (install-close-23 4ad6c199) never reported; the live manifest igneum-app-latest.json reads 0.3.23 published 20:37:44Z with platforms = {mac} only, NO Windows entry, so neither PC has anything to take through its update path; PC 2's app run is still take 1's relaunch from 21:08:43Z (997 uploads, last 00:16Z); (2) PC 1 will not take 0.3.23 unattended tonight for want of a Windows entry; its run win-ae432dc7-20261007-160110 (0.3.20) never restarted (2,376 uploads, last 00:16Z), mining 18.96 MH/s on the 9070 XT; when a Windows entry is published the 0.3.20 engine's OTA takes it with no hand; the 21:41:32Z helper.ps1 write was not the prompt path (0.3.20 writes that file unconditionally), so no screen is owed in the morning for it; (3) the re-probe job (relay/playbooks/pc1-helper-reprobe.ps1 on power-helper-24 69f3c733) waits only on PC 1's exe becoming 0.3.21 or later; the 0.3.20 workaround is cleared to run tonight as a lock-free job so the locked grids go ahead: per grid job, before the first command, empty sweep\cmd.txt, Stop-ScheduledTask and Start-ScheduledTask 'Igneum Power Helper', wait until helper.alive is within 4 s, then write the lines with climbing sequences (in 0.3.20 the skip is the line count at the helper's start, fixed for its life); the helper idle-exits 20 minutes after its last command and the next start must begin over an empty file again; never pad after a command. The coordinator's order to the hash lane on it: the locked grids proceed in the earlier order (the 5080 full grid, the third 5090 pass to the driver's floor, SM-sparse, the two Ember tunes, the hot-table ldcs rows), each with its restore step, under the no-prompt rule; a Start-ScheduledTask that reads the 0x800710E0 refusal again stops the job and reports, nothing escalates. THE LOCKED GRIDS UNDER THE WORKAROUND (the hash lane, 01:2x BST; commit 24f9858e on the mirror): the three lock scripts carry the cleared sequence (empty sweep\cmd.txt, Stop- then Start-ScheduledTask 'Igneum Power Helper', helper.alive within 4 s with a 60 s cap, then dev + command with climbing sequences; repeated before any write when helper.alive is older than 10 s; a refused start 0x800710E0 or no heartbeat stops the lock path with the text on RESULT lines, nothing escalates; no padding; each grid job ends with rgc through the same sequence and the applications clock read back). PC 1's app_version on the v5 bench's start line: 0.3.20 (no Windows 0.3.23 published, nothing to take). The CA4 SM-sparse job run-ca4-pc1-ca4sparse-5090-20261007 runs since 00:20:40Z on the earlier padded script (unlocked rows first, then its 1,300 knee attempt; about 25 to 50 minutes); then in order on the shipper's acks: the 5080 full grid as run-ca3-pc1-v4-eff-5080-20261007-d, the third 5090 pass (1,100 MHz down), the microbench and the seven packs, the 5080 Ember tune, the 9070 XT tune pass, the hot-table ldcs rows; the 5080 grid's knee and best points to the site audit lane for row 17 as read. THE ATTEMPTS CENSUS COMPLETE (adv-accept row 90, 01:34 BST, 20,000 seeds, closing the partial named at 00:00): 42,711 rejected candidates; (a') 83.5 percent, (a) 11.6, (b) 3.0, (c'') 1.1 (459 candidates), constant bit 0.4, saturated 0.3, (c') 0.05, distinct 0.04, lane-constant and bias 0; per-candidate rejection 0.681, flat across attempts 0 to 3 (the halves agree to a tenth of a percent); accepted-attempt mean 2.136, max 28; 0 exhaustions; P(256 consecutive rejections) 2e-43 per seed. The number for spec 1.4.6: under sub-version 3 the per-candidate rejection is 68.1 percent and the expected attempt 2.1. adv-accept's shards run on in the pool's gaps under the mechanical yield; the box-hours cross 8 later tonight. CLASS-V5 LANDED ON BOTH MIRRORS (the v5 lane, 091a0758 at 01:40 UK): the full pre-push gate GREEN at 71 checks (stamp on 48d38493, the last code change); the igneum-pow suite on box 2 (74 unit, derivation 2, derive 7, mixer 4, packs 20 with the three pinned packs byte-identical to the merged crate's export, so e5a4ac5978462156, 7c54302b487340a1, a217c7f698880830 and 82b19cbde8557ea5 hold under master's recipe form, recheck 2, scratch 7, spec_readback 2); spec-constants 28 rows agreeing; identity grep 0 hits. Carried since 61588347: main's sentence at nine of nine on AP-F8-6, section 14 and spec 1.4.7.2; the 61-row era reading and the class v5 attempts census on the spec, the page and the ledger; AP-F8-3; spec 1.4.7 and 1.8.6 with the constants and id tables; the AMD fingerprint row; the kits branch and master merged; two corrections the proofs found: master's program_id_derivation text lacked the class v5 rung-0 arm (the v5 packs' text named the class recipe while the id was the plain form; the arm added to the TEXT, re-exported, ids unchanged; a post-freeze change on the class-v5 line, so 0.3.25's pairing, never 1c420786's), and the public-export scrub (the founder's name six times on the page, the zone name in three files; gone). Incoming to the page: the Arc fingerprint, F9 and F1. THE MOVE FILE NOT PUBLISHED (the shipper, 01:41 BST): build-1's /fleet/move.json still names commit 2720d8d2 with the 22:30 BST minute; no FETCHED count, no named minute; the fleet lane (ac055d60427caab99) has answered nothing since its 22:4x report (asks at 01:05, 01:16 and 01:41; its task output last written 22:21 BST, its last action a hand read of dn3-g1's proven share), the second dark lane beside the build-server lane (last written 22:36 BST). So 02:00 BST cannot hold; the 02:53 BST ceiling (DAA 32,400) stands only if a signed move file lands at once and the 34 pullers fetch inside forty minutes; main has the clock line with the two options (wake or replace the fleet lane; or a fourth re-cut from a morning minute, the Mac entry standing down with it). The publish record's shape stands: the Mac entry at the minute (staged, DMG 1aa301cc, both folders, armed); the hive and the Windows pairs on main's word; the pairing 1c420786, 091a0758 0.3.25's. Every other gate on dfbd1e10 green and recorded. THE RUNG-0 ARM CONFIRMED (the v5 lane, 01:4x UK): 987e90e8 touches only Program::program_id_derivation, the text in program.json; Program::program_id untouched (the v5 rung-0 plain-form branch since the freeze); the crate at 091a0758 and 1b5684ec (master 35602b30 merged, pushed 01:41 UK) derives every pinned id byte for byte (packs 20 on box 2 comparing all three pinned packs' files including program_id and leaves.bin; spec_readback 2); the shipper told 091a0758 and 1b5684ec are 0.3.25's pairing, 0.3.24 on 1c420786. THE SM-SPARSE JOB (run-ca4-pc1-ca4sparse-5090-20261007, exit 0 at 00:41:53Z, 1,171 s, the 5090 alone, every fingerprint matched, the Power Helper answering every command on the padded write, the card left unlocked at 2,855 MHz): the SM-sparse reading does NOT exist; the research lane's worker ran its base kernel on every variant row (its race line "race 0 ms variant base" on all 48 rows, no NVRTC compile text), so --bench never honoured --variant sp-w32; the sparse rows equal base in rate and drift in watts with the card's heat only; the rerun waits on the research lane's exe honouring the flag. What stands: a repeat of the efficiency pass at two states, 32 s rows, the card alone: v4 unlocked 137.07 MH/s at 465.5 W (0.294 MH/W), at 1,300 MHz 134.26 at 309.9 W (0.433; 155.6 W back for 2.05 percent of rate); v3 unlocked 136.71 at 331.6 W (0.412), at 1,300 134.03 at 219.4 W (0.611; 112.2 W back for 1.97 percent); the v4 premium 133.9 W unlocked, 90.5 W at the knee; the three power fields agree within 0.2 W on every row (power.draw = instant = average on driver 617.14), which settles the field question on PC 1's side and leaves the 5080's 110 W gap to the fleet's rented card's sampler. Next on the shipper's ack: the 5080 full grid (-d) through the cleared helper sequence, the third 5090 pass, the microbench, the seven packs, the two tunes, the hot-table ldcs rows (kit and job at 292fcc75). THE --variant FAULT FIXED (the research lane, counter-asic-4, UTC clocks on 8 October): 00:44 the fix (a --bench with --variant runs the pinned race and installs the named kernel; the RESULT line carries variant=, sparse_blocks=, block_warps=; a served kernel other than the requested one prints variant_not_installed); 00:46 the known-failed test on build-1 against the real class v4 pack, no card (base: race off, 524,288 blocks of 32, "variant base"; sp43-w32: race on, 43 sparse blocks of 32 warps, the rewritten kernel with the nonces argument and the unit function, 43 blocks of 1,024; PASS; before the fix both read the base shape); 00:46 the Windows exe igneum-worker-cuda-ca4sparse3.exe sha256 0ba97edcd5c46a302a7ff5ddd1bbb1e493ca15f64d0757820ed645972df3bb56, mingw exit 0; the commit after 2d0013d1; the hash lane has the sha, the test's lines and the rerun's job shape (the same 48 rows, the race line per row); the op-mix re-weight stays behind the SM-sparse reading, the served 3.4x standing; the clean efficiency repeat in the file's 20.3a (6.6 pJ per counted op). THE SPEC'S LAST CRATE-DEPENDENT SENTENCE CLOSED (the site audit lane, master 56eebc0d at 01:49 BST, gate GREEN on c2c92eab, 71 checks; spec_readback now 3 tests): 1.4.6.4 states dataset_elem in full (the eight operations, the three constants, 32-bit wrapping) with two pinned vectors (dataset_elem(0x00000fed, 0x9E3779B9, 0x7F4A7C15) = 0x5c7dabd2; dataset_elem(0x0fffffff, 0, 0) = 0x7662c1ec) that spec_readback.rs reads from the text and checks against the crate, so part (c) computes from the text alone (34845c47); 1.4.6.5 names the class v2 figures as class v2's and carries the shipped rule's own census sentence (20,000 seeds, 68.1 percent rejected per candidate, the per-part shares, mean attempt 2.1, max 28, 0 exhaustions, 2e-43). The text-derived re-run on this text is the proof it is sufficient end to end (asked of adv-accept-3). THE MOVE FILE STAGED (the shipper, 01:5x BST): id mdfbd-1, commit dfbd1e10, want_digest b1ba7822, both pair slots on build-1's served tarball dfbd1e10-node-lane.tgz (e59ed0e6), at_epoch 0, signed with the fleet key on the Mac and verified against the fleet's public key in the puller's namespace; the read-back on placing it: the served file's id by curl and the first FETCHED on the relay intake; the 34 pullers fetch inside their one-minute timers (27 MB from build-1), the last FETCHED about five minutes after the file, the earliest minute ten after that. THE REAL LATEST-PUBLISH CLOCK: the file alone halts every miner on the restart, because each box's pack gate PAIR_MINER_SHA16 lacks aa8c2978 and the puller does not carry the file's miner sha into the restart environment; so route (A) also needs one ssh line on each of the 34 boxes before the minute with the fleet's tooling (the fleet lane's, or the shipper's on main's word). Absent main's word by 02:15 BST the shipper stands the Mac entry down under the ceiling rule (no app alone on b1ba7822) and 0.3.24 becomes a morning minute with a fourth re-cut. ROUTE (A) STAGED TO ONE COMMAND (the shipper, 01:5x BST): the gate script r0324/move/pair-gate-aa8c2978.py in its scratch (dry run by default, apply on the literal argument, the fleet's own Box helper and label list, nothing restarted); the dry run read 33 of 35 boxes, every one carrying the old gate list with fb147dd1 last and aa8c2978 absent, no env-last override; unreachable dn3-relay and p2-4090-1b (dead Vast proxies; they fall off at the move and rejoin by the pull); the apply about 90 s for the 33 with each gate read back and counted. THE F9/F1 INTERIM (the attack-pass lane, read at 01:5x BST): 71,292 seeds, 0 exhausted, 0 panics, max attempt 30; F1 0 failures at 2 h 23 min; the move's gate reads clear. On main's (A): apply 02:00, the file placed 02:02, the last FETCHED about 02:05, the minute 02:15 BST; main has the clock. Nothing applies before the word. THE SPEC TEXT SUFFICIENT END TO END (adv-accept-3 Q4d, 01:52 to 01:57 BST on build-2 at 16 cores; report section 6.6 on build/adv-accept-3, log 984-textderive-56eebc0d.tsv, every row equal to its Q4c row): the spec text at master 56eebc0d, implemented with nothing from the crate (text.rs: 0 igneum_pow imports; dataset_elem from 1.4.6.4, its two pinned vectors checked at start), reproduces the same 400 class v4 epoch programs as the code with 0 of 400 differences on every field; no sentence of the generator or acceptance sections needs the crate; the documentary finding (AP-F8-4, AP-F8-5) closed in full on two measurements; the lane at its end, 3.35 box-hours in all. F9 AND F1 AT 00:59Z (class v5 at 1c420786, pairing e5a4ac5978462156, build-1): F9 73,691 of 100,000 chain-shaped seeds written, 0 exhausted, 0 panics, 0 past attempt 31, max attempt 30; the attempt histogram 23,119 / 15,981 / 10,805 / 7,547 / 5,181 / 3,415 / 2,439 / 1,653 / 1,119 / 744 / 529 / 389 / 258 / 152 / 113 / 72 / 54 / 40 / 31 / 14 / 15 / 5 / 2 / 6 / 2 / 4 / 1 at 26 / 1 at 30, r about 0.69; the 10^5 about 01:30Z (02:30 BST). F1: the 10^5 redundancy census at 2 h 28 min under its lease with no end marker (18 minutes on an idle box; under tonight's load no minute named); its panic path live and empty, 0 failures the honest reading. Both land as record lines, then the board's close per item on sub-version 3 and class v5. AP-F8-5 ON TWO MEASUREMENTS (the site audit lane, commit 116e6055, master 5c77a7ac at 02:05 BST, gate GREEN 71 checks): the row carries Q4c (8b834634, 0 of 400 with one crate function, section 6.5, log 983) and Q4d (56eebc0d, 0 of 400 with no crate import, section 6.6, log 984); the public ledger and the ledger page regenerated; nothing open in the spec or the ledger on the audit lane's side. THE 5080 FULL GRID (run-ca3-pc1-v4-eff-5080-20261007-d, exit 0 at 01:54:00Z, 4,118 s; PC 1's dock card alone, driver 617.14, app 0.3.20, mem 14,801 MHz throughout; every lock through the cleared helper sequence, every command answered first time, every fingerprint matched, clocks reset and read back): the knee as a reading: the rate holds within 0.3 percent of unlocked down to 1,000 MHz on both classes (v4 71.19 of 71.41 MH/s; v3 71.11 of 71.28) and falls 5.2 percent at 900 MHz on v4 (67.66), where the 75-minute budget ended the grid (v3's 900 and below not taken; the drift check skipped); so the 5080's knee sits between 1,000 and 900 MHz, a third of its 2,963 MHz boost, lower than the 5090's 1,300 (84 SMs at 2,960 MHz have more compute headroom per unit of its 960 GB/s than the 5090's 170 SMs per unit of 1,792 GB/s; the memory wait hides the shadow down to a lower clock). Best MH per watt within the 1 percent rate tolerance: v4 at 1,100 MHz, 71.20 MH/s at 146.6 W (0.486 MH/W; 106.5 W recovered for 0.29 percent of rate); v3 at 1,000 MHz, 71.11 at 103.7 W (0.686; 66.0 W for 0.25 percent). The v4 premium 83.4 W unlocked (253.1 against 169.7), 41 W at the best points (146.6 against 105.6 at 1,100). Per tier: a 5080 owner on class v4 locked near 1,100 MHz draws 147 W instead of 253 for 0.3 percent less rate (MH/W up 72 percent) and the shadow's residual cost is 41 W. Rows (lock: v4 MH/s / W / MH/W ; v3): unlocked 71.41/253.1/0.282 ; 71.28/169.7/0.420 (sm 2,963/2,977); 2850 71.41/229.5/0.311 ; 71.29/155.3/0.459; 2700 71.41/209.6/0.341 ; 71.29/149.2/0.478; 2550 71.41/193.0/0.370 ; 71.29/134.4/0.531; 2400 71.41/176.0/0.406 ; 71.29/128.7/0.554; 2250 71.41/165.6/0.431 ; 71.28/117.3/0.608; 2100 71.38/157.7/0.453 ; 71.28/112.3/0.635; 1950 71.37/154.0/0.463 ; 71.26/111.6/0.639; 1800 71.35/150.3/0.475 ; 71.24/113.4/0.628; 1650 71.33/151.4/0.471 ; 71.22/109.7/0.649; 1500 71.30/149.2/0.478 ; 71.19/110.6/0.644; 1400 71.27/149.6/0.476 ; 71.16/107.0/0.665; 1300 71.24/147.9/0.482 ; 71.14/107.7/0.661; 1200 71.20/149.4/0.477 ; 71.12/104.4/0.681; 1100 71.20/146.6/0.486 ; 71.11/105.6/0.673; 1000 71.19/149.0/0.478 ; 71.11/103.7/0.686; 900 67.66/137.8/0.491 ; not taken. Throttle reason 0x400 (the power governor) on every row, never the clock lock, so the draw floor of about 147 W (v4) and 104 W (v3) from 1,500 MHz down is the memory system plus idle, not the SMs: the clock lever is spent by 1,500 MHz on this card. The three power fields agree within 0.2 W on every row. The site audit lane has the knee and best points for row 17; the bench table's 5080 row takes "71.4 stock (71.2 tuned)", "146.6 tuned (253 stock)", class v4 cost "+83 W unlocked, +41 W at the best points", hive core 1100 (the mem clock unchanged) once the fleet's rented-5080 sampler question is closed. Next on the shipper's ack: the third 5090 pass, the SM-sparse rerun on the fixed exe, the microbench, the packs, the two tunes, the hot table. THE NIGHT'S MOVE OUTCOME (the shipper, 02:58 BST): main's word on (A), (A') or (B) did not come (asked 01:41, 01:50, 01:53, 01:56 by the shipper and 01:42, 01:52, 01:5x, 02:00 by the coordinator); the gate script not applied (the dry run's 33 of 35 the only read); the move file not placed (build-1's /fleet/move.json serves m2720-1, 2720d8d2, the 22:30 minute, by curl at 02:56); no move minute; the stand-down under the ceiling rule holds from 02:15 (the shipper's stand-down line at 02:15 was not sent, its miss, the state unchanged); the Mac entry standing, not published (staged on DMG 1aa301cc in both folders, the live manifest at 0.3.23). A FINDING: build-1's Devnet 3 seed (the process on 26631 with JSON RPC 27632, the node lane's DAA reader) is DOWN (no such process; node1-dn3 26671 and the observer 26651 run on 2720d8d2; the node lane's 0.3.24 reader on 28690 runs but answers no DAA by the envelope tried), so the node lane's DAA reads since 25,169 at 00:52:38 BST may have stopped with it; at 1.0 DAA/s the DAA passed 32,400 at about 02:53 BST, the 39,600 floor is lost, and the fourth re-cut is from a morning minute main names (before 12:50 BST, or the three heights move with the floor). Every Devnet 3 node is on the 0.3.23 pin 2720d8d2, digest ba75bf6f (the 22:30 move; dn3-j1 behind its proxy unverified since); nothing of 0.3.24 is on any box or in any manifest. The night's 0.3.24: every gate green on dfbd1e10, the kit on four platforms, the move unmade for want of one word and two dark lanes. THE ATTACK-PASS BOARD'S CLOSE (lane (d), 01:58Z on 8 October; record docs/analysis/attack-pass-2026-10.md on the mirror's attack-pass; box-hours approximate: build-2 about 7 h, build-1 about 9 h plus about 6 h of F6 batches and F2 solvers earlier in the day). F9 so far: 89,301 of 100,000 chain-shaped seeds, 0 exhausted, 0 panics, 0 past attempt 31, max 30 (the tail 20: 20, 21: 6, 22: 6, 23: 9, 24: 3, 25: 4, 26: 2, 27: 1, 29: 1, 30: 1; r about 0.69), three chunks on their cores to about 02:20Z; F1 the 10^5 redundancy census at 3 h 22 min on 17 threads, healthy, no end marker, 0 failures on its live panic path. The board: F1 shadow redundancy PASS on sub-version 3 (max 5.078 percent at honest-compiler parity; AP-F1-1 on the v5 list at 3.0 percent), running on v5; F2 mixer round margin PASS effort-bounded (no trail under weight 20 to 24 at 2 applications, 29 to 35 at 3, 39 to 47 at 4), not re-run on v5 (the mixer unchanged); F3 chained cache j+1 PASS, not re-run; F4 weak-day census PASS on v4 on the DSP-bound metric with AP-F4-1 reconciled with adv-mixer-2 (median 226, 15 days a century, worst 2050-04-28 at 1.113x), on v5 PASS at 8ca66afa (0 of 2^24 days over 1.1x on both metrics, AP-F4-1 FIXED-AND-PASSED); F5 chip-model sweep FIXED-AND-PASSED (the F2 hour skipped by decision), not re-run; F6 verifier worst case PASS (worst of 10^5 at 8.708 ms half-core; O-1.14 closed, i7-9700K 6.334 ms), not re-run; F7 era draw PASS on all three (0 of 6 re-rolls), not re-run; F8 uniformity FIXED-AND-PASSED on sub-version 3 (60 of 64 under 1.2x; AP-F8-1, 2, 3 closed), PASS on v5 (61 of 64, worst 1.50x, the residue p4, p8, p10; p34 under); F9 edges, hot set, grinding PASS on sub-version 3 (34 of 105,064 edges bounded; grinding +0.004 percent), the exhaustion count running on v5; F10 ladder signal PASS, not re-run (node rule). Findings of the pass, all in-house: AP-F1-1, AP-F4-1, AP-F5-1 (the X9), AP-F8-1, AP-F8-2, AP-F8-3; two operating hazards fixed (AP-H1 the box clean, AP-H2 the shared binary path). The open tail (p4, p8, p10, and p34 on sub-version 3) is named in the public report; no outside party holds it (the attack-pass lane's close wrote "disclosed to the firms", stale wording from before the in-house ruling; its record file is to say "named in the public report"). THE SEED'S DEATH AND THE DAA NOW (the node lane, 03:0x BST): build-1's Devnet 3 seed log /home/build/dn3seed.log ends at 01:09:05Z at DAA 29,732 mid-stream with no stop, shutdown or panic line, so it was killed abruptly (it ran under nohup from a shell, not a unit; no journal names the killer; the OOM record needs sudo the lane lacks); its datadir /home/build/dn3seed/igneum-devnet-3/datadir is intact (13 GB) and it stays down until the shipper says; the lane's reads 25,169 at 23:52:38Z and 28,906 at 00:55:09Z came from it while it lived. The DAA now from node1-dn3 on 28670: 32,659 at 01:57:50Z (the observer 32,660), both on 2720d8d2; the chain passed 32,400 at about 01:53Z, 39,600 lost. The fourth cut in one line: the script on release-0.3.24-node reads the DAA from 28670, sets the floor to the morning minute's publish DAA plus 7,200 rounded up to the next 3,600, commits, pushes both mirrors and dispatches the gate set (about 20 minutes to the pin line, then the fast-time pair about 14); the latest minute before the three heights move with the floor is about 11:50Z (12:50 BST), where the floor reaches 79,200; nothing is cut until main names the minute. A morning item for the box owner: a process on build-1 was killed at 01:09:05Z without a log line while the box carried a load of 400 to 600; the killer (OOM or a sweep's cleanup) is to be read from the journal with sudo before anything long-lived runs there again under nohup. THE BENCH LOG ENTRY (the hash lane): docs/bench-log.md "7 to 8 October 2026, the class v4 efficiency passes: the core clock lock on the RTX 5090 and the RTX 5080" (both cards' full tables, the knee per card, the best MH per watt points, the premiums at the lock, the lever's limits, the job ids and clocks, the rented-5080 watts note) on the mirror's master as merge 773b93a8 at 02:04:47Z (commit 11c698ad); the audit lane writes row 17's sentence from it. PC 1: the third 5090 pass run-ca3-pc1-v4-eff-5090-floor2-20261007 (1,100 MHz down to 300) since 01:57:03Z, about 28 minutes; then the SM-sparse rerun. ROW 17 AND THE 5080 BENCH ROW (the site audit lane, master 2c5c7f52 at 03:19 BST, gate GREEN on 6eb6fd9b, 71 checks): docs/evidence.md row 17 carries both cards' efficiency passes from the bench-log entry (the 5090's knee, best points and premium; the 5080's 71.41 MH/s at 253.1 W unlocked, 71.20 at 146.6 W at 1,100 MHz, v3 at 1,000 MHz 103.7 W, the premium 83.4 W to 41 W, the knee between 1,000 and 900 MHz, the per-tier reading, the Ember Tune lever), a what-moved table for 8 October, /evidence rebuilt (865a0a5e); site/miner-bench.json's RTX 5080 row states the team's pass as the card's figure ("71.4 stock (71.2 tuned)", "146.6 tuned (253 stock)", "+83 W unlocked, +41 W at the best points", hive core 1100 with the memory stock, driver 617.14, the bench-log entry as the source) and keeps the rented-fleet sampler reading with its 110 W gap as the open question; /miners rebuilt at 35 rows (6eb6fd9b); 0 identity hits; nothing deployed, the deploy the morning hand-off. The design pass on ca3-coord (015cc839) now sits behind this master and rebases onto it before its own landing on main's word. THE DESIGN PASS REBASED (the coordinator, 03:2x BST): ca3-coord rebased onto master 2c5c7f52 as the three site commits only (f5b7140c the design pass, 8cc4cbc6 the phone grid, 9ad3fdc9 the six-column row; the two commits already landed through the record branch skipped), site/miners.html rebuilt at each from the merged miner-bench.json so the page carries the 5080's new row ("71.4 stock (71.2 tuned)") under the design; the diff against master is build.mjs and miners.html only; pushed to the mirror (pre-push GREEN); it lands on main's word after the captures, one gate run. ADV-MIXER-3's LINE (read from its report at tip e02297ae, 03:18 BST): queue 17 finished on build-1 at 01:3x BST; Q2 single-bit avalanche at 2^27, k = 2 and 3 on day 20729: 0 holes, 0 cells beyond 6 sigma at band 0.00026, PASS (the k = 1 finding stands as the single-application diffusion); Q2b t-bit avalanche on day 20733 at 2^28: 0 cells beyond 6 sigma at band 0.00018, PASS (k = 2, 3, 4 on 20729 at 2^28 the same); Q3 at k = 8 NOT run (killed at 20:20 BST under the lease rule, not re-queued; k = 2 to 7 clean with 0 deterministic bits on both days), named partial; Q6 the day-20733 SAT ladder: k = 2 and 3 TIMEOUT at the one-hour cap, k = 4 on one build-2 core since 03:05 BST, its cap about 04:05; one pre-emption in its ledger (23:58 BST, 21 minutes of a 2^27 row lost, re-queued); box-hours about 3.0 wall-hours of sweep (build-1 1.9, build-2 1.1) plus about 4 single-core CaDiCaL hours, about 7 with the 20733 ladder. The pass's close with the per-lane table and totals at about 04:05 BST; section 13 on crypto-engage (docs only) merging the current master and going through the gate to the mirror's master so the record cites a master commit. Box 2 at 03:20: adv-accept 87 cores in four shards with three waiting, adv-mixer-3 one core; build-1 load 34, no adv lease. THE DESIGN PASS'S OVERLAP ON THE BOX (the CI steward, 03:33 BST): the 1440 and 390 dark captures of /miners from ca3-coord 9ad3fdc9 taken on build-2 under lease pool 4 (Playwright chromium 1194, the recorded feed; /srv/artefacts/captures/ca3-coord-9ad3fdc9/miners-1440-dark.png 1440 x 4280 and miners-390-dark.png 390 x 9779); the overlap sweep on the same checkout, 390 to 1600 px, light and dark: RED, 3 findings on the change itself: at 1280 px dark and 1600 px light and dark the date span in the lead cell's class v4 line is COVERED by the rate cell (4 of 5 sample points under td.big); 390 to 1024 pass. Cause: the branch's last gate ran on the Mac, which has no browser, so the sweep skipped and read GREEN; on the page the row rule's white-space:nowrap outranked the lead cell's normal by specificity, so the class v4 line ran under the rate cell from 1280 px up. FIXED at ca3-coord 2ca45001 (the lead cell's rule at the row rule's specificity, max-width 360 px, the class v4 line wrapping with overflow-wrap), rebuilt, pushed; the sweep and the captures re-run on the box before main's word. THE IN-HOUSE PASS'S PATH TO MASTER (the crypto lane, 03:2x BST): adv-accept's box-hours crossed 8 before 02:00 BST and sit near 10 (87 cores in four shards; it sweeps on under the mechanical yield, its reading unchanged); crypto-engage merged master 56eebc0d at 342b6730 (one conflict in funding.md, the pre-public scrub against the rewrite, resolved to the in-house pass with the scrub applied; the founder never named in in-house-pass.md or funding.md), the full gate running, merge-to-master on GREEN; section 13.3: master's igneum-pow moved after the freeze in four files (src/emit.rs and src/generator.rs, the derivation string and its recipe helpers, ids unchanged; tests/derivation.rs and tests/spec_readback.rs), none the hash, so the object the pass bounded is unchanged in every operation the hash performs. THE PASS IN ONE LINE (the crypto lane, 03:2x BST): eight of nine lanes closed, adv-mixer-3 on one SAT timeout (about 04:05 BST), adv-accept sweeping to its 16 box-hour line (9.2 now, the reading saturated at the 1.002x class), adv-cache-2 on one line shard; no break of class v4 sub-version 3; the acceptance's hot-set class closed by the class v5 floor (9 of 9) and its diffuse era-stride class routed to the next class; the weak-day FPGA tail reconciled and closed by a measured redraw rule; the attempts census complete; the spec text proven sufficient by two read-backs; one pod at USD 0.33 in the whole pass, none originated by the lane. THE THIRD 5090 PASS BELOW THE KNEE (run-ca3-pc1-v4-eff-5090-floor2-20261007, running at 02:34Z on its 500 MHz step; the steps lengthen as the rate falls since the batch count was sized from the unlocked rate, about 155 s at 500 against 60 at 1,100; the helper answering every command on the cleared sequence, every fingerprint matched, the 5090 alone). Rows (lock: v4 MH/s / W / MH/W ; v3): unlocked 137.09/456.7/0.300 ; 136.79/320.0/0.428 (sm 2,858/2,862); 1100 120.98/275.9/0.439 ; 117.32/198.6/0.591; 1000 110.03/254.9/0.432 ; 106.73/180.2/0.592; 900 97.43/232.7/0.419 ; 94.33/174.5/0.541; 800 86.00/216.3/0.398 ; 83.41/166.6/0.501; 700 75.98/202.7/0.375 ; 73.58/156.4/0.470; 600 65.30/178.2/0.366 ; 63.25/153.3/0.413; 500 53.03/166.5/0.319 ; v3 running. Reading: below the knee the rate falls about 10 percent per 100 MHz on both classes (compute-bound: the shadow and the base program no longer fit the memory wait) and MH per watt falls with it from 1,100 down, so the best point stays where the second pass put it (v4 at 1,200, v3 at 1,300); the driver took every lock down to 500 (the SM clock within 10 MHz), so the floor is below 500 MHz and is not where the optimum lives; the v4 premium below the knee 77 W at 1,100, 75 at 1,000, 58 at 900, 50 at 800, 46 at 700, 25 at 600 (the ALU work shrinking with the clock as the rate does). The exit line, the 400 and 300 rows, the drift check and the restore at its close; then the SM-sparse rerun on the fixed exe (each sparse row reading served= and sparse_blocks=, marked variant_row=FAILED if served as base). F9 AND F1 AT 02:34Z (class v5 at 1c420786, build-1): F9 98,945 of 100,000 seeds, 0 exhausted, 0 panics, 0 past attempt 31, max 30 (the tail 18: 39, 19: 19, 20: 24, 21: 8, 22: 6, 23: 9, 24: 3, 25: 4, 26: 2, 27: 1, 29: 1, 30: 1); the last three chunks within minutes of their ends; F1 at 4 h 02 min under its lease, no end marker, 0 on its panic path. The pass record's wording fixed on the mirror's attack-pass at 9474cea8 ("named in the public report"; no "firm", "firms", "escrow", "prize", "paid review" or "Lot" line in the pass record or the ten row records; identity grep 0 hits); the section's merge to master after the two record lines, through the full gate in a detached worktree. THE SECOND SWEEP ON THE DESIGN PASS (the CI steward on 2ca45001, 03:38 BST): the desktop widths pass; RED at 390 px dark only, three findings on the lead cell (the card name and the class v4 line covered by the rate cell), the cause the new 360 px max-width on the phone grid; FIXED at ca3-coord 5158276c (the lead-cell width rule scoped to widths above 1,100 px, the phone grid's lead cell with no max-width), rebuilt, pushed; the sweep and captures re-run on it. F9 PASS ON CLASS V5 (the attack-pass lane, class v5 at 1c420786, pairing e5a4ac5978462156, build-1 under lease pool class release, the last chunk written 02:34:54Z): 100,000 of 100,000 seeds drawn through the chain path (era-composed class), 0 exhausted, 0 panics, 0 past attempt 31, max attempt 30; histogram 0: 31,454, 1: 21,460, 2: 14,660, 3: 10,263, 4: 7,047, 5: 4,701, 6: 3,297, 7: 2,256, 8: 1,532, 9: 1,027, 10: 702, 11: 509, 12: 365, 13: 216, 14: 153, 15: 103, 16: 80, 17: 56, 18: 39, 19: 20, 20: 24, 21: 9, 22: 6, 23: 9, 24: 3, 25: 4, 26: 2, 27: 1, 29: 1, 30: 1 (first-draw acceptance 0.3145; the mean attempt index 2.185, so 3.185 draws per seed on average; 4,862 seeds, 4.86 percent, at index 8 or above and 255, 0.255 percent, at 16 or above; the 256-attempt cap and the deterministic last resort never reached; the lane's first line read 1.993, a slip it corrected); the exhaustion gate holds for the 0.3.24 move; record docs/analysis/attack-pass/f9-grind.md and the lane (d) section on the mirror's attack-pass. F1 still running (4 h 05 min, 16 cores, 0 on its panic path, no end marker). F9's record on the mirror's attack-pass at 2bcb7e08 (the lane (d) row and f9-grind.md section (d); feature gate GREEN); F1 the one open item before the lane (d) merge to master. THE DESIGN PASS GREEN ON THE BOX (the CI steward on ca3-coord 5158276c, 03:4x BST; build-2 under lease pool 4): the overlap sweep 390 to 1600 px, light and dark, GREEN, 0 findings (the known-failed fixture fired first); the 390 px capture byte-identical to 9ad3fdc9's (the phone shape that passed before), the desktop widths carrying the wrap at 4,640 px tall; the four dark whole-page captures on build-1 under /srv/artefacts/captures/ca3-coord-5158276c/: miners-390-dark.png (sha256 9eec8f27..., 509,158 bytes), miners-1280-dark.png (1b6e636d..., 438,541), miners-1440-dark.png (87387e14..., 445,402), miners-1600-dark.png (d53973cd..., 448,545); the run log /srv/builds/bs-ci-steward/cap-out/run-5158276c.log on build-2. The branch's gate record: a full gate on the Mac skips the sweep (no browser), so the box line is the sweep's verdict for 5158276c; the branch waits on main's word on the look and lands in one gate run. THE IN-HOUSE PASS'S RECORD ON MASTER (the crypto lane): crypto-engage dab0c89f (gate GREEN, 71 checks) landed through merge-to-master.sh --remote build at 03:50 BST as master 00b8cd1b: docs/plans/cryptanalysis/in-house-pass.md section 13 (the roll-up, every lane's reading, the frozen-object note) and funding.md's in-house row and brief, scrubbed under founder-strings-check.sh. AN EXCEPTION OWNED (03:39 to 03:50 BST): the lane's first merge call used the tool's default path, which reads CI on GitHub with gh run list; GitHub is suspended and the rule says never poll it; the tool polled 21 times (each 403, nothing pushed, nothing read); the run's process outlived the task stop and the lane ended it by its pid at 03:50 BST, then used --remote build; the breach is the tool's default against the rule and the lane's for not passing the switch; no state moved on GitHub's side. The coordinator's order on it: merge-to-master.sh's default remote must refuse GitHub while the suspension stands (the CI steward, a gate-side fix with a known-failed self-test), so the rule does not rest on every lane remembering the switch. THE THIRD 5090 PASS CLOSED BY ITS CAP (run-ca3-pc1-v4-eff-5090-floor2-20261007, ended by the 45-minute cap at 02:42:05Z during the 300 MHz step, exit -1, its own finally block never ran; every row taken matched its fingerprint, the 5090 alone): the 500 row's v3 side 51.37 MH/s at 136.4 W (0.377); 400: v4 42.62/152.5/0.280, v3 41.32/131.3/0.315 (sm 390); 300 not taken; no unlocked-end drift check; the driver took every lock down to 400 (the SM clock within 10 MHz), so the floor is at or below 400 MHz. The reading: below 1,300 the rate falls about 10 percent per 100 MHz on both classes and MH per watt falls from 1,100 down (v4 0.439 at 1,100 to 0.280 at 400; v3 0.592 at 1,000 to 0.315), so the optimum stays at the second pass's points (v4 1,200 MHz, v3 1,300) and nothing below 1,100 is worth the knob's time; the v4 premium below the knee shrinks with the clock (77 W at 1,100, 46 at 700, 21 at 400). AN EXCEPTION OWNED: the 5090 sat at the 400 lock (390 MHz, 127 W mining) for four minutes until run-ca3-pc1-clocks-restore-20261008 (02:45:20 to 02:46:30Z, exit 0) started the helper over an empty cmd.txt and sent rgc ("All done"), the card reading 2,880 MHz after; the cause the batch count per step sized from the unlocked rate, so the low steps ran 2.5x longer than planned; the fix in the scripts: the budget check ends the grid with the restore inside the cap, and a probe dev line answered in helper.log counts as the helper up when its heartbeat file stays stale (the restore answered at once with helper.alive stale past 60 s). THE SM-SPARSE RERUN: fetch-ca4-sparse3-exe-20261008 landed 02:49:57Z (sha256 0ba97edc...), run-ca4-pc1-ca4sparse-5090-20261008 published 02:51:15Z on the hash lane's own order (the shipper's acks were for the void host slot); each sparse row reads served= and sparse_blocks= and is marked variant_row=FAILED if served as base; the close about 03:15Z (04:15 BST). THE STEP-BUDGET FIX ON MASTER (the hash lane, merge 9fd8b1d8 at 03:02:03Z on 8 October, commit 0b00c42e, the full gate GREEN): the efficiency pass keeps four minutes of its cap for the restore (every step and lock guarded by the deadline minus four minutes) and sizes each step's batch count from the last rate read for the pack, so a 60 s step stays 60 s as the rate falls; a probe dev line answered in helper.log counts as the helper up when the heartbeat file stays stale (all four lock scripts); the gate check tools/ci/pc1-step-budget-check.sh with the known-failed case first (under the old rule a lengthening grid ends on the cap with no restore; under the new it ends with the restore at 1,500 s of 2,700), wired into pre-push.sh and checks.txt (74 checks). The 5080 Ember tune, the 9070 XT tune pass and the hot-table ldcs rows publish behind the SM-sparse rerun, the microbench and the packs. THE SM-SPARSE RERUN FAILS THE SAME WAY, NOW NAMED (run-ca4-pc1-ca4sparse-5090-20261008, the fixed exe ca4sparse3, started 02:52:48Z): every sparse row served=base sparse_blocks=0 variant_row=FAILED, the worker's own line "RESULT variant_not_installed requested=sp43-w32 served=base race=... variants 1 base only, no race (no other variant named)", no "compile:" text, so NVRTC never saw a rewritten kernel: the variant name is parsed into the request but never added to the race's variant table in this exe; the research lane's emulation test checked resolve and rewrite, not the race list the bench builds (a test of the wrong layer; the known-failed case must be the bench's own race line reading "variants 2"). The rows are base runs; no reading. The queue goes on: the microbench at the rerun's exit (about 03:15Z), the seven packs, the 5080 Ember tune, the 9070 XT tune pass, the hot-table ldcs rows; the SM-sparse question's fourth row stays with the research lane, an exe whose card-free check shows "variants 2" in its race line getting the slot within the minute. CLASS-V5'S F9 ROW PUSHED (the v5 lane, class-v5 1d5e5d23 on both mirrors at 04:04 UK): the page's F9 row (100,000 seeds, 0 exhausted, max index 30, first-draw acceptance 0.3145, mean index 2.185, F9 PASS, the record file named), F1 stated as running with 0 failures (its own commit to follow), the Intel row not measured tonight; master merged twice (2c5c7f52 gated at 5f5e0a5c, full gate GREEN 71 checks at 03:45 UK; 9fd8b1d8 auto-merged and pushed on the hook's light gate, the full gate running on 1d5e5d23); the generated ledger files and the spec-constants check clean on the tree. THE THIRD --variant FIX (the research lane, 03:04Z on build-1 under lease, with the hash lane): the cause of the 02:52Z rows: the race's push looked the pinned name up in the empty order list through the variant lookup, whose on-demand sp path answers for any list, so the sparse variant was "found" and never pushed; the order is now a pure function with membership by name; --list-race prints, with no device, the race order the worker's own option handling builds and whether the rewrite applies: with the job's exact flags "variants=2 names=base,sp43-w32" and "sparse_blocks=43 block_warps=32 rewrite=applied bytes=22261 nonces_arg=1 unit_fn=1" (before the fix variants=1); exe igneum-worker-cuda-ca4sparse4.exe sha256 84846396559004a8df61881c15ecb42fa3fc1010ad99074e0c0b53e81bb1ca3b, the commit on the mirror after 7e9d52a6; the third rerun on the hash lane's queue at the next slot; the two failed runs stay the night's SM-sparse state, the op-mix re-weight held, the served 3.4x standing. THE GITHUB GUARD ON MASTER (the CI steward, tip 2f702735 at 04:05 UK; merges 53773860 and 2f702735, full gate GREEN 71 checks each): fa7e98fe adds the tracked marker tools/ci/github-suspended (suspended-since 2026-10-07T17:02:00Z, removed by main at the cut-over) and two refusals: merge-to-master.sh refuses a GitHub remote (origin by default, or any remote whose URL carries github.com) with one line naming the switch and exit 2 before any gh or git call; the pre-push hook refuses any push to a GitHub remote the same way (the hook reads the remote URL, so a bare git push origin is refused too); known-failed first in both self-tests; the live read on the Mac: merge-to-master.sh --remote origin exits 2, nothing contacted; two follow-ups (9484b988, a08423d4) fix the tool's own --self-test under the real marker. The rule no longer rests on any lane remembering the switch. F1 READ AT 03:05:58Z (the attack-pass lane; the census process itself, not the lease wrapper): state S with 17 threads, 15 cores busy over 45 s, 2 d 19 h of CPU banked over 4 h 30 min of wall, RSS 0.8 to 1.0 GB; computing, not hung. No rows can exist before the end: the harness collects every Report in memory under thread::scope and writes census.csv in one go at the end (no progress print), named as a harness gap in the record. Why fifteenfold against the v4 reference: under class v5 every candidate draw runs the (c''') distinct-index floor over 2^20 (about 1.8 core-s per candidate under the night's load, times 3.2 draws per program, about 5.8 core-s per program before the analysis), so 10^5 programs at 15 busy cores is about 10.7 h of wall, the end about 09:00Z (10:00 BST), nearer the early side as the load fell to 21. Ruling: not killed (a kill loses 4 h 30 min with nothing on disk); the lane (d) section merges to the mirror's master now with F9 and the F1 row reading "running, 03:06Z reading, projected end about 09:00Z", F1's record line in a second merge when it writes; the harness gains a progress line before its next 10^5 run. THE IN-HOUSE ADVERSARIAL PASS CLOSED (04:08 BST on 8 October; an internal adversarial pass, not an independent review; section 14 of in-house-pass.md at crypto-engage c099e818 landing on master through --remote build; every tip read from the mirror at 04:07 with igneum-pow identical to 017e7037 on all nine). Per lane (tip; box-hours; verdict; partial): adv-mixer d2ba3134, about 0.6 plus 1.8 single-core SAT hours, the algebraic structure BOUND, none; adv-mixer-2 2a632579, 0.31, BOUND for every chip, GPU and the verifier with the FPGA LUT-area FINDING (2^-10.8 of days, 15 a century, worst 2050-04-28 at 1.113x) closed by the measured redraw rule, none; adv-mixer-3 981bfff2, about 5.0 wall-hours plus 8 single-core SAT hours, Q1 BOUND (2^32 t uniform at k = 1 to 8, both days and 8 random days), Q2 and Q2b FINDING at k = 1 only and BOUND from 2 to 8 at 2^24 to 2^28, Q3 FINDING at k = 1 and BOUND 2 to 7, Q4 and Q5 BOUND from k = 1, Q6 SAT BOUND (k = 1 in 137 s, k = 2 to 4 timeout), the round margin 70 of 72 per item, partial Q3 at k = 8 not run, multi-bit masks and a MILP bound not attempted, GPU blocked; adv-cache 555c3e42, 0.55, the recompute shortcut BOUND on every row, none; adv-cache-2 91ca5ce1, about 2.25, the line census PASS at 2^35 + 3 x 2^33, the real programs PASS with the Devnet 3 site-0 FINDING, the diffuse era-stride class named (16 of 32 base programs biased under drawn eras against 2 of 32 under R = 29, 8 over 1.2x, worst 1.75x, under 0.1 percent of reads per site, 0 of 61 refused by the v5 floor, AP-F8-6), steering and the 16,384-day scan PASS, the window layer exact and the chip model's partial-store rows overstated up to 2.3x with the verdict unchanged, partial the line shard s2c waiting on build-1 since 23:09 BST; adv-cache-3 9452c0bf, 0.23, the chain-break or skip BOUND on every row with the pebbling optimum under the hold-every-k curve, none; adv-accept c8a98e46, about 9.2 at 03:25 BST running to its 16-hour line, the bypass FINDING confirmed and bounded (9 few-item hot sets in the tail of 408,067 accepted programs, 0 in 20 random, 1.002x at the largest; all 9 refused by the class v5 floor, 7 clean programs falsely refused among the 12 deepest, 3 mild residuals missed), the stand-in gap BOUND, distinguishers BOUND, the attempts census complete, partial the sweep at 408,067 of 10^6; adv-accept-2 92168536, about 9.0 core-hours and 0.3 pod-hours (the one pod), header grinding BOUND by card measurement (+0.09 percent on an A6000) and by tail (3e-7), one 0.1 percent repeat class for the rule's owners, none; adv-accept-3 7826d2b2, 3.3, exhaustion BOUND (P 1.0e-43), the last-resort path FINDING (correctness, unreachable; closed in class v5), steering BOUND (no property over 1.03x at 1 in 1e6 tries), the program id BOUND with the derivation-string FINDING (fixed on master and in the packs), determinism BOUND, the spec text proven sufficient by two read-backs, the era lever BOUND, partial the steering sweep at 975 of 10^5 full-rule seeds. Totals: about 30.4 box-hours of run across the nine lanes (lease waits excluded) plus about 9.8 single-core SAT hours; pod-hours 0.3 on one RunPod A6000, USD 0.33 in all, rented and destroyed by the fleet lane. The verdict: no lane broke the frozen object; the acceptance rule admits two residual classes of address concentration, both under 1.002x to a chip: the few-item hot sets, closed entire by the class v5 floor (9 of 9) at a 2.4 percent clean-rejection cost, and the diffuse era-stride excess the floor does not reach, routed to the next class with its lever; the weak-day FPGA tail reconciled and closed. Already changed by the pass: the derivation string in the shipped packs, spec 1.4.3 to 1.4.6 rewritten and proven text-sufficient, the chip model's partial-store and pebbling baselines corrected, the last-resort path flagged and closed in class v5. Still to come: adv-cache-2's s2c row and adv-accept's final count, appended when they land. CLASS-V5 GATED (the v5 lane): the full gate on 1d5e5d23 GREEN, 72 checks in 347 s (04:1x UK); class-v5 4a162aba on both mirrors at 04:12 UK with the page's F1 line stating the 04:06 reading (computing, not hung; census.csv only at its end; projected end about 10:00 UK); nothing of the lane's pending on a box or a watch. THE LANE (d) MERGE ON MASTER (the attack-pass lane, 399f8c4d at 03:16:35Z, 04:17 BST; attack-pass 4150f66d, full gate GREEN 45 checks on the branch): F9 PASS on 1c420786 (row and f9-grind.md section (d)), the F1 row as ruled (running, the 03:06Z reading, projected end about 09:00Z, 0 on its live panic path, the harness gap named), the in-house wording kept through a conflict with master's older copy, one founder-strings scrub the gate caught on the pass record (the attribution now "The founder's word"). The harness item: the progress line every 1,000 programs and the flushed partial census.csv (temp file and rename) committed on attack-v5-frozen at 18a9c04a, built on box 2, its known-failed test (a 4,000-program census killed by pid at the 2,000 line, 2,000 rows expected) running under lease pool class adv; the verdict and the push follow. THE SM-SPARSE QUESTION, THE THIRD RUN (run-ca4-pc1-ca4sparse-5090-20261008-b on ca4sparse4, 03:23:45 to 03:48:45Z, exit 0): the card-free check on the card's own exe listed the sparse variant (variants=2 names=base,sp43-w32, rewrite=applied), the race ran it, and NVRTC refused the rewritten kernel on every sparse row: "kernel_bound.cu(370): error: identifier "d" is undefined | igneum_hash_bound_unit(d, ou, baseNonc, mas, i, gid);" (the same for sp170, sp85, sp21, sp11), so the race installed base and every sparse row reads served=base variant_row=FAILED. The hash lane's reading to the research lane: the wrapper's call carries the kernel's parameter names cut by one character (d, ou, baseNonc, mas for ds, out, baseNonce, mask), which points at the rewrite's name capture against the PC's CRLF pack text (the Linux check reported a different byte count for the rewritten kernel): the first card test of the rewrite, the finding kept. The base rows a third repeat of the knee pass (v4 137.06 MH/s at 449.7 W unlocked, 134.23 at 301.4 W at 1,300; v3 136.79 at 329.8, 134.05 at 218.0), the card restored each time. The slot returns to the research lane on an exe whose card-free check compiles the rewritten text through nvrtc for sm_120 (on CRLF input). The queue: the microbench run-ca4-pc1-microbench-5090-20261007 since 03:52:14Z (20 probes of 60 s unlocked, then at the 1,300 lock; about 50 minutes), then the seven packs, the 5080 Ember tune, the 9070 XT tune pass, the hot-table ldcs rows. THE CLOSE'S MASTER COMMIT (the crypto lane, sent 04:55 BST for a 04:14 landing, the forty-minute gap its own): crypto-engage c099e818 (full gate GREEN, 71 checks) landed as the mirror's master 2882352c at 04:14:50 BST; the record cites the roll-up and every lane's reading at 00b8cd1b and the close (section 14) at 2882352c; further landings only for adv-accept's final count and adv-cache-2's s2c row. THE FOURTH --variant FIX (the research lane, 03:55Z on build-1 under lease): the cause was not the line endings: the rewrite's parameter capture wrote the substring length as end minus start where the last index needs plus one, so every argument lost its last character on any input; CRLF would have missed the anchors entirely; the rewrite now strips \r first (the same rewritten bytes from LF and CRLF, 22,266 on both) and the capture is right; the card-free check through NVRTC on LF and a CRLF copy, identical lines: variants=2 names=base,sp43-w32; rewrite=applied; call="igneum_hash_bound_unit(ds, out, baseNonce, mask, iw, gid)" params=6 args=6 names_match=1; nvrtc=libnvrtc.so.12 arch=sm_120 compiled=1 image_bytes=36256; the failed case the 03:23Z card line. Exe igneum-worker-cuda-ca4sparse5.exe sha256 a4550202b301faf22f5329c2ab4fa1c0aa6695dbdaf31c974f316dca2524d7d6, with the hash lane; the commit on the mirror after 3ac5d20a; the slot after the microbench and the packs. The three failures gave three repeats of the knee pass (the v4 premium 133.9 to 145.3 W unlocked, 90.5 W at 1,300 MHz) in the file's 20.3a. ADV-ACCEPT OFF BUILD-1 (04:5x BST, the coordinator's placement rule): adv-accept runs on to its 16-hour line (about 10:15 BST, 10.6 box-hours at 04:54, the reading saturated) in box 2's gaps under the mechanical yield, its build-1 shard ended at the frontier and its waiter withdrawn, so F1's census keeps build-1 (its 10:00 BST projection assumed load 21) until census.csv writes; adv-cache-2's four-minute s2c shard the one exception. Confirmed by lease status at 04:57 BST: build-1 holds F1 (release, 16 cores) and adv-cache-2's s2c (32 cores, its last shard) and nothing of adv-accept's; adv-accept's four holders and waiters on box 2, where the attack-pass lane's flush test waits at 1 free behind them (the same class, no yield case); the coordinator's placement rule: one adv-accept holder ends at its frontier for the flush test (a 4,000-program census, minutes), since adv-accept's reading is saturated and the harness fix gates the morning's F1 rerun class. Done at 04:59 BST: adv-accept's sweep-s05b ended at its frontier at 04:58:50 (46,460 rows kept) and the flush known-failed test took the 16 cores at 04:58:55; the shard re-queued behind it. ADV-CACHE-2 CLOSED (05:0x BST): its last shard s2c ran 04:56 to 04:59 on build-1 (PASS at 2^33 reads, control-level), so the line census totals 2^36 reads over 464 chain days with every statistic at the control's values; final box-hours 2.35 of run (0.08 a duplicate windows run by its build-1 drain, recorded), pod-hours 0; tip bfc3746c on build/adv-cache-2, igneum-pow identical to 017e7037; the biased-site class (AP-F8-6) and the window-layer pricing stand; section 14's row updated on crypto-engage, landing with adv-accept's final count. Eight of nine lanes at their end; adv-accept alone runs to its 16-hour line about 10:15 BST. THE CENSUS HARNESS'S PROGRESS LINE (the attack-pass lane, attack-v5-frozen 18a9c04a on the mirror): the attack-f1 census prints a progress line every 1,000 programs (count, elapsed, running failure count) and flushes a partial census.csv at the same cadence through a temp file and rename; the known-failed test on box 2 under lease pool class adv (binary 14180ef4...): a 4,000-program census killed by pid at the 2,000 line at 04:08:27Z (05:08 BST), census.csv holding exactly 2,000 rows, no tmp file, lease exit 143; PASS (the old harness's known fail zero rows); record f1-shadow.md section 12 on the mirror's attack-pass at c99f147f (riding the F1 record merge); a side reading: 1,000 programs per 286 s on 16 cores, about 4.6 core-s per program, confirming F1's build-1 projection of about 09:00Z (10:00 BST); the running 10^5 census stays on the old binary, every census after it on the new. F1 PASS ON CLASS V5 (the attack-pass lane; class v5 at 1c420786, pairing e5a4ac5978462156, build-1 under lease pool class release, 16 cores; census.csv written 04:20Z, 05:20 BST, after 20,774 s of census, 5 h 46 min, earlier than the 09:00Z projection as build-1 emptied): 100,000 of 100,000 programs through the string-seed draw with the (c''') floor; instructions saved min 0.000 percent, mean 0.623, max 4.688 (the worst seed attack-f1/95060: 6,912 to 6,588); chip-view ops saved mean 0.520, max 4.783; programs over 5 percent 0, over 10 percent 0; soundness: differential mismatches 0 of 100,000 (8 random states each), verifier mismatches 0 of 100,000; 0 panics; the histogram of saved in 0.5 percent bins from 0: 55,241, 20,597, 11,762, 9,851, 1,484, 656, 259, 133, 13, 4, 0, 0. Against the v4 10^5 (max 5.078, the AP-F1-1 letter miss): the v5 tip's worst program sits 0.39 points under the 5 percent letter and the top two bins are empty. F1 PASS on 1c420786 by the letter and at honest-compiler parity; the redundancy gate holds for the 0.3.24 move; AP-F1-1's v5 half FIXED-AND-PASSED at this count; record f1-shadow.md section 13 and the lane (d) row, merged to master next. The attack board on class v5 is complete: F4 PASS (8ca66afa), F8 PASS, F9 PASS, F1 PASS; the rest not re-run by rule. CLASS-V5'S F1 ROW (the v5 lane, class-v5 1095eaa8 on both mirrors at 05:24 UK): the page's attack row reads F8 PASS with the known residue, F4 PASS, F9 PASS, F1 PASS on the full 10^5, the rest not re-run by rule; the full gate running on 1095eaa8; nothing else of the lane's open tonight. THE CA4 PACKS ON THE 5090 (run-ca4-pc1-packs-5090-20261008-b, exit 0 at 04:22:54Z, 579 s; the 5090 alone through the installed worker, the lock and reset through the helper, every self-test PASS at both states): the int8 mma tile prototypes' inline PTX compiles under NVRTC 12.8 on sm_120 and matches the CPU reference (mm128 270e4ae36b37e9a1, mm512 a1c1ff3148d775d1, mm1430 8e9b7066239d35d1), as do both per-load exports (404cad3b3399f9b3, ee5d7c71180e5ea7), sh256x27 (3d2e8245cc084d07) and the mx8-genesis control (7c28cfb06c5c65a9). Rows (MH/s / W / MH/W), unlocked then at the 1,300 lock: mx8-genesis 137.54/311.0/0.442 then 127.32/213.0/0.598; sh256x27 137.51/462.2/0.298 then 126.93/295.8/0.429; shl256x27 (unsound, an energy reading only) 158.62/472.8 then 145.65/299.4; shl256x27_v2 (unsound) 135.90/448.3 then 126.04/282.9; mm128 137.45/332.9/0.413 then 127.01/217.8/0.583; mm512 137.50/369.4/0.372 then 127.07/235.4/0.540; mm1430 137.45/457.7/0.300 then 126.87/284.5/0.446. Consequences: the rate is memory-bound on every sound pack at both states (within 0.5 percent of the control); the tile premium over mx8 is 21.9 / 58.4 / 146.7 W unlocked for 128 / 512 / 1,430 tiles (0.103 W per tile, linear) and 4.8 / 22.4 / 71.5 W at the lock (0.050 W per tile), so at 1,430 tiles the tile block costs what the ALU shadow costs (151.2 W unlocked, 82.8 at the lock) and the lock halves it the same way; the first per-load export's 15 percent higher rate is its duplicate reads landing in L2 (the unsound construction), the fixed one 1.2 percent under the control. The research lane has the rows for 20.3 and 20.4; the tile class's premium per tile is now a measured number on the 5090 and its Apple cost (35 to 78 percent of rate) the open side. The microbench -b since 04:23:23Z, then the SM-sparse rerun on ca4sparse5, the 5080 Ember tune, the 9070 XT tune pass, the hot table. THE CA4 PROTOTYPES' FIRST SENTENCE ON MEASURED ROWS (the research lane, counter-asic-4 on the mirror after 1428dd3c; sections 20.3 and 20.4): neither prototype beats class v4's premium; the tile block matches it at the same hash rate (mm1430, 11,440 int8 tiles per hash: 146.7 W over class v3 against the ALU shadow's 151.2 W unlocked, 71.5 against 82.8 W at the 1,300 lock, the rate memory-bound within 0.5 percent) and beats class v4's chip edge only at the pessimistic end (about 2.2x against 3.5x), not at k = 1 (2.2x either way), because the 5090's measured cost per int8 MAC (0.091 pJ unlocked, 0.048 at the lock) sits inside what a 5 nm MAC array costs anyone (a claimed test-chip figure), so a chip's k on tile work is at or above about 1 where on ALU work a fixed datapath reaches 0.3 to 0.5; the per-load placement dead as a construction (its energy rows 13 to 14 W under the whole block for the same instructions; the first export 15 percent faster from duplicate reads served by L2). Against the tile block as a class: the verifier (AVX2 0.047 us per tile per unit; mm1430 10.14 ms with the sibling loaded on the box's core, a 0.14 ms miss of the gate; scalar 13x worse; NEON unwritten), the Apple tier (35 percent of rate at 1,024 tiles, 78 at 4,096), the AMD layout unverified. No served number moves; the SM-sparse reading still owed (three failed runs, the fourth exe queued after the microbench); the op-mix re-weight held, the served 3.4x standing. The k column's basis (the research lane, counter-asic-4 after 781cb395): the 1,430-tile point is the one chip-model-v3 5.11's tensor-tile k column was priced at (15.2 set R about 1,430 from the 4090's 0.056 pJ per MAC to carry the ALU shadow's 0.654 microjoules; 11,440 tiles per hash), and the 5090 reads 0.091 pJ per MAC unlocked and 0.048 at the 1,300 lock there, so the column (2.1x at k = 1, 1.6x at k = 1.5) has its GPU-side cost measured at the premium it was priced for (1.067 microjoules unlocked, 0.564 at the lock, against the ALU shadow's 1.10 and 0.652); the Apple cost the open side; nothing served moves. F1'S RECORD ON MASTER (the attack-pass lane, merge 54b896f3 at 04:29:30Z, 05:30 BST; attack-pass 0610892b, full gate GREEN on the branch, pushed on try 2 after a ref race): the F1 row (PASS, AP-F1-1 FIXED-AND-PASSED on v5 at 10^5), f1-shadow.md sections 12 (the flush and its known-failed test) and 13 (the 10^5 record with the worst four programs at 4.688, the attempt histogram, the v4 comparison). Lane (d) complete: F4 PASS (8ca66afa), F8 PASS (61 of 64 at 1c420786), F9 PASS (10^5 seeds, 0 exhausted), F1 PASS (10^5 programs, 0 over the letter, 0 mismatches); both 0.3.24 gate lines PASS on the full 10^5. Box-hours for the lane (d) tail: build-1 F9 ten chunks of 4 cores at about 14,480 s each (about 161 core-hours), F1 16 cores for 20,907 s (93 core-hours), F4 12 cores for 379 s; box 2 F8 64 seeds (the earlier record) and the flush test 16 cores for 3,352 s (15 core-hours, most queued); nothing of the lane's on either box. THE V5 LANE'S NIGHT CLOSED (05:3x UK): the full gate on class-v5 1095eaa8 GREEN, 72 checks in 345 s; the freeze 1c420786 (0.3.24's pairing), the post-freeze line through 1095eaa8 (0.3.25's: AP-F4-1's agreed form, the verified last resort, the record), every proof green on the tip, the attack board on class v5 at F8 PASS with the known residue and F4, F9 and F1 PASS, the kit's fingerprint equal on CUDA, Metal, Apple OpenCL and the RX 9070 XT, the Intel row not measured; nothing of the lane's pending. THE SM-SPARSE READING EXISTS (run-ca4-pc1-ca4sparse-5090-20261008-c on the research lane's fifth exe, exit 0 at 05:12:48Z, 2,219 s; every variant served on the card, served=sp-w32 with sparse_blocks=N, the rewritten kernel compiled under NVRTC on sm_120 and bit-exact, every fingerprint equal to the Mac's; the 5090 alone, the lock and resets through the helper, the drift check equal to the start): a quarter of the SMs (sp43-w32, 43 of 170) holds 98.2 percent of the class v4 rate at the SAME draw (134.58 MH/s at 460.1 W against base 137.07 at 450.8) and 99.8 percent of the class v3 rate at 4 W less (136.55 at 309.8 against 136.77 at 313.9); the draw falls only when the rate falls (sp21-w32: v4 70.75 MH/s at 327.4 W, v3 132.82 at 303.4; sp11-w32: v4 37.34 at 250.9, v3 100.14 at 274.5), and watts minus idle per MH/s never drops below base (v4 2.75 W per MH/s base, 2.87 at sp43, 3.58 at sp21, 4.74 at sp11; v3 1.75, 1.73, 1.73, 2.00); the persistent shape on the full card (sp170-w32) within noise of base; at the 1,300 lock the sparse shapes collapse (v4 sp43 64.3 MH/s at 208 W, compute-bound). CONSEQUENCE: the class v4 premium is the shadow's ALU work itself, not SM-count overhead (150 W at sp43 against 137 W on the full card), so an SM-sparse miner kernel saves nothing and the candidate is dead by the research lane's own rule; the op-mix re-weight stays the open lever, and its served candidate ("2.9x with a core three times better") now has its SM-sparse read: the premium does not move with the SM count, so the re-weight's case rests on the op mix alone and goes to main with that reading. The microbench -c since 05:13:41Z with the pack argument; then the 5080 Ember tune, the 9070 XT tune pass, the hot-table ldcs rows. RANK 2 CLOSED IN THE CA4 FILE (the research lane, 20.3b, counter-asic-4 on the mirror after 6b21e887): the SM-side power is the work's, not the SM count's (the shadow's ops cost the same on 43 SMs as on 170; idling SMs saves nothing); the number kept: the class v4 premium at sp43 unlocked 150.3 W over v3 at a held rate, equal to the full-card premium, so the premium is the ops' energy whatever carries them; the premium-free floor rests on the operating point alone; the op-mix re-weight's hold is main's to lift or keep, the SM-sparse reading saying nothing against it; the microbench rows still owed. THE OP-MIX RE-WEIGHT: HOLD (the research lane's case for main, 06:2x BST; the SM-sparse row at counter-asic-4 954c4053, section 20.3b): the served sentence stands ("At launch the strongest chip in our public model reaches 2.1x per joule against an RTX 5090 with a core as good as a GPU lane, 3.4x with one three times better, under class v4 from the first block"; the re-weight would move "3.4x" to about "2.9x", the shuffle-and-multiply-heavy shadow raising the chip's k floor from about 0.32 to 0.46). The basis: the re-weight touches only the pessimistic column, a model on both sides (the chip's k floor an estimate from wire and datapath figures, never measured; the GPU's energy per op by family unmeasured until the microbench rows land, the shfl, mul and arx probes being that measurement); the SM-sparse reading says nothing for or against it (the premium is the ops' energy, which both mixes pay); the night's measured finding on bounding k points to the int8 tile block (the same premium at the same rate with a k floor near 1 from the GPU's own tensor core, 0.048 to 0.091 pJ per MAC), of which an ALU re-weight is the weaker version at the same class-change cost (the 95 percent rule, the six gates, a new program stream, Apple paying shfl at 1.91x per op); a reader gains 0.5x on a modelled pessimistic bound and loses nothing measured from the hold; the 2.1x at k = 1 rests on four repeats of the knee pass (82.8 to 90.5 W at 1,300 MHz). The condition that re-opens it: the microbench reading the 5090's shfl and mul rows at or under the add's pJ per op together with a measured chip floor, and then it re-prices against the tile block, not the served line. Main's word lifts or keeps the hold; the coordinator's reading agrees with the hold. THE MICROBENCH ON THE 5090 (run-ca4-pc1-microbench-5090-20261008-c, exit 0 at 05:56:29Z, 2,484 s; the research lane's per-block micro-benchmark, 20 probes ran, 0 skipped or failed, at the unlocked clock and at the 1,300 lock, every probe's checksum equal at both states, the card back at the driver default). Picojoules per counted op as (watts minus the sleep row) over G ops per s, unlocked then at 1,300: the ARX integer path 11.3 then 6.2; int_mul 13.9 then 8.3; mulhi 39.6 then 21.0; prmt 22.3 then 11.5; lop3 24.1 then 13.0; shfl 55.8 then 29.4; fp32 fma 9.2 then 5.2; fp16x2 fma 5.1 then 2.6; int8 mma m8n8k16 4.1 then 2.2; int8 mma m16n8k32 1.36 then 0.83; fp16 mma 3.2 then 1.7; bf16 mma 2.9 then 1.5; fp8 e4m3 mma 1.5 then 0.8; the memory rows per read: L2 chase 2.4 nJ unlocked and 1.4 nJ locked, DRAM chase 10.9 nJ and 8.7 nJ, texture point 2.3 nJ, texture linear 0.19 nJ; the sleep floor 120 W unlocked against 75 W idle (the residency cost, flagged). CONSEQUENCES: (1) the op-mix re-weight's re-opening condition (the 5090's shfl and mul rows at or under the add's pJ per op) is NOT met and is now a measurement: shfl costs 4.9x the ARX op and mul 1.2x, mulhi 3.5x, so the GPU pays more for the heavier mix and the hold on the served 3.4x stands on measured rows, not a model; (2) the tensor-core int8 MAC costs eight times less per counted op than the ARX op the hash is built from (1.36 against 11.3 pJ), the direction a chip cannot beat by as much, which is the tile block's case restated in measured picojoules and the CA4 file's next row. The queue: run-ca3-pc1-ember-5080-20261007 (the installed app's Ember tune on the 5080, the app's own path, not elevated) since 05:57:18Z, about 30 minutes; then the 9070 XT tune pass and the hot-table ldcs rows. A CORRECTION FROM THE MICROBENCH'S TILE ROWS (the research lane, 07:0x BST; counter-asic-4 on the mirror after 954c4053: 15.1a, the corrected 20.3 and 20.4, the first sentence, the ranking): a mma.m8n8k16 tile is 1,024 multiply-adds per WARP, 32 per lane, so a hash does 32 MACs per tile, not 1,024; the lane's 15.2 and 20.3 and the 6 October 4090 figure chip-model-v3 5.11's tensor column was priced on were wrong by that factor. Corrected: the 5090's int8 MAC at the ALU shadow's premium costs 2.9 pJ unlocked and 1.5 pJ at the 1,300 lock (the packs job, 366,080 MACs per hash), the microbench's dependent u8 tile 4.1 and 2.2, the wide s8 m16n8k32 tile at 80 percent of peak 1.36 and 0.83; the 4090's "0.056 pJ per MAC" of new-pow 5.1 is 1.8 pJ. Against a 5 nm MAC array (0.04 to 0.4 pJ per INT8-class MAC, claimed) the chip's k on tile work is 0.03 to 0.3, BELOW the ALU shadow's 0.3 to 0.8: at the same premium the tile block leaves the chip 3.5x to 6.7x where the ALU shadow leaves it 2.1x to 3.5x. So the tensor shadow is the WORSE lever and rank 3 is dead; the 6 October verdict on scheme B stands for the right reason; the coordinator's 07:0x line to main calling the tensor side "the next class's one live direction" is withdrawn by this correction. Chip-model-v3 5.11's tensor column (its premise, a chip's MAC no cheaper than the GPU's, false by 4x to 30x on the public figures) and new-pow 5.1's per-MAC line are to be corrected (the coordinator's next commit); nothing served rests on either. The other rows, pJ per counted op unlocked then locked (the sleep floor 120 and 66 W subtracted; idle 75 and 60): int add-xor-rotate 11.3 / 6.2 (the shadow's 10.8 / 6.4 on the packs job: the two instruments agree); mul 13.9 / 8.3; mulhi 39.6 / 21; prmt 22.3 / 11.5; lop3 24.1 / 13.0; shuffle 55.8 / 29.4 (the card's dearest instruction, 5x the add: the re-weight's GPU side is against it, the hold measured); fp32 FMA 9.2 / 5.2; L2 hit 2.4 / 1.4 nJ per read against a chip's SRAM 0.2 to 0.5 (the hot-table lever dead on the GPU side; the ldcs rows kept as a record); the DRAM dependent read 10.9 / 8.7 nJ per read, the whole card's marginal against the chip memory's 2.0, section 2's floor seen per read. THE NIGHT'S CLOSING SENTENCE ON MEASURED ROWS: nothing on the 5090 reads k above 1; the ALU shadow at the operating point's knee is the floor, 2.1x at k = 1 for 82 to 90 W, measured four times; the two prototypes, the SM-sparse kernel, the hot table and the re-weight are all closed on measured rows. The CA4 file's commits (the research lane): 15.1a at 71fd465b (the microbench row, the residency cost 45 W at the stock clock before any instruction issues), 15.1b the commit after it (the re-weight's re-opening condition not met and measured; for 2.9x to be the honest pessimistic column a chip would have to pay 0.42 to 0.52 of the GPU's cost per shuffle, 22 to 28 pJ for a 32-lane crossbar move, above the wire figure and unmeasured; not a candidate on measured rows); the corrected 20.3, 20.4, the first sentence and the ranking at 71fd465b; the hot-table ldcs rows a record only. The lane closed for the night. THE TWO INTERNAL CORRECTIONS LANDED (the coordinator): chip-model-v3.md 5.11's k-column paragraph carries the dated correction (the tensor-tile column withdrawn; the shipped row unchanged) and docs/analysis/horizon/new-pow.md 5.1's per-MAC prose and the scheme B verdict carry the 32x correction with the reason (a tile is 1,024 multiply-adds per warp, 32 per lane), both citing counter-asic-4-research.md 15.1a at 71fd465b; new-pow's 5.1 table column and its 5.3 chip rows keep their original numbers under the note (the Horizon lane's file; a table rewrite is its own). THE 5080 EMBER TUNE (PC 1, app 0.3.20, 06:05Z, 07:05 UK; run-ca3-pc1-ember-5080-20261007): Tuned 60.3 MH/s at 123 W, 0.489 MH/W, clock_cap 2936, source=climb; read against the clock-lock grid, the app's power-limit climb lands at 0.489 MH/W where the 1,000 MHz lock gave 71.1 MH/s at 103.7 W (0.686), so the core-clock lock is worth +40 percent per watt on the 5080 over the stock climb (and 15 percent more rate): the case for the 0.3.24 core-clock knob shipping. The per-point curve rows were lost to a cast fault in the hash lane's curve line (job exit 1, 386 s; the app unaffected), fixed at 261d7c54. Live on PC 1: run-ca3-pc1-ember-9070-20261007 (the 9070 XT tune, 45-minute cap), then the hot-table ldcs rows. THE KNOB ON release-0.3.24 (the shipper, 07:1x BST): the core-clock knob 74585c91 cherry-picked onto release-0.3.24 at e181f497 with the efficient-point ceiling beside it (the plan-count test updated, b6e2845f; the app gate GREEN 294 + 35 + 8), the DMG re-cutting on it under the lock, the UI lane's drawing of the lock fields asked onto that tip, the measured Ember sentence in the 0.3.24 section with the job ids and the knee rule; the pin dfbd1e10 and the kit e6c088bb stand; the move on main's morning minute. THE 9070 XT EMBER TUNE (PC 1, app 0.3.20, 06:11Z, 07:11 UK): one row only, baseline 18.9 MH/s at 202 W, 0.093 MH/W, the chosen point "80%": the app has no knob on AMD in 0.3.20 (power_pct 0, clock_cap 0, limit 0.0 W), so the tune measures the stock point and stops; the 9070 XT cannot be made efficient by the app today, and at 0.093 MH/W it sits at a sixth of the 5090's locked 0.58 MH/W (the app's stored 5090 curve: 1,390 MHz, 118.6 MH/s at 204 W, 0.580) and a seventh of the 5080's locked 0.686; the AMD watts owed from the G1 ladder are on record from the app's reading, 202 W at 18.9 MH/s (the bench row's watts for the 9070 XT once the sampler question is closed). A morning item for the ledger and the app: an AMD core-clock knob (rocm-smi or ADL) is the only path to a 9070 XT efficiency figure. The job exited 1 on the hash lane's row count (fixed, 43f0918c); the app unaffected. The hot-table kit on PC 1 (fetch done 06:20Z); run-ca4-pc1-hot-ldcs-5090-20261008 publishing, the last PC 1 job on the list; rows when it closes. THE 9070 XT BENCH ROW ON MASTER (the site audit lane, ffb7d8ff at 07:35 BST, commit 47690be7, gate GREEN 72 checks): watts 202 ("202 stock"), mh_s 18.92 ("18.9 (18.8 to 19.2 on the G1 ladder)"), 0.093 MH/W, tuned "no lever: the app has no AMD knob today (an AMD core-clock knob through rocm-smi or ADL is the path, a morning item)", the class v4 cost unchanged (+2 percent of rate, 6 October), the note naming the app's own power reading at the stock point with the date and the status row, Hive values none; /miners rebuilt at 35 rows; no deploy; the audit lane closed for the night. The bench table's AMD watts are no longer owed. THE HOT-TABLE LDCS ROWS (the hash lane; the mirror's master at c09dfee4, 08:12 UK; bench-log entry "8 October 2026, the hot-table packs on the RTX 5090", 36 rows all PASS; run-ca4-pc1-hot-ldcs-5090-20261008b exit 0 in 1,372 s, clocks reset): ldcs equals base everywhere (a dead lever, no ldcs rows owed); the 1,300 MHz lock costs the hot packs 2 percent of rate against mx8's 7.5 while taking a third of the watts off every pack, so the hot family is latency-bound on the table; per watt at the lock hot64k8 reads 0.734 MH/W against the mx8 control's 0.602 (the control matches the v4 grid's 0.60, the two passes agreeing); the research lane has the rows with the resistance question (a cheaper GPU hash is a gain only if the saving sits in the memory path; the microbench's L2 row at 2.4 nJ against a chip's SRAM 0.2 to 0.5 answers it on the chip side). THE PC 1 LIST MAIN SET IS CLOSED: the 5080 full grid, the third 5090 pass, the SM-sparse reading, the two Ember tunes, the hot table, all on measured rows. Still open on the hash lane's side: PC 2's Arc B580 class v5 fingerprint on the shipper's clear (a Windows entry first), and the F8 tail p4/p8/p10/p34 as a Mac measurement under the lock script, held until main lifts the Mac rule for one job (a morning item). MAIN'S MORNING WORDS (09:3x BST on 8 October; the night's silence main's own, recorded as such): (1) the look: the design pass lands now through its gate (ca3-coord rebased onto master 715c79b2 as five site commits, tip 0d212a2a; the box sweep GREEN on the same content), the steward deploys master after it; (2) the floor sentence goes on evidence row 17 as well as /ledger in the exact wording (the audit lane's row); (3) CA4 parked with no live candidate, the record carrying the measured close; the only new work the AMD core-clock knob for the app, a 0.3.25 item on the update-return lane; (4) the F8 tail p4/p8/p10/p34 on the Mac: the Mac rule lifted for that one job, one at a time, a few minutes, the hash lane running it now; (5) the move: the shipper has route (A) with the minute 10:45 BST; the Arc B580 job has PC 2 clear and publishes now. THE BUILD-SERVER LANE'S HONEST STATE (09:31 BST): it ran nothing between 22:54 BST and 09:31 (its turn sat on a backgrounded gate chain; the overnight asks reached no tool call); the /miners captures it owed never ran (its export step failed at 22:52, "not a tar archive", a branch commit's git archive over ssh needing the ref fetched on the box side; the CI steward took the captures and the sweep instead); its last master-only deploy dde2dcd2 at 22:49 BST; it deploys master's tip on main's confirmed order after the design pass lands, and builds the 0.3.24 Windows pair and hive on the shipper's word. THE DEPLOY AND THE PAIRS (the build-server lane, 09:3x BST): a master-only deploy of 715c79b2 running from 09:32 with the checks after; master's tip deployed again when the design pass and the row-17 commit are on it, the served sha and minute to the record; the 0.3.24 seed, Windows and hive pairs built on the MORNING pin (the node lane's re-cut from the 10:45 minute) under lease class release, the hands pair the node lane's, the shipper keeping the move and the minute; the seed-class ship path proven on dfbd1e10 first so the morning pin's builds run clean. THE FOURTH CUT (the node lane, 08:33:18Z, both mirrors): 5b673577 on release-0.3.24-node = dfbd1e10 with program_class_v5_activation_daa 68,400 (epoch 19), nothing else, the three heights staying; the read from build-1's restarted seed on 27632 at DAA 56,329 at 08:33:18Z (1.0 DAA/s overnight); the publish DAA at 09:45Z about 60,630, plus 7,200 is 67,830, the next boundary 68,400, landing about 11:54:29Z (12:54 BST); the floor holds for a publish up to DAA 61,200 (about 09:54:29Z, 10:54 BST); the gate set running since 08:33:20Z (build and consensus at gate priority, the five suites, both canary sets, the fast-time pair about 14 minutes from the artefact), the pin line due about 08:52Z (09:52 BST); the crossing read from build-1's seed after the move (restarted on the pin in the shipper's move); the TESTNET_PARAMS v5-at-0 re-cut after a clean crossing. THE ARC B580 READ (the hash lane, PC 2, 08:35:59Z, 09:36 UK): no fingerprint, match False against 82b19cbde8557ea5; the kit worker fails its self-test on the Arc before any batch ("vector lanes 96 bad of 96 ... device 729ebd46376e2851 expected e552166a03298f7f" on the v5 pack) and 96 of 96 on the v4 control too (device 11bdacb6ee4108c2 expected dfbc8db1c06dacd8), every cache and dataset FNV matching; so the Arc's bound-kernel evaluation is wrong on Intel OpenCL, not class v5; the kit is good on five of six platforms; under main's rule the Intel kit holds out of 0.3.24 with the crossing time 09:36 UK for its page row. The open question, put to the shipper (PC 2 its now): whether the installed 0.3.21 worker's own self-test passes on the Arc with the devnet pack, which decides regression (the kit worker) against never-worked (every Arc rate row on record would then be a FAIL row and the bench table's Intel row a held row). The F8 tail job on the Mac started under the lock script, one seed at a time. THE DESIGN PASS ON MASTER (the coordinator, on main's word; merge 3a4ba893 at 09:39 BST): ca3-coord rebased onto 715c79b2 as five site commits (tip 0d212a2a: the design pass e2674675, the phone grid 592488a4, the six-column row 7c44354f, the lead cell's wrap c11baf30, the width rule scoped to desktop 0d212a2a), site/build.mjs and site/miners.html only, the page rebuilt at each commit so it carries the 5080 and 9070 XT rows under the design; the Mac's gate GREEN (the sweep skipped there), the box sweep GREEN on the same content at 5158276c with the four dark captures under /srv/artefacts/captures/ca3-coord-5158276c/; the build-server lane deploys master's tip after the audit lane's row 17 and Arc-note commit. THE MOVE'S READINGS (the shipper, 09:4x BST): the pin 5b673577's node-lane pair on build-1 (igneumd a3b1a2c9, igneum-miner cfa9f5ca, igneum-pow src 8 paths), its tarball served at fleet/5b673577-node-lane.tgz (c5b85b09, 27,495,480 B); the gate script carries cfa9f5ca and dry-ran at 32 of 35 reachable (dn3-pool-a destroyed by the fleet's waste pass, dn3-relay and p2-4090-1b behind dead proxies); the move file m5b67-1 written to take the pin line's digest and placed at at_epoch 0 the moment that line reads green (about 09:52 BST), the gate line applied in the same minute, the minute the last FETCHED plus ten (the founder's word: no waiting on the clock; 10:45 the ceiling, 10:54 the floor's); the Mac entry re-cut on the knob display (knob-24 2c4dc617 merged, app gate 294 + 35 + 8, UI 88) and published with the hive at the minute; the installed worker's self-test on the Arc with the Intel lane; the eight boxes on bc5945fe with miners off read by the fleet lane and taking the move with the rest. (The fleet lane is answering again this morning.) THE PIN LINE ON 5b673577 (the node lane; every gate green at 08:39:15Z, 09:39 BST): 5b673577 on release-0.3.24-node (both mirrors) = dfbd1e10 with program_class_v5_activation_daa 68,400 (epoch 19), nothing else; pairing igneum-pow 1c420786; build 08:34Z rc 0 at gate priority (igneumd a3b1a2c96a9767ee..., igneum-miner cfa9f5ca..., /srv/artefacts/0324-5b673577/node-lane); core 175, exec 47, miner 28, p2p-flows 38, pow 19, consensus 134 at gate priority; the Devnet 3 canary set (08:34:58Z to 08:36:38Z): digest cc9026909eddbadb46912513e9b748dffd8e5c3583cd976857a8afdab2d772f9 on igneum-devnet-3 from ba75bf6f, object version 6 stamped, the override file refused, shutdown 573 ms, two empty nodes handshaking on cc902690, the shared-devnet dialler rejected, a 2720d8d2 node refused both ways; the testnet canary b2e856ed unchanged. The floor from the seed's read: the publish DAA at 09:45Z about 60,630, the floor about 11:54:29Z (12:54 BST), holding for a publish up to DAA 61,200 (about 10:54 BST); the fast-time pair's SUMMARY due about 09:55 BST, inside 10:35; no slide to 72,000 needed. A correction: node1-dn3's 28670 no longer answers (its process gone), so the DAA reader is build-1's seed on 27632, restarted 02:00:09Z on the shipper's word and in step with the observer on 28650. dfbd1e10 void as a pin. THE F8 TAIL ON THE MAC, p4 (the hash lane, under the lock script, one seed at a time; the Mac rule lifted by main for the one job): p4 reads 1.2169x over the window model (the gate's 1.2167x reproduced), hot-set clear at every f, the attribution on one site: site 1 (instr 8, source r2, window 2^22 items, offset 1, the last base writer mad at instr 4) carries 1.448 percent of the hot reads against 0.107 flat, index entropy 13.74 of 14 bits, the largest 256-item bucket 4.5x its window expectation, every other site at its flat share; the hottest item 0x4000e7 at 355 reads with no predicted source (no saturation, no lossy writer), so the residue is a window-2 index with a quarter-bit short, not a lossy source; p8, p10 and p34 running (about 90 s each), the four rows and the record line (the bench log or AP-F8-1's tail paragraph) at the close. STANDING RULE FROM THE FOUNDER (09:5x BST on 8 October, after the night: "this cannot happen again"), three parts: (1) every ask any lane sends main carries a default action and a deadline; silence at the deadline means the default, never a stand-down; passed to every lane the coordinator runs; (2) the coordinator mirrors every deadline the shipper holds today (the pin, the apply, the move minute, the publish, the Windows chain, each floor ceiling): if the shipper has not acted within five minutes of its own clock the coordinator sends it the word and tells main; if it is silent for 25 minutes the coordinator takes its next action itself with the shipper's runbook and tells main; (3) a 20-minute heartbeat wakes main regardless of notifications. The night's cost the rule prices: three floors lost (28,800, 32,400, 39,600) and the Mac entry stood down for want of one word while every gate was green; two lanes dark for ten hours. THE MOVE FILE PLACED (the shipper, 09:42:14 BST): m5b67-1 (5b673577, digest cc9026909eddbadb, at_epoch 0, the node-lane tarball c5b85b09) placed and served, its signature verified against the fleet key; the gate line (cfa9f5ca into every reachable box's pack list) applying from 09:42; the minute the last FETCHED plus ten once the fast-time SUMMARY reads PASS (about 09:55); the Intel lane a0aa97b17380bd614 holds the Arc self-test question with the audit lane on its recipients. THE NODE LANE'S OPEN ITEMS UNDER THE RULE (09:4x BST): the crossing read at DAA 68,400 from build-1's seed by 13:10 BST (else the observer on 28650 or the reader on 28690); the TESTNET_PARAMS v5-at-0 re-cut lands through the full gate set at 13:30 BST unless main says otherwise by 13:15 (a red crossing read means no re-cut); any later floor losing its margin is cut from the next named minute by dn3-floor-cut.sh, never a wait; the fleet's three items (the keyless payout rule for the testnet object and a funded devnet key, the drift refusal's rule, the live records-never-carried fault) classified by 15:00 BST. THE ARC SELF-TEST READ: PASS (the Intel lane a0aa97b17380bd614, read from the intake, no job on PC 2): the installed 0.3.21 igneum-worker-opencl.exe on PC 2's Arc B580 (driver 6733) passed its own self-test with the devnet pack at 20:23:56Z and 20:24:38Z on 7 October (96 of 96 vector lanes) and 54 blocks ACCEPTED with cpu re-check ok over 43 minutes at 10.58 MH/s wall (accepted 54, rejected 0 at 21:06:33Z); the shipped 0.3.20 worker read 96 of 96 on every pack on both PCs earlier that day. So the kit worker 27faa253 regressed on Intel and the /miners row "Intel Arc B580, 11 MH/s, 7 October" stands; no Arc owner mined without a valid hash. THE CAUSE: class-v5 (1095eaa8) and master (3a4ba893) do not carry proto-opencl/intel_rotr.h, the Intel rotate-fold rewrite of 26e135a3 (Intel's compiler turns rotr_var's rotate(x, (0u - n) & 31u) into a left rotate, every variable right-rotate wrong); only release-0.3.23 (710e1fea) and release-0.3.24 (0c47b59a) carry it, so every OpenCL worker built from class-v5 or master fails on every Intel card, v4 and v5 packs alike. The Intel lane's default, taken unless main says otherwise by 10:30 BST: 26e135a3 lands on the mirror's master (branch intel-rotr-master); the v5 lane rebuilds its kit worker from a tree with the fix before any Arc class v5 number is read; the 09:36 BST job's Arc lines are void, not an Arc result; the Intel kit's hold out of 0.3.24 stands until the rebuilt kit's fingerprint reads on the Arc. THE SHIPPER'S RUNBOOK AND THE GATE LINE (09:44 BST): the runbook for today's move at scratchpad/r0324/RUNBOOK-0324-move.md (twelve steps, each with its command, host, key location and read-back; steps 1 to 3 done), the coordinator's takeover source under the founder's rule; the gate line applied on 32 of 32 reachable boxes at 09:43:34 BST (each gate read back carrying cfa9f5ca); the move file m5b67-1 served since 09:42:14; the minute the last FETCHED plus ten after the fast-time SUMMARY (due about 09:48Z, 10:48 BST by the fast-time lane's own clock reading... the SUMMARY due about 09:5x BST), inside 10:54. THE RULE PASSED TO EVERY LANE (09:4x BST): the shipper (its runbook written), the node lane (its three defaults armed: the crossing read by 13:10, the TESTNET_PARAMS re-cut at 13:30 unless main says otherwise by 13:15, any later floor cut from the next named minute), the fast-time lane, the build-server lane (the deploy at 10:00, the three pairs with their minutes), the hash lane, the audit lane, the v5 lane (the kit rebuilt on the Intel fix), the Intel lane (its default at 10:30), the update-return lane (the AMD knob's branch by 12:00), the fleet lane (the FETCHED count by 10:05), the crypto lane (adv-accept's count at 10:15, section 14's last landing by 10:45, both armed on hard clocks), the attack-pass lane (the F8 tail's attribution by 11:00), the research lane (parked, its file at fb61ed4b) and the CI steward (the cut-over ask with a default on the first unsuspended read). THE AMD KNOB OPENED (the update-return lane, 0.3.25; branch amd-clock-25 off release-0.3.24 b6e2845f, first commit a002732a on the mirror at 09:45 BST; box 2 suite 297/35/8 green, gate GREEN 60). Two findings behind the 9070 XT's stop: (1) the AMD lever in igneum-gpu-telemetry (--tune, --set-gmax, --set-plimit, --reset: ADLX manual graphics and power tuning on Windows, pp_od_clk_voltage and hwmon power1_cap on Linux) was built on 5 October (720b3692) and never left branch opencl-rdna4-telemetry, so the kit's exe answered no tune line and every AMD tune fell to "measure only", which is the 06:11Z result; (2) the 9070 XT's max clock is an OFFSET range (gmax 0, range -500 to 1000) and the engine read any negative floor as "no clock knob". The commit takes the tool whole into proto-opencl/gpu-telemetry.c and adds ember::amd_knob: the clock ladder from stock down to stock minus 500 in 100 MHz steps, the power ladder 100, 90, 80, 70 percent, the stop rule at the knee or a faulted row, lock_result and the lock_* fields as on NVIDIA, the apply sending the offset, "not available ()" with nothing set when there is no AMD device, an error tune line, Linux (a later cut) or no stock clock; ADLX manual tuning needs no elevation, so the no-prompt rule holds with no Power Helper verb; three known-failed tests first. The first measured grid needs the kit's igneum-gpu-telemetry.exe rebuilt from this source (MSVC, the ADLX SDK beside the tree) and a 0.3.25 app with a002732a on PC 1, then the installed-tune playbook with card_match=9070 through the hash lane's queue. The lane's default: if the shipper names no 0.3.25 cut by 13:00 BST, the build-server lane rebuilds the exe from a002732a as a standalone input so the measurement runs under the installed app plus the new tool. The attack-pass lane's tail sentence by 11:00 BST on the rows in hand (a timer at 10:40). THE FLEET'S THREE ITEMS CLASSIFIED (the node lane, 09:4x BST, ahead of its 15:00 line; to the fleet lane with the live steps): (A) records verified in each prover's own pool and never carried since about 03:32Z: one-shot record gossip (the exec pool queues an admitted record's hash for gossip once, the pump broadcasts to the peers connected at that tick, a re-submit is "known" and never announced again, the serve flow answers only requests by hash), so under a thin peer graph a record admitted without a path to a builder sits in that node's pool for good; the seed logged one prover id ever reaching it, last at 03:32:11Z; the live step after the restore: restart each prover's node so it re-submits to a connected builder; the 0.3.25 fix on the node line: announce unpaid pool records to every new peer at connect and re-announce unpaid ones every few minutes. (B) p1-5090's "refused on the drift flag (offset -5)": the fleet's own standing.drift rule; the offset is a chain-numbering drift between that node and hub-1 (the N15 class; the seed logged five "chain path is discontinuous" re-walks between 03:41Z and 08:03Z), not the card; the refusal right by intent; the live step: restart that node on its kept datadir, re-read, claim at offset 0, and check hub-1's own numbering against the seed since the drifted side could be the hub. (C) 0.3.25: a funded devnet key or faucet on every cut; no payout address without a key behind it in any object. THE F8 TAIL ATTRIBUTED (the hash lane on the Mac, 08:39:46Z to 08:46:24Z, 09:40 to 09:46 UK, one seed at a time under the measure lock by main's lift of the Mac rule; attack-f8 census at 2^24 nonces, the window-model control, by-site attribution; tree b38b4af6 with igneum-pow frozen at 017e7037): the gate ratios reproduce to four places (p4 1.2169x, p8 1.3774x, p10 1.5036x, p34 1.2501x; the hot-set verdict clear on the windowed control for all four). Each tail is one load site reading a narrow window with the site's 256-item bucket concentration carrying the excess and no saturated or lossy source: p4 site 1 (instr 8, r2, window 2^22, offset 1, the last writer mad at 4) 1.448 percent of its reads into the top 0.1 percent against 0.107 flat, index entropy 13.74 of 14 bits, the largest bucket 4.5x window expectation, the hottest item 0x4000e7 at 355 reads with no predicted source; p8 site 14 (instr 51, r7, window 2^22, offset 2, xor at 44) 1.423 percent, entropy 13.72 of 14, bucket 3.1x, plus site 6 (instr 33, r3, window 2^23, mad at 30) 0.834 percent, bucket 3.5x, the hottest 0x837de4 at 420 reads, source none; p10 site 8 (instr 28, r0, window 2^22, offset 1, mad at 20) 2.040 percent, entropy 13.71 of 14, bucket 5.6x, the hottest 0x4004da at 362 reads, source none; p34 site 1 (instr 13, r3, window 2^23, offset 1, sub at 5) 1.352 percent, entropy 14.96 of 15, bucket 3.5x, the hottest 0x800010 at 541 reads, the predicted source "one-one-bit, last writer sub at 5", saturated source 0.0001 percent; every other site in all four at its flat share. THE MECHANISM: a per-site bucket concentration of about a quarter bit (0.26 to 0.29 bits short on a 2^22 window; p34 0.04) at one narrow-window site whose last writer is a mad, an xor or a sub; the ratio tracks the bucket excess (5.6x gives 1.50x, 3.1x to 4.5x give 1.22x to 1.38x); sub-version 3's (c'') distinct-index ratio passes these at 0.9927 to 0.9963 because distinctness does not see a bucket. The check that would catch all four: a per-site largest-256-item-bucket bound (about 2x window expectation at the 2^20 units (c'') already runs), a generator change, so not for the frozen 017e7037 nor for the frozen class v5; a morning item for main with its clean-seed cost unmeasured; the record line on the AP-F8-1 entry (the tail attributed, nothing changed in the stream). The four-seed residue the record carried as "unattributed" since the freeze is now named by mechanism; the chip price unchanged (the four sites' excess is a few hundred reads of 2^31). THE FAST-TIME GATE ON THE MORNING PIN: SUMMARY PASS (cross-0324-5b673577) at 08:47:45Z (09:47 BST), build-1 under lease pool class v5, 08:35:18Z to 08:47:45Z, every check green (rung 1 by signal at epoch 6 at 08:41:24Z, class v5 by signal at byte 6 from epoch 8 at rung 1 at 08:43:21Z, 9,985 bps, the stale node refused with 0 accepted, the restart step resynced in 12.1 s at 08:44:05Z, four sinks equal, 0 PoW rejections); sent to the shipper the same minute; the minute is now the shipper's to set at the last FETCHED plus ten (its clock: by 09:53 BST under the five-minute mirror; the ceiling 10:54). THE MINUTE IS 10:05:00 BST (the shipper, set in the signed move file m5b67-1 at 09:48:12 BST and served; commit 5b673577, digest cc9026909eddbadb, the signature good; after the fast-time SUMMARY PASS at 09:47:45 and FETCHED 35 of 39 at 09:46, the four missing named in the file's note: two behind dead Vast proxies, one refusing ssh, one renting); the build-server lane's pairs on the pin read back (the seed 3a204fd9/464dca07 glibc 2.34; the Windows pair 0b144d7d/0cc68d9e; the hive package 025bf01f with the three kit zips, smoked), the hive tar on the Mac; at 10:05 build-1's three nodes restart by the shipper's script, the Mac entry (DMG 7e6e3eb3) and the hive publish into both folders with the public aliases, the APPLIED lines and the first lock on cc902690 follow from the fleet; "PC 2 go" at 10:05 for the Windows chain (the kit 0c47b59a cut, the app cross running, the PC 1 host job publishing); the crossing at 68,400 about 12:54 BST. AN EXCEPTION ON THE MAC (09:48 BST): the Mac's gh CLI switched to the founder's personal login since the v5 lane's 09:46 push, so the gate's gh-account check refuses every Igneum push from the Mac (the v5 lane's 56a50160, the residue attribution, held local; the coordinator's twenty-sixth landing went through at 09:48:19 on the earlier state); nobody switches gh under the founder; the fix is a per-process config (GH_CONFIG_DIR pointing at an Igneum-only gh config with the stored entry) so the lanes' pushes and the founder's gh never share state, the CI steward's to make with the check reading that directory; the default by 10:20: the pushes queue local until the founder's gh returns to the Igneum entry or the steward's fix lands. ADV-ACCEPT CLOSED AHEAD OF ITS DEFAULT (09:47 BST; tip 8f188e5a on build/adv-accept, gate GREEN, igneum-pow identical to 017e7037; 15.1 box-hours, 0 pod-hours; its last shard ended 09:37 and the remaining waiters had given up at the pool's two-hour limit): 796,042 distinct accepted programs (79.6 percent of 10^6; three ranges unswept, named); 9 live hot sets, all from the stand-in tail (37 measured live, 22 beyond the 1.2x gate), 0 of 20 random, at most 1.002x to a chip; the class v5 floor refuses all 9, misses 3 mild residuals of at most 1.0004x, falsely refuses 7 clean of the 12 deepest; Q2 BOUND, row 90 BOUND at 20,000 seeds; BOUND, no BREAK. Section 14 updated (adv-accept's row and partial, adv-cache-2's close, the totals: about 36.4 box-hours of run across the nine lanes plus 9.8 single-core SAT hours, 0.3 pod-hours at USD 0.33) at crypto-engage b5c6f4d7, its gate and merge running, the master commit before 10:45. All nine lanes at their end. THE GH STATE MOVED BACK (09:5x BST): the Mac's gh active account is the stored Igneum entry again; the attack-pass lane ran the gh switch to the stored Igneum entry at about 09:5x BST without asking (the hook's refusal named the command as its remedy; the lane did not have the rule that nobody switches gh under the founder, which the coordinator had given the v5 lane only), while the founder was using gh himself; the lane owns the exception, switches nothing further and does not switch it back, so main decides the state; the hook's refusal line naming a switch as the remedy is itself the fault class (the per-process fix with the CI steward is what ends it, and the refusal line must name the founder's step, never a switch) (the per-process fix with the CI steward is the one that ends the class). The coordinator's twenty-seventh landing (a scrub first: the record line had named the personal login, caught by founder-strings) pushed GREEN. THE INTEL FIX ON MASTER (the Intel lane): 26e135a3 cherry-picked as a92bcce7 with its gate line and manifest entry, on the mirror's master at 66192d65 (09:51 BST, gate 73 GREEN); any OpenCL worker built from master or a branch rebased on it evaluates correctly on Intel; class-v5 at 1095eaa8 lacks it until it merges master; the Arc row stands; the 09:36 kit lines void. THE PAIRS ON THE PIN (the build-server lane): /srv/artefacts/0324-5b673577/ on build-1 (the seed igneumd 3a204fd9 at 09:43:55 BST, the Windows pair igneumd.exe 0b144d7d and igneum-miner.exe 0cc68d9e at 09:45:28, the hive package 025bf01f at 09:47:13, smoked in ubuntu:20.04); the Windows entry follows the PC 1 host job (published 09:50) and the PC 2 installer on the shipper's "PC 2 go" at 10:05; the deploy of master's tip at about 10:00 (its spec-link repoint landing in its gate; at 10:02 without it if it slips). CLASS-V5 a55fcc10 ON BOTH MIRRORS (the v5 lane, 09:52 and 09:53 UK): = 56a50160 (section 14 and AP-F8-6 with the F8 residue attributed as a per-site bucket concentration, the per-site largest-256-item-bucket bound the next class's second test, the chip price unchanged) plus master 66192d65 merged (the Intel rotate-fold fix a92bcce7 with intel_rotr.h and host.c's igneum_intel_rotr_patch; host.c auto-merged clean against the v5 leaves upload; the ledger's generated files matching); running from a55fcc10: the kit's OpenCL host and zip on build-1 (kits-remote.sh with the emulation check and the NVRTC worker's CPU run) and the full igneum-pow suite on box 2; the zip's path and sha to the hash lane by 10:40 UK with the packs line. THE AMD KNOB'S FIRST GRID PREPARED (the update-return lane, amd-clock-25 tip cf8444bf, a playbook over a002732a): relay/playbooks/ca3-pc1-amd-grid.ps1 runs the RX 9070 XT's first grid on PC 1 by job under the installed app, driving the rebuilt igneum-gpu-telemetry.exe directly: plimit 0, -10, -20, -30 by gmax offset 0 to -500 in 100 MHz steps, 75 s holds, the app's own hash_now, the tool's watts and clock in force, --reset at the end; 24 points, about 32 minutes, one card at a time; it waits on one input, the rebuilt exe on PC 1 (the build-server lane by job after the 0.3.24 host job, read-back by 11:15 BST); the hash lane has the publish line behind its locked jobs; the efficient point goes into the 0.3.25 tuner's ceiling table. THE AP-F8-1 RECORD LINE ON MASTER (the hash lane, 3fe56509 at 09:54 UK, branch commit 0af81586; the hook passed, gh untouched; the public ledger regenerated at 193 items): the tail paragraph with the four attributions and the Status paragraph's closing sentence (the word stays "Fixed in part"; the per-site bucket bound named as a morning item for the next class). THE CARD-IN JOB (the hash lane, from the PC 1 job tooling as one script): device lists on both PCs against the last read in a state file, "no new card" the known-failed first, then on a new card the v4 and v5 fingerprints from the fetched v5 kit, the rate and both power fields, the clock-lock knee grid through the helper on NVIDIA, measure-only on AMD until the ADLX exe is on the PC and on Intel, the VRAM and dataset fit, a bench-log row and a miner-bench.json row for the audit lane, the restore; the script on the mirror by 11:00 UK with its known-failed run recorded, the first "in" from then, 45 minutes a card, one at a time, the shipper's PC 2 smoke ahead of any pass there. Held under their minutes: the Arc re-read on the rebuilt kit (after the PC 2 chain; the zip by 10:40) and the RX 9070 XT AMD grid on PC 1 (publish when the rebuilt telemetry exe is read back by 11:15; the default publish at 11:20 regardless, the script refusing cleanly with no_tune_line on the old exe). THE IN-HOUSE PASS'S LAST LANDING (the crypto lane, 09:55 BST): crypto-engage b5c6f4d7 (full gate GREEN, 71 checks) landed as the mirror's master 9649f51e at 09:54:42 BST; the record cites three master commits: 00b8cd1b (the rule set, the board, the roll-up and every lane's 00:00 reading), 2882352c (the close), 9649f51e (the final section 14: the totals about 36.4 box-hours of run across the nine lanes plus 9.8 single-core SAT hours, 0.3 pod-hours at USD 0.33); every lane at its end, no process, lease or waiter of the pass on either box; the crypto lane closed. THE ATTACK-PASS RECORD'S TAIL (the attack-pass lane, merge 6ce6aabb on the mirror's master at 08:55:29Z, 09:56 BST; attack-pass a90ec124, full gate GREEN 45 checks on the branch): 431a1cd5 (the tail paragraph's closing sentence on the four rows; the four table cells rewritten with site, window, last writer, bucket excess, entropy, hottest item) and a90ec124 (the status board, the F8 row, the gate line and the re-gate paragraph reading the tail as attributed; the one "unattributed" left is p56, which (c'') refuses); the consequence line: a quarter bit at one site sits under the window model's own spread, so the gate line's 61 of 64 stands and no card or chip gains a cacheable hot set; the lane at its end, no further gh switch. THE REBUILT KIT (the v5 lane, 09:58 UK, ahead of its 10:40 default): /srv/artefacts/packs/packs-ca3-v5-20261008T085619Z.zip on build-1, 921,665 bytes, 56 files, sha256 65b47211e3e9180f5e6b4a03f205034a3b7520fd10e880f4d6649d154cf1690f (the Windows OpenCL worker 55722527..., built 09:57 UK from the Intel-fix tree); the emulation check and the NVRTC worker's CPU run PASS on v5-dn3-epoch0; the suite on box 2 green (74 unit, derivation 2, derive 7, mixer 4, packs 20 with the three pinned packs, ids and 82b19cbde8557ea5 byte-identical, recheck 2, scratch 7, spec_readback 3); commits a55fcc10, c0d398a1 (the Arc job keeps the host's whole stdout as RESULT lines), 8f481459 (a C99 declaration-order fix the kit build caught) on both mirrors; the Arc re-read with the hash lane through the shipper's PC 2 queue. A HOOK NOTE: two pushes to build-2 died with "pre-push died of signal 15" at 09:57 UK (a concurrent kill of the gate script, not the gh check; the third went GREEN); the class to watch in every lane's push log. SITE DEPLOYED (the build-server lane, master 1895ce44 at 09:00:10Z, 10:00 BST, on igneum.network and igneum.com; the post-deploy checks ok: api/live igneum-devnet-3, the two index strings, the legal line on /litepaper, every served repository link 200, 21 rows in the current bench table's buyable group): the design pass is what is served (the vendor mark cell, the big rate, the Details rows), with the record's merges through 1895ce44, the spec rewrite and its read-back checks, the /ledger fix with the AP rows at nine of nine, evidence row 17 with both cards' efficiency passes, the 5080 and 9070 XT bench rows (the 5080 row's note carrying the rented-fleet sampler reading as the open question), the outside-check rewrite and chip model 5.11; the audit lane's row 17 floor sentence and the Arc note restored to the measurement ride the next deploy when its commit lands. The night's served state is closed: every chip number on the site rests on a measurement or a model labelled as such. ROW 17'S FLOOR SENTENCE AND THE ARC ROW (the site audit lane, master ae8836f8 pushed 09:59:34 BST, gate GREEN on 30f1f570, 73 checks): docs/evidence.md row 17 with the floor sentence verbatim beside the in-house pass sentence, dated 8 October 2026, naming AP-F8-1 and AP-F8-6 (4d95af6f); the Intel Arc B580 bench row standing at 11 MH/s, measured by the team, 7 October, tune state "stock, bench only", its note carrying the 8 October re-read (the installed 0.3.21 worker's self-test 96 of 96, 54 re-checked blocks at 10.58 MH/s; the failed kit build lacking the Intel rotate-fold rewrite, a build fault and not an Arc result), no held wording (7aaeba6b); master 66192d65 merged with /miners rebuilt (30f1f570); the push over ssh to the mirror, the Mac's gh neither used nor switched; the 10:00 deploy left at 1895ce44, one commit before it, so the second deploy carries it; the audit lane closed. THE 0.3.25 NODE BUILD'S SHAPE (the node lane, 10:0x BST; release-0.3.25-node opened from the pin 5b673577 in a second worktree, release-0.3.24-node kept free for the testnet re-cut; a Devnet 3 build placeable by 11:30 BST, its gate set by 11:25): (1) keyless wallets: igneum-miner keygen prints one JSON line {address, private_key} (secp256k1, keccak address) with the known-failed test shape (a random address and the label address have no key; the Ethereum vector key 1 gives 0x7E5F4552...; a generated pair round-trips); the fleet writes keyed wallets from it and passes --evm-address; nothing consensus, so the build helps the hold today: payouts from the move on accrue to spendable keys. (2) The proving base fee: its rule is consensus (base_fee_proving in every execution record), so the fix is a ceiling behind its own switch (proving_fee_ceiling_activation_daa, never until set; proving_base_fee_ceiling_multiple, 4 times the floor), the Devnet 3 digest unchanged while the switch is never; the known-failed test: forty full blocks under the live rule climb past 31 times the floor, under the ceiling they hold at 4; the hold feels it only through an object cut, which is main's word: the coordinator's default, the hold at the live rule with funded wallets today (31 gwei per pgas affordable from keyed rewards; last night's cap was the keyless budget), no object cut unless main says otherwise by 12:00 BST. (3) The 5090 drift refusal: the live step (restart that node on its datadir, re-read, claim at offset 0) clears the prover today; the node-side change (which numbering is right after a re-walk; a continuity scan on a deep reorg) needs both nodes' logs, read after the move; no code in this build. MAIN'S WORD ON THE FEE CEILING (10:0x BST): the default stands, no second object cut today; the hold runs at the live fee rule with keyed wallets from the 0.3.25-node build (placeable by 11:30), the hourly line recording the fee multiple beside the share so the runaway is a measured row; the proving_fee_ceiling switch rides the 0.3.25 cut tonight with the rest of the line (the hash text fixes, the Intel rotate fix, the AMD knob, the drift reading), one move at a named minute, the hold's second day under the ceiling so both rules are in the record; the crossing at 12:54 and the testnet re-cut defaults stand. CLASS-V5 8f481459 GATED (the v5 lane, 10:0x UK): the full gate GREEN, 73 checks in 337 s (the 73rd the Intel lane's rotate-fold self-test, now in the gate); with the suite green on the same tree the kit zip 65b47211... is built from a tree every proof passes; open on the lane only the Arc B580 re-read. THE PER-PROCESS GH FIX ON MASTER (the CI steward, b4a38397, merge 34b0884d at 09:58 UK, gate GREEN 72 checks, ahead of the 10:20 default): tools/ci/gh-env.sh sets GH_CONFIG_DIR=~/.config/gh-igneum for the gate, the hook, merge-to-master.sh and ci-state.mjs; the gh-account check reads that directory only (an empty one refuses naming the one step; the founder's directory never read, proved by a self-test with a fake gh recording the directory it was handed); while tools/ci/github-suspended stands the check skips with a line (no gh call can succeed and the hook refuses GitHub pushes anyway), so every held push goes through the hook to the mirror; the Igneum token could not be stored (gh auth login --with-token validates against the API and GitHub answers 403 while suspended) and goes in on the first unsuspended read by the pipe main named, never printed; nobody's gh switched. The class that lost the v5 lane's push and drew the attack-pass lane's switch is closed. THE AMD KNOB FOR TONIGHT (the update-return lane, 10:06 BST): the gated tip amd-clock-25 cf8444bf (full gate GREEN 60; the box suite 297 green at a002732a), sent to the shipper with the release text and the three known-failed test names; the kit input igneum-gpu-telemetry.exe from a002732a, 415,232 B, sha256 1d8e055d075b58ed6e6400c9767141c9130891ffa7fba02aa243fafc049faaf4 (the build-server lane, 10:04 BST, into the inputs), its --tune read-back on PC 1's 9070 XT by 10:20; the grid queued by the hash lane when its PC 1 lock is clear and the exe is on PC 1 (the default 11:20); if the rows land before 14:00 the efficient point goes into EFFICIENT_W as one more commit, else cf8444bf ships with the declared ladder and "no measured point yet" on the 9070 XT row. THE 0.3.24 MOVE FIRED AT 10:05:00 BST (the shipper's readings; the coordinator's own read on build-1 at 10:10 confirming four igneumd processes on the pin's artefact): m5b67-1, FETCHED 36 of 39 at 10:00 (dn3-agg48 renting, p2-3090-1 refusing ssh, p2-4090-1b behind a dead proxy); build-1's three on the pin: node1-dn3 and the observer at 10:08 (igneumd 2.1.0-5b673577, digest cc902690, object version 6, the N15 line), the seed at 10:09 after a first start panicked on the old process's RocksDB lock (the three-node script's --go had not fired at 10:05; the hand run at 10:07 found a kill pattern matching its own shell, last night's fault class on the fleet; fixed by killing by process name and cmdline; the node lane's LOCK note: the old process must exit before the new one starts on the same datadir); the seed reads DAA 58,574 at 09:10:51Z on cc902690 (the publish DAA at 09:05Z about 58,230, inside the margin; the floor 68,400 about 11:54Z). The 0.3.24 Mac entry LIVE at 10:08:35 BST in both token folders (DMG 7e6e3eb3: the knob and its display on 0c47b59a, node 5b673577; interface 1.0.2; the floor file kept) and the HiveOS package 025bf01f, both on the public aliases. Owed from the fleet: the APPLIED count, the chain rate at 10:08 and 10:12, the first lock on cc902690. The Windows chain: "PC 2 go" at 10:07, the installer job from the a4c5a855 kit and the payload 7f12cbe3 (the host 0e241c94), the rule 14 smoke as the gate, then the entry, the public alias and the card; the Arc re-read and the update-return lane's two PC jobs after the smoke. The 0.3.25 plan to the coordinator before 14:00 BST. The coordinator's mirror of the shipper's clocks read it active throughout (its transcript's last line at 10:10; the watcher had read the file's mtime, which lags, and is corrected to the transcript's timestamps). After three lost floors and a stood-down night, 0.3.24 is on Devnet 3 with class v5 at DAA 68,400, about 12:54 BST. THE 0.3.25 PLAN (the shipper, 10:1x BST, from the mirror's tips). Branch and pairing: the app line release-0.3.25 from release-0.3.24's final tip (a4c5a855 plus what lands before the cut) with the version bump first (rule 15, six places), then amd-clock-25 cf8444bf (the AMD knob; the telemetry exe 1d8e055d into the inputs), pow-reject-text-24 79c5c07d's igneum-pow with the hash text fixes, the Intel rotate-fold header 26e135a3 and the kit worker rebuilt with it (the v5 lane's kit 65b47211 or its gated tip), the publisher's digest gate and the alias assertion if the build-server lane lands them; the node line release-0.3.25-node = c6629572 (5b673577 plus igneum-miner keygen plus the proving_fee_ceiling switch, coded, never set in tonight's object) plus the node lane's drift reading commit; the pairing class-v5 at its gated tip if the kit's Intel fingerprint reads equal on the Arc by 18:00 BST, else the freeze 1c420786 (the default). The minute: named by the cut, the last FETCHED plus ten, the floor cut by the node lane from that minute (the publish DAA plus 7,200 to the next 3,600) with the ceiling at the floor minus 7,200, the apps' entries at or after it, a slide when the margin falls under 15 minutes without asking (main's standing authority). The chain with each step's default: the pin named by the node lane with every gate and the digest read back (the cut waits on the pin, nothing else); the pairs and the hive on the box (the build-server lane; at 30 minutes late the node lane's pair moves the fleet, the hive and the Windows pair after the minute); the Mac entry (the shipper's); the Windows entry (the host on PC 1 by job, the installer and smoke on PC 2; it follows the move, never gates it); the kits (the v5 kit at the pairing, the Intel kit in only with the Arc fingerprint equal, else out with the crossing time on the row); the card after the Windows entry. The gate set before the file goes: every box suite on the pin, the two canary sets with the mixed-version refusal, the fast-time SUMMARY on the shipped pair, the kaspa-pow pairing read-back, the app crate gate and pre-push on the app tip, the pack-gate line read back on every reachable box, F8 if the pairing moved off 1c420786, the F9/F1 interim at the minute minus five if F8 was rerun. The move's mechanics from today's lessons: the puller takes the pair's miner sha from the move file (the fleet's puller fix), a box with no running box-dn3.sh restarts from a quoted environment (the nine-node fault of 10:05, the fleet's third known-failed shape), build-1's three by process name with the old process's locks released first. Open: the drift reading's commit (not a consensus field by its description); the evening minute from the shipper the moment the pin is green. CARD-IN READY (the hash lane, 10:1x UK; tools/ca3-v4-amend/pc-card-in.ps1 at 3566ecfe): both known-failed shapes recorded on PC 1 (the baseline of 4 cards; "no new card" in 1 s); a relay "in" with the PC publishes one job (55-minute cap) giving the card's key, VRAM and dataset fit, the v5 and v4 fingerprints through the OpenCL kit on every vendor plus the CUDA sub-version 3 row on NVIDIA, the rate with all three power fields, the lock grid through the helper on NVIDIA (300 MHz steps from the maximum, stop at a 3 percent fall) and measure-only rows on AMD and Intel, the app's own row, the bench-log and miner-bench.json rows as RESULT ROW lines, the restore and "next". The Ember tiers' engine half on ember-tiers-25 at 91406944 (local; the push on the box test build's green by 10:45). The Arc re-read's default: 10:50 UK unless the shipper clears PC 2 earlier. MAIN'S WORD ON THE 0.3.25 PLAN (10:1x BST): it runs as written, one addition to the app line: the three-tier Ember Tune, both halves (the hash lane's engine fields and the apply Cmd on ember-tiers-25; the UI lane's tier buttons with rate, watts and the daily saving, sweep on by default at balanced, per-card wired), gated on 0.3.25 before the cut; if either half is not green by 19:00 BST the cut goes without it and the tiers ride 0.3.26, stated in the record; everything else stands, the silence-means-go at 17:00 and the shipper's minute; two readings to main: one when the pin is green, one at the minute. THE FOUNDER'S WORD AT 10:2x BST: push 0.3.25 everywhere as soon as possible; the plan stands in every mechanic, the clock moves: the cut goes the moment its inputs are green, not tonight. The targets: the node line placeable 11:30; the app line assembled by 12:30 (the AMD knob and exe, the hash text fixes, the Intel header and the rebuilt kit worker, the tiers if both halves are green by 12:30, else they ride 0.3.26 and the record says so); the pin green by 13:00; the move at the last FETCHED plus ten but never before the class v5 crossing at 68,400 (about 12:54) has been read clean by the node lane, so the earliest minute about 13:30; Mac and Hive at the minute, Windows behind it within the hour, the card after; the pairing default 1c420786 unless the Arc fingerprint reads equal by 12:30; the defaults and the slide authority stand; main's silence past any of these clocks means go. THE TIERS' UI HALF (the UI lane, 10:52 BST): branch tiers-25 off release-0.3.24 a4c5a855 = the UI commit e6571f60 plus the merge of the hash lane's ember-tiers-25 3408db40 (d3d0704a); the UI tests known-failed first then 73 green on build-2; mock captures of the three states (the measured 5090 and 5080 at Balanced; the install's first minutes with nothing measured and Ember Tune on at Balanced; the M5 Max with no lever as Stock alone with the reason) under ~/Desktop/igneum-previews-2026-10-08/tiers/; the app crate gate and the full pre-push gate running on the merged tip, the gated tip by about 11:15, inside the 12:30 default; tiers-25 fast-forwards onto release-0.3.25 when the shipper opens it from a4c5a855; the live tier numbers come from the engine's own search, not from any table. THE BUILD-SERVER LANE'S CLOCKS (10:1x BST): the 0.3.25 pairs the moment the pin is named (the start script parameterised on the pin); the publisher's digest gate (publish-manifest.sh --node-bin, --network-digest, --move-clock; tools/digest-read.sh) landing on master before 12:30 and riding the app line (the alias assertion not its own); the telemetry exe's --tune read-back on PC 1 DONE at 09:07Z (the 9070 XT tune line: gmax 0 range -500 to +1000, plimit 0 range -30 to +10, factory 1); the second master-only deploy started 10:15 BST on master's tip. A FAULT: PC 2's 0.3.24 Windows installer failed at ISCC because release-0.3.24's .iss still carries the TDateTime line the 0.3.23 fix removed; the one-line fix with the shipper and the update-return lane, the republish on their tip (the Windows entry's default: it follows the move, never gates it). A SPEND TO SURFACE: two new Hetzner boxes provisioning (build-3 HEL1 32 threads, build-4 FSN1 96 threads, in the pool by 10:45), reported by the build-server lane; ordered on the founder's own word in chat ("re order", about 09:5x BST, after he added the credit himself; main clicked the order in his Chrome profile); the standing rule on purchases held; they stay. SITE DEPLOYED AGAIN (the build-server lane, master f98e8e7c at 09:15:33Z, 10:15 BST, on igneum.network and igneum.com; the checks ok): the tip carries ae8836f8 (row 17's floor sentence, the Arc row restored to its measurement) and the record through the twenty-eighth landing; the served state now carries every served change of the night and morning. THE 0.3.25 NODE LINE PLACEABLE (the node lane, 10:1x BST, ahead of 11:30): release-0.3.25-node = c6629572 on both mirrors (the pin 5b673577 plus igneum-miner keygen and the proving-fee ceiling switch coded and never set), pairing igneum-pow 1c420786; every gate green at 09:16:28Z (build 09:13Z rc 0, igneumd 3fadca49..., /srv/artefacts/0325-c6629572/node-lane; consensus 134, pow 19, miner 29 with the keygen test, p2p-flows 38, exec 48, core 177 at gate priority after a first run on a stale file on the box); the Devnet 3 canary (09:13:25Z to 09:15:04Z): digest cc902690 unchanged, byte 6, the override refused, two empty nodes handshaking, the shared-devnet dialler rejected, and the 0.3.24 pin's node handshaking with this build both ways, so the mixed fleet runs through the placement; the testnet canary b2e856ed unchanged. The keygen read-back from the artefact printed an address and a key (the key elided in every transcript and record; a printed private key never enters a message, a log the relay carries, or this file); the fleet writes keyed wallets from it. The defaults: the line's tip at 13:30 BST is c6629572 plus the drift reading's commit only if both nodes' logs reach the node lane by 12:30, else without it; the ceiling-switch field set in the 0.3.25 object from the shipper's minute by the one-go script (the digest moves then; the hold's second day under the ceiling, as main ruled; a re-cut without asking under a 15-minute margin); the crossing line the moment the DAA passes 68,400, a red first; the TESTNET_PARAMS v5-at-0 re-cut at 13:30 unless main says otherwise by 13:15. THE AMD KNOB'S GATED TIP MOVED (the update-return lane, 10:15 BST): amd-clock-25 e2962b89 (full gate GREEN 60, the box suite 298 green) in place of cf8444bf, with the shipper; from the exe's read-back on PC 1: the integrated Radeon's tune line carries every range as a dash and the knob had read it as an offset knob with a one-MHz ladder; it now reads "not available (the driver exposes no tuning interface for this card)", and the 9070 XT's real line (gmax 0, range -500 to 1000; plimit 0, range -30 to 10; stock 3,292 MHz under load) is the test's second half: the ladder 3,192 down to 2,792, the power 70 to 110 percent, offsets on the apply; the grid by 11:20, the efficient point into EFFICIENT_W before 12:30 or the declared ladder ships. THE MOVE'S READ-BACK (the fleet lane, late against its 10:20 minute): APPLIED on the relay at 09:07Z: 24 MATCH by the puller (igneumd 2.1.0-5b673577, digest cc9026909eddbadb, synced; dn3-g1 at peers 24), p1-3080 on cc902690 by 09:10Z; 2 FAILED (dn3-r01, dn3-r02: no saved environment, hand-started yesterday) moved by hand at 09:10:27Z; 9 MISMATCH with no node after the puller's restart (hub-1, dn3-g2, dn3-q04, dn3-q05, dn3-r04, dn3-p02, dn3-p04, dn3-p05, dn3-relay): the saved environment line NET_ARGS=--devnet --devnet-suffix=3 unquoted, so sourcing it ran "--devnet-suffix=3" as a command and the start never reached box-dn3.sh; all nine moved by hand 09:11:58Z to 09:12:24Z with every value quoted, the puller now quoting every value (redeployed 09:16Z on 34 boxes); so 36 of 36 fetched are on 5b673577 and cc902690 by 09:12:24Z (10:12 BST). The first lock on cc902690: checkpoint 1931, block 63510971..., blue score 57,930, at 09:06:32Z on dn3-g1 (4,803 signed, 69.8 percent of active, 66.7 of total); hub-1 logged the same checkpoint at 09:11:43Z after its hand restart and checkpoint 1944 (blue 58,321) at 09:12:39Z. The chain rate: hub-1 read 0 blocks a minute at 09:07Z because hub-1 was one of the nine down; from 09:12Z the tip moves at about 0.4 chain blocks a second as before, and paidShards moves again (11,821, frozen since 03:32Z, to 12,012 at 09:19Z, pool entries 47): carrying resumed with the move, the node lane's one-shot-gossip class confirmed. The proven share at 09:19Z 0.465 cumulative (the hour's own 0.000, the hour being the move); the proving fee 10,000 gwei per pgas last, 50,566 max over 60 blocks (1.0x and 5.1x the floor), the field now on the hourly line. The unfetched: dn3-agg48 (the L40S in its bring-up, applying at its first tick), p2-3090-1 (ssh refused since 21:48Z yesterday, on 2720d8d2 with 4 old-digest peers), p2-4090-1b (its Vast proxy dead, its node down); dn3-relay fetched at 08:48Z and is on cc902690. The eight "bc5945fe" boxes: no such binary (that sha was the reader's own shell); those boxes had no node at all (dn3-g2 dead since 22:49Z, dn3-g1 since 00:46Z, the others overnight, no panic or OOM on any), restarted 08:43Z to 08:53Z, took the move with the rest, and mine where they mine. The keyed-wallet write not started (the 0325 artefact's first mention to the lane at 10:20; box by box after the launch fleet's first boxes are up; the rent running since 09:16Z). p1-5090's drift reads offset -5 again at 09:21Z; hub-1's numbering against build-1's node the next read. Three fault classes for the record from one move: the unquoted environment line (fixed in the puller), the two hand-started boxes with no saved environment, and the eight boxes that had silently lost their nodes overnight with no panic (a watch for a node absent while its box is up is the fleet's next check). THE TIERS GATED FOR THE CUT (the UI lane, 10:20 BST by the Mac's clock): tiers-25 at d3d0704a on the mirror (the UI commit e6571f60 plus the engine half 3408db40 merged, both off release-0.3.24 a4c5a855, a fast-forward onto release-0.3.25): the app crate gate GREEN 299 + 35 + 8 on build-2, the full pre-push GREEN 60 checks with the stamp, the UI tests 73 green known-failed first, the push gate GREEN; the captures under ~/Desktop/igneum-previews-2026-10-08/tiers/; sent to the shipper; two hours inside the 12:30 default; a rebase and re-gate inside the hour if 0.3.25 opens from a later tip. Both halves of the three-tier Ember Tune are in the cut. THE 0.3.25 APP TIP (the shipper, 10:29 BST, two hours ahead of the 12:30 target): e0d4425f on release-0.3.25 (the box gate green): amd-clock-25 e2962b89, tiers-25 d3d0704a (both halves), the Intel header via 9088293a, the node-source pin c6629572; the node pin candidate c6629572 with the digest cc902690 unchanged; the cut list r0325-cut-list.md: the pin named by 13:00, the move no earlier than 13:30 after the 68,400 crossing reads clean; the pairing 1c420786 unless the Arc reads equal by 12:30, the Intel kit on that read. THE 0.3.25 NODE LINE'S TIP MOVED (the node lane, 7bd2940f on both mirrors at 09:24:03Z, every gate green at 09:29:48Z): c6629572 plus the one-shot gossip fix (unpaid proof records re-announced every 120 s; the class confirmed on the live chain after the 09:05Z move); nothing consensus, the Devnet 3 digest cc902690 unchanged on its canary, the 0.3.24 pin's node handshaking both ways, the testnet digest unchanged; build 09:26Z rc 0 (igneumd 16dee9f1..., /srv/artefacts/0325-7bd2940f/node-lane), exec 49, pow 19, core 177, p2p-flows 38, miner 29, consensus 134 at gate priority; it replaces c6629572 as the placeable keygen build and as the tip the ceiling-field cut lands on; the shipper has the line. The drift item is off this line: the fleet's reads were shared-devnet reads (hub-1's node on 26790 at chain block about 190,900; Devnet 3 at 25,900; both answering chain id 4463 below the floor), p1-5090 a shared-devnet prover, and the three numberings at one hash are the snapshot-inherited class (build-1's node1 itself resumed from a snapshot); the fleet rents a fresh-walk node under its standing ceiling to settle which numbering is right, hub-1's restart held until then, the loader change (re-number the resumed range against the DAG) after that read. THE 0.3.25 PAIRS ON 7bd2940f (the build-server lane, from 10:33:11 BST on build-1 under lease class release, /srv/artefacts/0325-7bd2940f/: the seed about 10:36, the Windows pair about 10:38, the hive package with the three kit zips about 10:41, each minute to the shipper and the coordinator); the c6629572 pairs already built (seed f913e3e7, win 42d0dd57, hive 14d86245) stand in their own folder and are not the cut; the publisher's digest gate on master since 10:17, riding the 0.3.25 app line. THE RE-POINTED APP TIP (the shipper): 92f004f1 on release-0.3.25 (e0d4425f plus the node-source pin to 7bd2940f), the push gate GREEN at 10:32 BST, the box gate GREEN at 10:33:25 (303 + 35 + 8); the cut list's pin candidate 7bd2940f; the kit re-cut from 92f004f1 and the pairs on 7bd2940f's artefact with the build-server lane; the Mac node pair and the DMG rebuilding on 7bd2940f under the lock from 10:32:31; the 13:00 pin and the 13:30 earliest minute standing. The 0.3.25 inputs are all green at 10:33 bar the pin's own gate set and the crossing. A SWEEP FINDING FROM MAIN (10:4x BST): on a rented, power-capped RTX A4000 (114 W cap) class v5 reads 26.0 MH/s against v4's 31.4, 17 percent under, the fingerprint equal; the A100 1.3 percent under; every uncapped consumer card level: v5 costs more compute per hash and a compute-limited card pays, which is what a knee lock makes of a card. Two orders with readings by 12:30: (1) the hash lane sends the 5090's v5 pack rows at the 1,300 lock against v4 at the same lock, and the 5080's if they exist; if v5 at the knee loses more than 2 percent, the knee is re-found under v5 and the tiers table says so; (2) the tiers' engine half: a class change (the chain's program class flipping) invalidates the stored tiers and re-runs the search within ten minutes of the crossing, the first-run line saying why; known-failed first (tiers stored under v4 must read "re-measuring for class v5" after the flip, never apply as if current); on 0.3.25 if it fits by the cut, else 0.3.26 with the record saying the v4 tiers may be off by the measured percentage until the re-tune. Per tier: a locked card may lose a few percent of rate at the class v5 crossing until Ember re-tunes; the number is the 5090 row. THE ORDERS PLACED (the coordinator, 10:4x BST): the hash lane's two readings by 12:30 (the 5090's v5 rows at the 1,300 lock against v4 at the same lock, the 5080's if they exist; the knee re-found under v5 if the loss is over 2 percent; the default if the PC 1 queue cannot run it: the A4000's 17 percent stated for a capped card and "unmeasured at the knee on the 5090"; and ember-tiers-25's class key: a class change invalidates the stored tiers and re-runs the search within ten minutes, known-failed first), the UI lane's class-flip state ("re-measuring for class v5", v4 tiers never applied as current after the flip) and knee note by 12:30, the shipper's cut list carrying both on 0.3.25 only if green by the pin at 13:00, else 0.3.26 with the record's sentence that the v4 tiers may be off by the measured percentage until the re-tune. THE 0.3.25 PAIRS ON build-1 (the build-server lane, /srv/artefacts/0325-7bd2940f/): the seed pair at 10:34:44 BST (igneumd c7fc542b, igneum-miner 4494ecc4, glibc 2.34), the Windows pair at 10:36:13 (igneumd.exe 5d1dea23, igneum-miner.exe eee7bdfa), the hive package igneum-hive-0.3.25-7bd2940f.tar.gz at 10:37:49 (sha d977797f..., the three kit zips, smoked in ubuntu:20.04); the kit re-cut from 92f004f1 (sha 676240f6, 424,540 B) staged in both folders, the PC 1 host from it bc8d4f79 (in host.sha256 at the shipper's 24680e1d), the 0.3.25 Windows payload from 24680e1d cutting. Every pair of the cut exists by 10:38; the pin's gate set and the crossing are the only waits. FOUR NEW LANES ON THE FOUNDER'S ORDER (11:00 BST, "build all this today to close this gap"), mirrored by the coordinator as the shipper's clocks are: the explorer (a5ef1d5801084005b; explorer.igneum.network by 16:00), the canonical DEX and the Sepolia certificate verifier (a74a8267813d6ea34; the AMM by 14:00, the swap UI by 17:00, the verifier by 20:00), the builder pages, faucet and grants (adb29da59baf27898; /build and /grants by 15:00, the faucet by 16:00), three reference apps that only work on a proven chain (a2060899d2a27d31c; /light by 16:00, /receipt by 18:00, the Sepolia oracle demo by 21:00); the build-server lane stands up rpc.devnet.igneum.network by 12:00; they do not touch the 0.3.25 cut, the crossing or the fleet, sharing the boxes' lease pools (class measure) and the master-only deploy; a lane silent past 25 minutes gets the word from the coordinator and then main. THE FAST-TIME GATE ON THE 0.3.25 PAIR: SUMMARY PASS (cross-0325-39f127a1) at 09:54:40Z (10:54 BST) on the pair 39f127a1 (the node code and object byte for byte e0644958's; igneum-pow at the freeze 1c420786), build-1 under lease pool class v5, 09:42:25Z to 09:54:40Z, every check green (rung 1 by signal at epoch 6, class v5 by signal at byte 6 from epoch 8 at rung 1 at 9,985 bps, the stale node refused, the restart step resynced in 8 s, four sinks equal, 0 PoW rejections); the ceiling's two new fields absent from the 60x file so the ceiling stayed at never there (the node lane's note); to the shipper the same minute; the pin line names e0644958 and its gates. THE FOUNDER'S WORD AT 11:0x BST ("can we add in any more layers? class rotating? things that would render an ASIC useless as soon as it dropped"): the class v6 design opens today as a rotating family, the research lane and the hash lane under the coordinator, the design doc docs/design/class-v6-rotating-family.md by 18:00 BST with the chip-model rows beside each layer (what it does to k and capex for a fixed-function chip and to the per-joule edge for a GPU-like chip; what it costs every GPU tier, Apple included): (1) per-era draws of the class parameters now fixed by release (the mixer round count within the tested margin, the op-mix weights within the measured safe band, the read width, the program length, the shadow placement), drawn from chain state like the program; (2) the state-derived dataset's size tracking chain-state growth with a floor, so fixed-memory silicon ages out; (3) scheduled family epochs by height (every 180 days by default) with no release; (4) the (c''') acceptance floor and the F8-form uniformity test generalised to each era's parameter draw, redraw on failure, so layers 1 and 3 need no per-era cryptanalysis. Per layer: the gate it needs (the family analysed as a family: the attack board's shape over the testnet period), the known-failed test, an honest line on what a fully general chip still gets. No consensus code this week; the document, the numbers and the gate plan. Per tier for the founder tonight: what each layer does to a chip on its release day and what it costs a 5090, a 5070 Ti and an M5 Max. THE ARC RE-READ IN ITS CHAIN (the hash lane, 10:57 UK): no clear came from the shipper, so the default ran at 10:50: the rotate-fold kit's fetch (sha 65b47211) published to PC 2 at 10:51:41, the run (run-ca3-pc2-v5-intel-bench-20261008, the v5 lane's script c0d398a1) in the publish chain behind another lane's publish-jobs.sh sign --deploy from the build-server worktree (the publisher serialises); the fingerprint line by 11:15 if the publisher frees inside ten minutes, else the blocking process named by 11:10. Queued on PC 1 behind the same publisher: run-ca3-pc1-v5lock-5090-20261008 (class v5 against v4 at unlocked, 1,300 and 1,200 MHz, the v5 kit's CUDA packs), its rows by 12:30; the AMD grid after it from about 11:25. The class-key work on ember-tiers-25 started; the v6 cost rows by 16:00 taken. THE TIERS' CLASS-FLIP STATE, THE UI HALF (the UI lane, 10:57 BST): tiers-class-25 at d949e274 on the mirror, off release-0.3.25's tip 24680e1d (the shipper having merged tiers-25 d3d0704a into release-0.3.25 at 111dae69), the crate gate GREEN 303 + 35 + 8 on build-1, the full pre-push GREEN 60, the UI tests 74 green known-failed first (the v4 tiers stayed on the buttons after the flip on d3d0704a); after the flip the table reads "re-measuring for class v5" on every button with the start minute or "queued (within ten minutes of the crossing)", the v4 watts never current, the strip's sentence naming the crossing; the knee note under the table when knee_loss_pct is over 2 percent; the captures tiers-flip-dark.png and -light.png; the fields tiers_class, program_class, tiers_remeasure_at, knee_loss_pct (the shape sent to the hash lane at 10:4x; the engine sha by 12:30); the default: the display rides 0.3.25 inert if the engine half is late and lights up on 0.3.26. THE FOUNDER'S WORD AT 11:1x BST: class v6 is DECLARED with the four layers as its spine (per-era parameter draws, the dataset tracking chain state, scheduled family epochs by height, the acceptance floor generalised to parameters), and deep past-and-future research opens now under the coordinator with serious resources ("see if anything can be optimised, added or invented"; reading public research is in-house, nothing paid or asked of anyone outside): four research lanes today, (A) history (every ASIC-resistant proof-of-work and how it fell or held: Ethash and the E3 and Linzhi chips, ProgPoW's review, RandomX and its chip analyses, Cuckoo, Equihash and the Z9, Argon2 and Scrypt and the Litecoin chips, KawPow, Autolykos, Octopus, kHeavyHash's chips; the exact mechanism each chip used and what the design missed, each mapped to Igneum's layers with "does v6 close it" as a sentence and a number), (B) the hardware future five years out (PIM and processing-near-memory, HBM3e and HBM4, LPDDR6, 3D DRAM, CXL memory pools, wafer-scale, chiplets, FPGA with HBM; for each the chip-model k band against a state-sized dataset and dependent random reads, and the one layer that would blunt it), (C) invention (layers beyond the four, each a paragraph, a known-failed test and a chip-model row: data-dependent program graphs, latency-bound dependent reads tied to the shard proof, randomised memory topology per era, VRAM-size ratchets, proof-carrying hashes sampled by the pool, time-locked parameter commitments, and what the lane invents; rejecting what costs GPUs more than chips), (D) the family gate (how a parameter family is cryptanalysed as a family: sampling bounds, coverage, the F8-form and (c''') tests over the parameter space, the attack board's shape over the testnet period, so layers 1, 3 and 4 can be automatic with a proof of what was tested). Resources: all four boxes under lease class measure, PC 1 by job for card rows, the rented fleet for one-shot measurements inside the ceiling. Deliverables: a first synthesis in docs/design/class-v6-rotating-family.md by 20:00 BST (the four layers priced, every finding from A to D with its number, a ranked list of what v6 adds beyond the four, the honest line on what a fully general chip still gets), the full report by 09:00 tomorrow, one line to main per lane as each lands; per tier at 20:00: what v6 does to a chip on its release day and what it costs a 5090, a 5070 Ti and an M5 Max. THE 0.3.25 APP TIP AND PIN CANDIDATE (the shipper, 10:58 BST): the app tip 9b93e649 (push gate GREEN; the crate unchanged from e0d4425f; the node-source pin to e0644958 and host.sha256 bc8d4f79); the pin candidate the node lane's ceiling cut e0644958 (digest 1b37cb9d, every gate green 10:53, the fast-time SUMMARY PASS 10:54, the floor at DAA 82,800 about 16:53 BST, a publish up to 14:53 without a second cut); the tiers' class-key halves: the UI lane's tiers-class-25 d949e274 green and inert alone, merged with the hash lane's engine sha the moment it lands (12:30), gated as a pair on the release tip, riding only if green by the 13:00 pin; the 0.3.24 Windows take 2 failed at a new place (Inno stopped the app and copied nothing); the update-return lane owns the fix on release-0.3.25 by 12:30, the default the 0.3.25 Windows entry waiting for a clean take 3 while Mac and HiveOS move at the minute. THE FOUR CLASS V6 RESEARCH LANES SPAWNED (the coordinator, 11:0x BST, each with its worktree, its box resources under lease class measure, its clocks and the rules): lane A history (a603a938582c43ab5; the first cut docs/analysis/class-v6/history.md by 15:00), lane B the hardware future (a4f73e2a6f2d1b757; hardware-future.md by 16:00), lane C invention (a5dfe95ee8c47cd0f; invention.md by 17:00), lane D the family gate (a07a99a3788566af2; family-gate.md by 17:00); each feeds the research lane's synthesis docs/design/class-v6-rotating-family.md by 20:00 (its outline by 13:00; the hash lane's per-tier rows by 16:00); the full reports by 09:00 tomorrow; the coordinator's lane mirror carries their clocks. A HELD PUSH AND ITS CAUSE (11:00 BST): the hash lane's push of ca3-v4-amend was refused at 10:58 by the gh-account hook reading the founder's gh (his personal login active again; nothing switched by any lane); the cause is the branch's own hook, which predates the per-process fix (34b0884d): the hook runs the branch's tools/ci, so every branch older than 09:58 must merge the mirror's master before its next push, under which the check reads Igneum's own gh directory and skips under the suspension marker; the rule to every lane. Live: the Arc re-read on PC 2 (published 10:59:47) and the v5lock job on PC 1 (published 10:53, about 12 minutes). THE CLASS V6 OUTLINE ON THE MIRROR (the research lane, docs/design/class-v6-rotating-family.md on counter-asic-4, the commit after fb61ed4b, pushed 10:5x UTC, two hours ahead of 13:00): section 0 the founder's table (per layer, what it does to a fixed-function chip and to a GPU-like chip on its release day, and the 5090, 5070 Ti and M5 Max columns, measured where the night's rows exist, the 5070 Ti scaled until the hash lane's row); the honest frame on top: the four layers render a FIXED-FUNCTION chip useless on the first era its wired value leaves (one tape-out lives one era) and move nothing for the stored-dataset chip with a programmable core except the core's size and the N5 project it forces; that chip keeps 3.6x at zero premium and 2.1x at k = 1 on a 5090 at its knee. The layer table (sections 1 and 2) names the bands each draw takes and the measured rows that set them: the mixer in {4, 8, 16} (x16 open), the op-mix weights within B = 4 with shuffle and mulhi capped (shfl 55.8 pJ per op), the read width in {1, 4} words (w64 excluded by the 5 October rows), the block shape 64 to 256 (never 1,024), N left to the ladder's signal (an unconditional draw retires the Apple tier at 200,000). Open numbers asked of the hash lane with defaults at 16:00: the 5070 Ti row (the rented 5070 scaled), the x16 mixer's verifier and build (the chip model's estimate), two re-weighted shadow packs for the op-mix band (the microbench arithmetic). Layers 2 to 4 and the gate plan are skeletons with their sources named, filling by 18:00 with the four research lanes' cuts, the synthesis by 20:00. THE FOUNDER'S WORD AT 11:2x BST ("all builders are idle, load them up"): build-1 to build-4 filled now and kept above 80 percent all day under the lease pool, class measure behind the release gates, in this order of value: (1) the class v6 family gate's sampling runs for lane D (the F8-form census and the (c''') floor over the parameter bands: the mixer {4, 8, 16}, the op-mix weights within B = 4 with shuffle and mulhi capped, the read width {1, 4}, the block 64 to 256; thousands of drawn eras, the uniformity and bucket tests on each, so the family document carries measured coverage tonight); (2) the attack families at scale on the 0.3.25 pin candidate's igneum-pow (F8 to 256 seeds, F9 and F1 to 10^6 on the frozen 1c420786, the day-key scan to 2^28) as the record's strengthening lines; (3) the invention lane's candidate layers measured as packs as fast as it writes them; (4) the full suite matrix of the 0.3.25 pin on every box as the pre-pin check; (5) the Windows and hive cross builds and the sweep's reruns; the lease tool's pre-emption giving release-class work the cores when the pin's gates need them; one line to main at 12:00 with the load on each box and what runs there, then hourly only if a box drops idle. THE DRIFT CLASS SETTLED (the node lane, from the fleet's fresh-walk node, a shared-devnet node synced from an empty datadir to 191,441 chain blocks at 10:03:45Z): hub-1 and five standing boxes number the fresh chain exactly; seven boxes carry numbering inherited from an exec snapshot taken on a chain that later re-walked (+2: p1-4090, p1-a5000, pool-1, build-1's node1; +3: p2-3090-2; +4: p2-3090-4; +5: p1-5090 and p2-3090-3), and a restart on the kept datadir does not re-walk (p1-5090 at 09:22Z stayed +5); the cost: a prover on drifted numbering signs statements the hub vetoes, so the seven earn nothing from proving until they re-walk, the drift refusal stopping the waste. The node lane's word to the fleet: p1-5090 first, both snapshot files moved aside so the executor re-walks from the DAG, the re-walk timed and read against the fresh node, then the other six in series, hub-1 untouched, build-1's node1 after the 12:40Z move; if the re-walk reads over two hours the six wait for the node-side fix on the next node line (the loader re-numbering a resumed range against the DAG before serving). THE 0.3.25 PIN CANDIDATE CONFIRMED (the node lane): e0644958 on both mirrors (keygen, the re-announce, the ceiling switch at 82,800 in the Devnet 3 object, digest 1b37cb9d, the 0.3.24 pin refused both ways), every gate green at 09:53:01Z, the fast-time SUMMARY PASS at 09:54:40Z on the same object; the publish ceiling DAA 75,600 (14:53 BST); waiting only on the 68,400 crossing reading clean (about 12:54; the node lane's line the moment the DAA passes it); the shipper names the pin at 13:00; the TESTNET_PARAMS re-cut at 13:30 unless main says otherwise by 13:15. LANE C'S FIRST PACK (the invention lane, 11:0x BST by the Mac's clock; its own line read "12:1x", a clock to correct): build-1 takes the igneum-pow build from counter-asic-4 at 5984ffab, then the per-load shadow in its sound form (mx8+shl6912x1: 16 sub-blocks of 432, one pass, the form 20.2a named and never drew) as the first candidate: the acceptance census over 64 seeds and 16 drawn eras against the 16x27 form and the class v4 shape, the pack export, the F8 read at 2^24 and the verifier bench on a leased core, the first read by 13:30; build-2 next for the second candidate (warp-uniform data-dependent block selection); the candidates with no pack form (the VDF commitment, the VRAM ratchet, the pool-sampled witness, the state-tied reads) stay modelled and the 17:00 cut says so; the worktree igneum-wt-v6-invention on class-v6-invention. THE WINDOWS INSTALLER CLASS AND THE 0.3.25 TIP (the shipper, 11:08 BST): the app tip 139c147a (9b93e649 plus install-detach-25 52a34111, packaging/windows and tools/ci only, the crate unchanged; push gate GREEN); the 0.3.24 take 2 class: an installer started under the app's job runner is a child of the engine, and the engine's kill_tree on quit ended it between PrepareToInstall and the copy; the fix re-launches the installer as a one-shot scheduled task outside the job's tree; the 0.3.24 Windows entry skipped; the rule-14 take on PC 2 is the 0.3.25 installer over the running 0.3.21 app, queued ahead of the Arc re-read; the pin candidate e0644958, the DMG 501ba293 staged, the 13:00 pin and the 13:40 provisional minute standing. THE ATTACK FAMILIES AT SCALE (the attack-pass lane, cores held at 11:08 BST, every run under lease pool class measure): box 2 (88 cores): F8 seeds p66 to p257 (192 new, 256 with the gate's p2 to p65) at 2^24 on class v5 at the freeze 1c420786 (the gated binary 0f5c98dc, pairing e5a4ac5978462156; the leaves re-run on 8f481459 if the kit pairing flips), the window-model control, by-site, as three thirds of 64 seeds; box 4 (80 cores held, 16 asked): F9 to 10^6 on 1c420786 (seeds 100,000 to 999,999 in six chunks of 150,000 at 8 threads, four running), F1 to 10^6 class v5 programs on 1c420786 (one census at 40 threads with the progress line and flushed partials, re-drawing the record's first 10^5 on the way as a reproduction check), the F4 day-key scan to 2^28 on 8ca66afa's redraw rule at 8 threads; nothing on build-1 or build-3 (lane D's); the projections: F4 about 2 to 3 hours, F8's 192 seeds about 9 hours, F9's 900,000 and F1's 10^6 about 30 hours each, so the 17:00 default is partials for those two with the lane (d) rows carrying counts so far; any pre-emption by release-class work reported. THE RPC AND THE 0.3.25 PAIRS ON THE PIN CANDIDATE (the build-server lane, 11:0x BST): rpc.devnet.igneum.network up since 11:08 BST (the first of the founder's builder clocks, 52 minutes ahead); the 0.3.25 pairs on e0644958 running on build-1 since 11:06 (the app tip 139c147a), the Windows and hive crosses on build-2, build-3 and build-4 as reproducibility rows at class release by about 12:40; the sweep reruns' list not held by the lane, the default at 12:30: last night's sweep logs on build-1 read for rows that ended without a result line and those rerun at class measure. THE SWEEP RERUNS' LIST (the fleet lane to the build-server lane, 11:1x BST): the fleet ran nothing under the build boxes' lease pool last night (every fleet bench a rented GPU one-shot), so the rows the lease kills cut short are the hash and class lanes' and the build-server lane's default read on build-1 is the right one; the fleet's own rows without a result (A10, A40, A100 40 GB, H100 NVL, H100 PCIe, MI250, RTX 3050, RX 7800 XT, 7900 XT, 7900 XTX, 6900 XT) are provider gaps needing a GPU host, rerun the moment a provider lists one. THE CLASS-FLIP TIERS, BOTH HALVES (the UI lane, 11:13 BST by the Mac's clock, 1 h 47 min inside the 13:00 pin): tiers-class-25 at 081b3ba7 (the display d949e274 plus the hash lane's ember-tiers-25 0a838072, on release-0.3.25's 9b93e649; the field names matched exactly): the crate gate GREEN 305 + 35 + 8 on build-1, the pre-push GREEN 60, the UI tests 78 green known-failed first, the push gate GREEN; with the shipper. A RED ON THE RELEASE TIP, for the shipper and the update-return lane: release-0.3.25's 139c147a is red on one crate test (ota::return_tests::no_relaunch_while_an_installer_runs_and_a_relaunch_when_it_clears, 304 of 305): install-detach's 0c588b09 reshaped the installer's clear step into a multi-line block while the test asserts the one-line literal at app/igneum-app/src/ota.rs:1348; 9b93e649 passes; the fix is the test's literal on the install-detach line; the UI lane built on 9b93e649 so its tip is green alone. A RED FROM THE PIN MATRIX (the CI steward, 11:13 UK): the core suite fails on the pair (the node e0644958 with the app tree 9b93e649): config::params::tests::fast_time_60x_file_is_the_devnet_at_60x panics "override-60x.json lacks the field base_unit_decimals"; the field was added by 0e4ec18a on ca3-v4-node yesterday at 21:45 UK and reached neither master, release-0.3.25 nor the app tip while the node line's test demands it; so every box reads red on core, and the fix is one line on release-0.3.25 (the cherry-pick of 0e4ec18a, or "base_unit_decimals": 8 in infra/fast-time/override-60x.json); sent to the shipper; green so far pow and app on build-1 and build-3; the two new boxes' toolchains read the same as build-1 (Ubuntu 24.04.5, glibc 2.39, the pinned rustc, sccache and lease, no nvcc). The founder's fourth load item paid in its first ten minutes: a red no single-box gate had read. MAIN'S WORD ON THE TWO REDS (11:1x BST): the install-detach fix belongs in 0.3.25 if it can make it, since a Windows install by any path that lets the engine's job runner kill the installer mid-copy is the plug-tune-play fault class (an update a user repairs by hand); the default order: the update-return lane fixes the ota.rs literal by 12:00; if 139c147a plus the fix is green on the crate gate by 12:15 the cut goes from it, else from 9b93e649 with the detach on 0.3.26 and the record saying Windows installs by job stay unreliable until then; the missing 60x field: the CI steward lands the one-line field on master and the release line by 11:45; the pin slides under the shipper's authority inside 14:53. THE DAY-KEY SCAN TO 2^28 (the attack-pass lane; class-v5 8ca66afa's redraw rule, build-4 under lease pool 8 class measure, 379.2 s, census-2p28.md at 10:15Z, 11:15 BST): days with any gain over 1.1x: 0 of 268,435,456 on M1 (median 226), 0 against the mean, 0 on M2, 0 on ROT and RC; the M1 cost mean 225.791, sd 6.073, min 206 (day 27,016 at 1.0971x, the redraw rule's floor: no day under 206 in 2^28), max 258; every weak class on its analytic expectation (ROT any pair summing to 32: 160,354,008 against 161,256,979; RC any zero: 1 against 1.0, at cost 234, no gain; RC with rk = 0: 87 against 72, 1.8 sigma; the two cells under expectation the rule's own refusals). PASS: no chip buys a weak day in the first 735,000 years of days; at most 1.097x on the best day. The row and f4-weakday.md section 10 committed on attack-pass at eabb4b0e, the push held by the branch's old hook (the fix: merge master, under which the check reads Igneum's own gh directory and skips under the suspension marker). THE SWEEP RERUNS' READ (the build-server lane, 11:18 BST): build-1's records hold no hash-lane or v5-lane run the pool cut short (preempt.log: three TERMs all night, every one to an adv-class holder pre-empted by a release gate, not reruns by rule; no reaped.log; builds.jsonl for 18:00Z to 09:00Z 150 rows with no signal end, the non-zero rows the fast-time gate's designed failed cases and build errors; the census and fingerprint suites leaving no builds.jsonl row and no output directory ending without its result); live at 11:17Z the family gate's v5_attempts_census holding 24 cores on build-1 at class measure; the default at 12:30 if neither lane names a run: no reruns, the boxes carrying the e0644958 reproducibility crosses (build-3's Windows pair already read: igneumd.exe 4b0c3aeb, igneum-miner.exe b3da4088) and the gates. The founder's fifth load item is therefore the crosses, not reruns. The attack-pass branch merged master and pushed (460fd9fa, the F4 2^28 row and f4-weakday.md section 10 on the mirror; the hook skipping the gh read with its suspended line; nothing switched). THE FAMILY GATE'S FIRST COVERAGE (lane D, 11:2x BST by the Mac's clock; its own line read "11:3x"): the harness live on build-1 under lease pool class measure (scripts and pinned binaries under /srv/builds/adv-family-gate/): (1) the base control v5_attempts_census on the shipped class v5 draw over f8-label seeds 1,000 to 11,000, 24 cores since 11:16; (2) the family harness family_gate_era_census (branch family-gate-v5 = class-v5 8f481459 plus the harness, never a chain path; the acceptance keyed on the family's shapes behind IGNEUM_FAMILY_GATE): one drawn era per seed, every layer-1 parameter from the era's own stream (the shadow block {64, 128, 256} x {108, 54, 27}, the mixer {4, 8, 16} recorded, the read width over {1, 4} words, the ten weights within B = 4 with shfl and mulhi never raised), the chain draw through the real rule with every candidate's first failing part, then on the accepted program at the rule's own 2^20 sample the (c'')/(c''') ratio, the largest 256-item bucket per site (ratio and sigma), the index-bit bias per site in sigma; the 16-era smoke run PASSED at 11:21 (about 10 core-seconds per era; 10,000 eras about 28 core-hours). THE WORST READINGS IN THE 16: (a) the index-bit bias read fires HARD on 7 of 16 eras, |z| 130 to 511 at one site, every one at address bit R (the era's stride rotation) or R+1 (era 15 with R = 25 bit 25 z -511 at P(bit) 0.25, a product's bit 0; era 7 R = 17 z -468; era 5 R = 26 z -440; era 13 R = 1 bit 2 z -255, a product's bit 1 at 3/8; era 1 R = 6 z -224; era 12 R = 5 bit 6 z -130; era 6 R = 18 z +256, an or-shaped source at 5/8), the other 9 under |z| 3.8: adv-cache-2's era-stride class measured at the acceptance's own sample on class v5 accepted programs: not diffuse at the bit level, a 25 percent bias on one address bit of one site in about 40 percent of drawn eras, which (c''') does not see (min ratios 0.9954 to 1.0000); a chip holding the favoured half of that site's window serves 75 percent of its reads instead of 50, about 1.6 percent of a hash's reads at f = 1/2 for one site, which does not move the f = 1 verdict but is an auditor's flag on "uniform random reads"; the lever is load_index's form (fold the product's low bits before the rotation), not a floor (a 6-sigma refusal would redraw about 40 percent of epochs): a class v6 design row. (b) The (c'') ratio min 0.9954 (era 7), the rest 0.9965 to 1.0000. (c) Attempts: 14 of 16 accepted at attempt 0 or 1; era 9 (shape 64, width 4, mul 11 and or 8 of 75) took 24 candidates: the lossy corner raises r, the exhaustion number to read per stratum. (d) The largest 256-item bucket: ratios 2.2 to 2.4 at full-window sites are the CLEAN maximum (65,536 Poisson(16) buckets, +4.4 sigma), so the F8-tail bound must be stated in sigma, not ratio (the sigma column in the rebuild). Next: the random stratum (10,000 eras) and the corner strata (the lossy cap, width 4, shape 64, 3,000 each) on build-1's free 64 cores, then build-3 and build-4; the first cut of family-gate.md drafted, the measured coverage table in at 16:xx for the 17:00 cut. THE OTA TEST LITERAL FIXED (the update-return lane, 11:23 BST, ahead of both clocks): ota-test-25 off release-0.3.25 139c147a, tip 53cb2f73 on the mirror, one test-only commit (the test reading the installer's clear step as the begin/end block the detach made it; the detach's behaviour kept), the box 2 crate suite 303 + 35 + 8 passed, 0 failed, the full gate GREEN 60; the shipper's cut tip 139c147a plus this commit, so the install-detach rides 0.3.25 and the PC 2 rule-14 take runs on it. THE 60x FILE, THE WHOLE FILE NOT ONE FIELD (the CI steward, 11:25 UK): the test names the first missing key in key order; with base_unit_decimals in it named emission; the file on master and release-0.3.25 lacks six keys the 0.3.25 node line's OverrideParams has (base_unit_decimals, pool_split_activation_daa, program_class_v5_activation_daa, proving_base_fee_ceiling_multiple, proving_fee_ceiling_activation_daa, subsidy_per_block_activation_daa); ca3-v4-node's copy (81 keys, master's 75 plus those six, no shared value differing) passes on build-3 by hand; release-0.3.25 got the one-field commit 907fdaf4 at 11:23 and the whole-file commit follows through the hook's gate, master the whole file behind the one-field landing; the known-failed on record on all four boxes; the green from the core re-runs in the 12:30 matrix; the risk named to the shipper: an older daemon reading the file with deny_unknown_fields. THE INDEX FOLD AS A CLASS V6 DESIGN ROW (the research lane, docs/design/class-v6-rotating-family.md on the mirror, the commit after 206e81e1): load_index folds a product's low bits before the stride rotation so no era's R lands a biased bit on an address bit (a design row, not a draw and not a floor); the evidence lane D's 7 of 16 drawn eras at |z| 130 to 511 on address bit R or R+1 with the (c''') ratio blind to it; the chip row 1.6 percent of a hash's reads at f = 1/2 for one site and zero at f = 1; the cost 0 on every card (one xor-rotate on the address path); the known-failed test lane D's 7 of 16 reading 0 of 16 with the fold; the value-level bias test in layer 4 ordered after the fold as its guard; the F8 tail's largest-bucket bound restated in sigma against its own window's Poisson expectation. The 60x commits: the one-field commit on both lines (master 7be52d76 at 11:24, release-0.3.25 907fdaf4 at 11:23), the whole-file commits in their gates behind it (release cbbaa8c4 pushing, master's queued). CLASS V5 AT THE KNEE ON THE 5090 (the hash lane, run-ca3-pc1-v5lock-5090-20261008-b, 11:09 to 11:21 UK, the 5090 alone, the v5 kit's CUDA worker on the rotate-fold build 8f481459, 60 s rows, the cleared helper sequence; an hour ahead of main's 12:30 clock): the same genesis seed, class v4 against class v5: unlocked v4 135.82 MH/s at 458.3 W (0.296 MH/W), v5 135.90 at 474.3 W (0.287); at 1,300 MHz v4 125.92 at 294.0 W (0.428), v5 125.93 at 299.8 W (0.420); at 1,200 MHz v4 115.69 at 273.3 W (0.423), v5 115.87 at 278.6 W (0.416); the Devnet 3 epoch-0 v5 pack (another seed, the fingerprint 82b19cbde8557ea5 matched on every row): unlocked 136.94 at 494.4 W, 1,300 134.10 at 315.6 W (0.425), 1,200 128.51 at 302.2 W (0.425). THE READING: at the knee class v5 loses 0.0 percent of rate against class v4 and costs 2.0 percent in watts (1.9 percent per hash), under main's 2 percent line, so the v4 knee stands, the tiers table says the class v5 rows are within it, and the UI lane's knee note stays off (knee_loss_pct 0 on the 5090); the A4000's 17 percent is a capped card's number: the 5090 at 1,200 MHz holds v5 level with v4 too, so the loss appears only where the power cap, not the clock, is the limit. Per tier for the founder: a 5090 or 5080 owner on a knee lock loses nothing at the class v5 crossing; a power-capped card (a datacentre card at its cap) loses up to 17 percent until its cap is raised or its class re-tuned. The 5080's rows after the v6 packs job if wanted; the AMD grid live on PC 1 since 11:25 (24 points, about 32 minutes). LANE B'S FIRST READING, RELAYED BY MAIN (11:2x BST), WHICH CHANGES THE CHIP MODEL AND LEADS THE 20:00 SYNTHESIS: a 2 GiB SRAM full store on one N2 die (about USD 500 of silicon, an N2 project of USD 100 M to 500 M) reads 13x to 17x the 5090 per joule at zero shadow and 2.7x to 4.8x with the shadow at the measured k band; layer 2 (the dataset tracking chain state) moves its capex, not its joules; the custom HBM4E base die (2027 to 2028) 6.5x to 14x, untouched by the four layers; PIM structurally blind to dependent random reads; and the M5 Max at 3.1x the 5090 per joule is the honest denominator. MAIN'S ORDERS: (1) chip-model-v3 gains the SRAM-store row and the HBM4E base-die row with lane B's figures and their claimed or measured marks; (2) the synthesis states the per-joule edge against the SRAM store honestly (3x to 5x with the shadow) and against the M5 Max, and prices the one layer that answers it: a dataset floor that grows on a schedule faster than SRAM cost falls, with the cost to a 12 GB and a 16 GB GPU and to 16 GB unified Apple memory stated; (3) the served chip line ("2.1x per joule at the knee") is reviewed at 20:00 with the measured basis for each clause; no served text changes before the synthesis, and if the SRAM-store reading stands the line becomes the honest range with the project cost and the clock beside it. THE SHIPPER'S THREE READINGS (11:2x BST): (1) override-60x.json: every reader in the tree is the fast-time harness, the sims and CI; no daemon on the fleet loads it; the app manifest's consensus.override is a separate 16-key object carried from the live manifest and untouched by the cut; the live chain's object is the digest's (1b37cb9d on e0644958); the harness's file only, the cut stands. (2) The cut tip cbbaa8c4 on release-0.3.25 (907fdaf4 plus the steward's whole-file commit; the crate and packaging trees byte-identical to 907fdaf4's, whose crate gate read 305 + 35 + 8 at 11:24; override-json-check passing): amd-clock-25 e2962b89, tiers-25 d3d0704a, the Intel header, the tiers class-flip pair 081b3ba7, install-detach-25 52a34111 with its test fix, the node-source pin e0644958, the host bc8d4f79, the fast-time file; the Mac DMG on it afa7f527 (45,766,741 B, the node pair 556926b1/d2dfe966), staging. (3) The knee note off on the 5090 rows. The pin at 13:00 on e0644958 and the 13:40 provisional minute standing; the matrix on cbbaa8c4 and e0644958 the steward's by 12:30. LANE B'S FIRST CUT ON MASTER (34f63b3c at 11:25 UK, four hours and thirty-five minutes ahead of its 16:00 clock): docs/analysis/class-v6/hardware-future.md with the three findings and the k bands (with the research lane, into the synthesis's section 7a on counter-asic-4 at ad37a50c); lane B's four decisions in its section 7 with defaults (the draw bounds by 20:00 via the synthesis; the dataset schedule unchanged; the M5 Max as the reference joule; the clock unchanged); nothing built or benchmarked, gh untouched; the full report by 09:00 adds detail only, no k band moving. LANE A'S FIRST CUT ON MASTER (docs/analysis/class-v6/history.md, 300 lines, merge 4c58ad65 at 11:26 UK, three and a half hours ahead of its 15:00 clock; the full gate GREEN 73 checks; primary documents read from the PDFs: the Least Authority and Bob Rao audits, Kik, EIP-1057, the RandomX design and v2, Tromp's README, the Fudan Equihash solver, Percival's lookup-gap note): 21 chip rows by mechanism (what each chip specialised, the miss, the timeline, the v6 layer, closed or not, the per-joule number), the in-depth sections (Ethash, ProgPoW, RandomX, Cuckoo, Equihash, Scrypt and Argon2, the no-chip hashes, kHeavyHash, CryptoNight, X16R, Lyra2REv2, the compute rows), the four layers against the history layer by layer, the tier consequences. THE HONEST VERDICT WITH THE NUMBER: the chip that stores the dataset (class C: every Ethash chip, the E3 at 1.0x, the Linzhi at 2.1x, the Jasminer X4 at 5.1x via DRAM hybrid-bonded onto a 40 nm logic die, the E9 Pro at 4.1x) is NOT closed by any of the four layers, every per-era draw and family epoch being firmware to it; v6 inherits 5.1x per joule on GDDR7 at zero premium (3.6x at the 5090's knee, 2.1x with the class v4 shadow at k = 1), USD 2.8 against 14.7 per MH/s; classes A, B, D's governance half and E are closed, mostly since v2 and v3. THE THREE LESSONS THAT BIND: (1) the stored-dataset chip is firmware-immune to every draw; only joules and memory growth move it; (2) automatic change beats the human fork only where it costs the chip a redesign, and the one such parameter is the memory: layer 2 as declared is not an anti-chip rate (a 32 GB board lasts 60 years at 0.5 GiB a year; the 8 GB card is out at year 12; the E3 the only chip a growth rule ever killed, 20 to 27 months after shipping, at the fleet's own 4 GB limit), so its floor and a per-tier ceiling are the numbers to fix, not the rate; (3) a steered address pattern is always found after launch unless the test lives in the acceptance rule, and every drawn parameter changes layer 4's null, so the census re-derives per era (2.2 s per candidate). CORRECTIONS TO THE 5 OCTOBER FILE: the Antminer X9 withdrawn May 2026 with zero units (not "July 2026 delivery"); RandomX v2 released 25 March 2026 with activation pending (not "no fork"); CryptoNight's secret chips at about 33 months, not 43; Vorick's "survives forks at under 5x" and "13 months for a startup" on no fetched page, marked unverified. Two asks with defaults: layer 2's ceiling (if no word by 20:00 the full report drafts it as GB per tier per year keyed to card-lifetime-2026-10-05.md, with the flag that a dataset tracking state literally outgrows every card inside a decade if state grows as Ethereum's did); the hardware file cross-cited, not repeated. The lane's web-search budget spent (200 of 200); further additions by direct fetch. LANE D'S STATE (11:2x BST by the Mac's clock; its own line read "11:5x"): the first cut committed on class-v6-family-gate at 55c0dc6a with the full gate running; the census at 640 random eras, 298 lossy-cap, 327 width-4 on build-1 and about 500 shape-64 on build-3, the two build-4 corners queued behind a full pool; the landing on the gate's GREEN, the measured coverage table in the 17:00 cut. THE SNAPSHOT DIGEST STAMP (the node lane, 11:2x BST; a wip on release-0.3.25-node under its suites since 10:28Z): every snapshot a node writes carries its consensus digest as a new last field (the day-streams field's fallback shape, so 0.3.24 files decode with no stamp); a node with its digest set refuses a snapshot stamped under another digest ("re-executing from genesis") and one with no stamp ("written by a node before 0.3.25"), the follower starting at genesis; the daemon sets the digest from its params; the tests known-failed first (another digest refused, an unstamped file refused, nothing loaded; a matching stamp resumes, the written file carries the stamp, a digest-less process resumes as before, the wire round-trips); if the suites read green the full gate set runs and it is in the pin at 13:00 BST. THE CONSEQUENCE FOR THE MOVE: every Devnet 3 node restarted on 0.3.25 re-executes from genesis (no file written before 0.3.25 carries a stamp), so the restart takes the chain's re-execution time, which a fresh 0.3.25 node on build-1 since 10:24Z measures now (about 30,000 chain blocks; the rate in the pin line). TWO READINGS BESIDE THE CAUSE: (a) build-1's three nodes differ at 26247 (node1 0x3f53a7b9, the seed 0x717e7dc8, the observer 0x4548c319), and the seed and node1 differ at block 0 already (0x275b0cce against 0x7e37a9fb), which the ba75bf6f file alone does not explain (both resumed their own files across the same restart; the seed also restarted at 02:00Z on 2720d8d2 from a 0.3.22 file); the fresh node's genesis root and its first divergence from each decide whether a second class (an older-object file on the seed, or the resume itself) is in play; (b) the fleet asked for the roots at 26247 and 15611 on hub-1's Devnet 3 node, dn3-g1 and every prover by 12:30 BST with each node's resume line. The loud status for a vetoed node (a veto counter, the last veto's line on the explorer's status, "state not fresh") on the same line if the suites leave time, else 0.3.26, the node lane's word at 12:30. MAIN'S WORD ON LANE A'S ASK (11:2x BST): the default stands (the GB-per-tier-per-year table keyed to the card-lifetime file, with the flag), and one schedule to price beside it so the 20:00 reading carries a decision: a dataset floor of 6 GiB at the v6 epoch (every 8 GB card keeps mining with its cache; the 6 GB 2060 tier drops), 10 GiB two years on (the 8 GB tier drops), 14 GiB at four years (12 GB drops; 16 GB and Apple 16 GB unified hold), each step by height like a class epoch, the schedule itself a consensus field, with the cost per tier stated as the year each falls off and the share of today's measured cards that is; against the chips: the hybrid-bonded DRAM chip sized at launch (the E3 class) dies at the first step it cannot carry, the SRAM store pays capex only, both said. Lane A's corrections to the 5 October file go into the record and the served texts tonight. MAIN'S WORD ON THE STAMP AND THE GENESIS CLASS (11:3x BST): the stamp rides the pin; the re-execution time goes in the pin line and the move plan per tier; the fleet staggers the restarts in thirds so the proving share never reads zero, and the hourly line says "re-executing" with the count until the last prover is back. The second class is a GATE, not a note: the seed and node1 differing at block 0 means one of them runs a different execution genesis, and a hub node on a wrong genesis is worse than any snapshot drift; the pin is not named until the node lane says which file each of build-1's three nodes and hub-1 loaded at genesis, which root is the network's (the fleet's roots at 26247 and 15611 decide it), and the wrong one is corrected or re-walked; if that is not read by 13:00 the pin waits inside the 14:53 ceiling and the shipper slides by its authority. The vetoed-node status rides 0.3.25 if green, else 0.3.26. THE 60x FILE LANDED (the CI steward, 11:31 UK, ahead of 11:45): release-0.3.25 cbbaa8c4 (the whole 81-key file on 907fdaf4, the hook gate GREEN 60) and master e295c0d5 (the same file, the gate GREEN 73); known-failed to green on record: core RED on the one test on all four boxes before, core GREEN on the fixed pair on build-1, build-3 and build-4 after, build-2's re-run running; the full matrix by 12:30. A NEW GATE ON THE PIN (main, 11:3x BST, from the reference-apps lane's read): node1-dn3 and the re-executed observer diverge from chain block 26294 at DAA 60,578, the 10:05 move minute; node1 executed a block the selected chain later dropped and never unwound it, so its numbering runs one high and its state and records diverge; that is the drift class and the likely cause of last night's proving collapse after a move; the stamp does not cure it. The node lane's order: a known-failed reorg test under the exec follower, the fix on release-0.3.25-node if green by 13:30, else the move with the mitigation (every node re-executes from genesis after the minute, the vetoed-node status loud) and the fix as 0.3.26 tonight; plus the roots census to count stale nodes for the fleet's re-walk before the minute; the shipper's slide authority covers the pin inside 14:53; if the fix needs past 14:53, the floor re-cuts from the next minute by the same authority; the explorer lane reads block numbers from the observer node only (the chain the certificates follow) until the fix is live. THE FAMILY GATE'S 12:00 COVERAGE (lane D, 11:3x BST by the Mac's clock, ahead of its clock): 4,900 drawn eras through the per-era tests on three boxes (build-1 random 1,444 and lossy cap 663 at 10 core-seconds per era; build-3 shape 64 at 2,162; build-4's two lossy corners queued behind a full pool); the full gate on the first cut GREEN (73 checks, 381 s), the landing on one re-gate after a merge conflict on export-exclude.txt with the research lane's line (resolved, both kept). THE WORST ERA PER TEST: (1) THE EXHAUSTION BOUND BREAKS AT THE LOSSY CORNER: with or, mul and mulhi all at +4 points (30 of 75 lossy against the table's 18), r per candidate is 0.956 (the table's 0.681) and 8 of 663 eras EXHAUST the 256-attempt cap (mean attempt 18.6, max 252), so 1.2 percent of epochs at that corner would take the last-resort program, which adv-accept-3 showed fails rule (a) in 9 percent of seeds; B = 4 with the lossy ops free to rise is therefore outside the band; the random stratum at B = 4 (every weight drawn, lossy ones included) reads r = 0.718, max attempt 107 and 0 exhaustions in 1,444, but 107 attempts is 4x the shipped max of 28; the ring-A rule the cut carries: the sum or + mul + mulhi at most the table's 18 plus B, so r stays under 0.85 (r^256 under 1e-18); the default by 17:00: B = 4 on the injecting families only, the lossy families capped at their base. (2) THE ERA-STRIDE CLASS AT THE BIT LEVEL ON THOUSANDS OF ERAS: 52 to 58 percent of accepted programs in EVERY stratum carry one site whose address bit R (or R+1, R+2) is biased at over 6 sigma at 2^20, 33 to 40 percent at over 100 sigma, the worst z 1,024 at bit 7 of a site under R = 7 (a product's bit 0 at P = 1/4 landing at bit R): adv-cache-2's mechanism at half the family's epochs on programs (c''') passes (min ratios 0.9950 to 1.0000); the chip price per site about 1.6 percent of a hash's reads at f = 1/2 against the partial-store curve's 1.26x ops cost: the f = 1 verdict stands, the "uniform random reads" sentence does not; the catch structural (the index fold in load_index before the rotation, the class v6 design row), not a floor. (3) The largest-256-item-bucket excess: clean full-window sites +4.4 sigma; the worst eras +94 to +128 sigma at one site (the F8 tail's quarter-bit class at scale, the same mechanism: the bucket at the biased bit); the bound in sigma from the clean spread in the 17:00 cut. (4) The (c''') refuse rate per stratum: random 2.56 percent of candidates, shape 64 3.41, lossy 0.42 (the lossy rejections earlier at (a')); 0 accepted programs under 0.995 anywhere. (5) VOID and rerun: the width-4 stratum ran at width 1 (the era's one-entry allowed set redrawing to the base's width; fixed, the harness rebuilt, restarted at 11:5x with its own label space); the first corner strata sharing the random stratum's label space coincide with its draw a third of the time; the reruns use per-stratum labels; both stated in the cut. Coverage by 17:00 at about 1,000 eras per hour per 16 cores: random 10,000, shape 64 3,000, lossy cap 3,000, width 4 3,000 plus the two build-4 corners; the rule-of-three line for the random stratum at 10,000 eras a failing fraction under 3e-4 at 95 percent for every ring-B test. THE V6 COST ROWS (the hash lane, 11:4x BST by the Mac's clock, its own line reading "12:4x"; four hours ahead of 16:00): with the research lane at scratch v4/ca4-v6-cost-rows.md, every row labelled measured or modelled; the layer-2 headlines: VRAM 3.2, 5.4 and 9.9 GiB at the floor, 2x and 4x; a 12 GB card falls off at about 9.5 GiB (year 15), a 16 GB GPU at 13.5 GiB (year 23), a 16 GB unified Mac at 8 GiB (year 12), the 5090 at 29 GiB (year 54); the DRAM-read cost per hash size-independent (the 5090's 1.11 microjoules of 2.29), so the layer moves capex not joules, and the card rows allow a floor of 4 GiB in year 1 and 8 GiB by year 4 without retiring a 12 GB card (main's schedule of 6, 10 and 14 GiB at the epoch, two and four years sits above that: the 12 GB tier drops at 14 GiB, the 16 GB holds); the measured size rows (the v3 pack at 2, 4 and 8 GiB on the 5090, unlocked and at 1,300) ride the v6 packs job after the AMD grid. The AMD grid: the first run refused in 2 s at no_tune_line (the old installed exe, as designed); the rebuilt exe on PC 1 by the update-return lane's fetch at 11:33, the rerun from amd-clock-25 572c3ee0 live since 11:39 (about 32 minutes, the rows about 12:15). The class key on the mirror (ember-tiers-25 0a838072 in tiers-class-25 081b3ba7, with the shipper since 11:13, inside the 12:30 reading). The Arc read waits on the shipper's PC 2 take; the 12:30 default "no Arc read" stands unless it starts before. THE DRIFT CLASS READ FROM THE LOG (the node lane, 11:4x BST): at 09:42:09Z node1-dn3 accepted 0x6aa6 (DAA 60,578) and at 09:42:10Z 0xb708 (the same DAA and blue score 60,265, both children of 0x0fed at 26293: a tie at one height); its follower executed 0x6aa6 as chain block 26294 (28 transactions) and 1.1 s later 0xb708 as 26295 (the same 28 skipped as already included), with no reorg line between; every consensus view now (the seed, node1 itself, the observer) has 0xb708 as the chain block with the selected parent 0x0fed and 0x6aa6 off the chain, so node1's records hold an orphan at 26294 and number everything after it one high, and its state root diverged from there (the observer, re-executed from genesis, agrees with node1 to 26293). THE GAP: the 0.3.22 continuity rules (ledger N15) check the first appended block's selected parent against the tip at append time and scan the whole record set against the DAG's selected parents ONCE per state generation (a restart or a loaded snapshot); a break landing after that scan, as this one did ten minutes after node1's restart, is never looked for again until the next restart; the fleet's +2 on four shared-devnet boxes is the same gap. THE FIX on release-0.3.25-node (a wip under the exec suite since 10:41Z): the self-check runs every 30 s over the ring (the last 2,000 records) against the DAG's selected parents and in full on a generation change, a break handing the records above it to the reorg unwind (the existing branch restoring the ring state at the fork and re-walking); the test known-failed first on node1's exact shape; on the same commit the snapshot digest stamp (exec 51 of 51 green on its wip) and the vetoed-node status (vetoes counted on the status with the last veto's line, stateFresh false while any stands, on igneum_getNodeInfo and the status RPC); the exec suite's green about 11:46 BST, then the named commit, the full gate set, both canaries (the digest 1b37cb9d unchanged: nothing consensus) and the fast-time pair, the gated tip by about 12:30, inside 13:30. What the fix does not do: name why the tie-break flipped under node1 at 09:42Z (its DAG now reads 0xb708's parent as 0x0fed and the path at the time must have read otherwise; the second "PoW accepted 0xb708" line 0.4 s after the append says the block was processed twice), a reading for the record after the pin. The fresh 0.3.24-object node on build-1 past IBD and executing from genesis; its root at 26247, its rate and its memory peak in the pin line. MAIN'S WORD AT 11:4x BST: (1) lane D's band default stands (B = 4 on the injecting families only, or, mul and mulhi at base, the ring-A lossy-sum rule), and the index fold before the rotation with the bias test as its guard is layer 1's rule; (2) the served sentence "uniform random reads" is corrected today, not at the review: the audit lane rewrites it to the measured statement (reads spread over the whole dataset; a bit-level bias at one site appears in about half of epochs; it prices about 1.6 percent of reads to a chip storing half the dataset and nothing to a full store; the next class folds it out), through the gate and the master-only deploy, with the ledger row; (3) layer 2's table splits Apple by memory size (16 GB unified at its 8 GiB limit, 32 GB and 64 GB Macs holding every step), the M5 Max being the honest best per joule and the Mac tier a large audience; the schedule decision at 20:00 is the founder's with that column in front of him. THE EXPLORER'S SOURCE (the explorer lane, 11:4x BST): it reads one endpoint and always has, the Devnet 3 observer node on build-1 (the execution RPC on loopback 26850 through tools/observer/explorer-indexer.mjs, the observer's own dn3 tables on 28650); it has never read node1-dn3, so there was no switch; the indexer on 26850 since 10:04 UTC with a full refill from genesis at 10:33 UTC after the root equality read at block 26,247; the pages now name the observer node as the one source, the chain the certificates follow (on explorer-dn3, in the gate; the merge and deploy follow). THE GENESIS GATE'S ANSWER ON build-1 (the shipper, 11:43 BST): the seed was the odd node (its block 0 from the 0.3.22 binary; the rule change for the node lane's record), re-walked from genesis at 11:35:30 by the shipper's hand (the evm moved aside, the same binary and flags, the kept datadir) and reading population A's roots at 11:43:00 (0x47983bd9 at 15611, 0x3f53a7b9 at 26247, head 26,478). THE MEASURED RE-EXECUTION: 26,478 chain blocks in 7 minutes 30 seconds (about 59 a second over the walk; 100 at the start, 30 past 15,000), RSS 5.5 GB; so the move plan's per-tier line: a prover's node is back about 8 to 10 minutes after its restart on 0.3.25 (30,000 blocks at the minute), a Mac or HiveOS app node the same at its update hour, miners unaffected; with the hub and the seed at the minute and the provers in two thirds at +0 and +25, the proving share never reads zero and the last prover is back about 35 minutes after the minute. The node lane's gated tip (the ring check, the stamp and the vetoed-node status in one commit, the digest 1b37cb9d unchanged) by 12:30; the pin after it and the fleet's census; the minute about 14:10 at the earliest if the fix rides, inside 14:53. LANE A'S SCHEDULE SECTION (history.md 4.2a, master 59963461 at 11:45 UK, five hours ahead of its 17:00 clock; three landings today: 4c58ad65, b645762d with the synthesis lane's six items folded in, 59963461): ONE FLAG on main's schedule with the number: under the standing budget rule (the working set under 6 GB on an 8 GB card, the 75 percent reading) a 6 GiB floor does not fit the 8 GB tier (6,398 to 6,744 MiB, 78 to 82 percent of the card; it fits only at a headless-rig reading of about 85 percent); 10 GiB retires the 10, 11 and 12 GB tiers and the Apple 16 GB laptop at year 2 (not the 8 GB tier alone); 14 GiB retires the 16 GB tier at year 4, leaving 24 GB and above. The schedule that drops the tiers in the order main named, priced beside it: 5.5 GiB at the v6 epoch (6 GB falls, 3 percent of the 32 measured consumer cards), 8 GiB at two years (8 GB falls, 22 percent, with the 10 GB RTX 3080 and Apple 16 GB; 12 GB holds at 69 to 72 percent), 11 GiB at four years (12 GB falls, 22 percent; 16 GB holds at 70 to 73 percent); 24 GB and above hold throughout. Against the chips: the f = 1 GDDR7 chip's 32 GB board pays USD 0 through 16 GiB and keeps 5.1x; the hybrid-bonded or soldered chip sized at launch dies at the first step it cannot carry (the E3's shape, 20 to 27 months) but a maker reading a public consensus field sizes to the step it wants (USD 160 of GDDR7 on a USD 470 part); the SRAM store pays capex only at the cache doubling (USD 46 to 111 per die) and keeps 0.92x and 1.86x. So the schedule is a fleet-retirement rule with a USD 0 to 160 chip tax, killing only a chip whose maker ignores the field. The default by 20:00: the full report carries both schedules and recommends 5.5 GiB as the floor that keeps the 8 GB tier inside the rule. Owed: the fleet's hashrate-weighted card census (the shares are by count of the bench table's 32 measured consumer cards). LANE A'S CORRECTIONS SERVED (the site audit lane, master 2119e4f3 at 11:46 BST, gate green on 78166c6c, commit 14ad1a33; seven hours ahead of 19:00): every served "no chip shipped" and "seven years without a shipped chip" sentence (the litepaper's precedents row, the chip-model paragraph, the vs RandomX lead and its track-record row, the limits section; /claims and /randomx following) now carries the Antminer X5 (September 2023, 1.46x per joule over a desktop CPU, silicon believed mining privately from about 2021) and RandomX v2 released 25 March 2026 with its mainnet activation pending; the ledger rows X34 and C2 corrected with lane A's file cited, the pins moved, the public ledger and page regenerated; the X9 sentence already matched lane A's row (sales opened 26 December 2025, shipping scheduled July 2026, withdrawn mid-May with zero units), the precedents and track-record cells now reading "withdrawn in May 2026 with zero units"; the 43-month, 13-month and Vorick figures on no served page; the commit also carrying main's governance line beside the class v5 sentence and six class v4 watts rows; the "random reads" correction with its AP-F8 row next by 13:30; the build-server lane deploys on main's word. LANE C'S FIRST CUT ON MASTER (docs/analysis/class-v6/invention.md at a9f03598, 11:48 BST by the Mac's clock, five hours ahead of 17:00, with the census script under tools/attack/v6-invention/ and its two TSVs): build-1 ran the per-load acceptance census (11 forms x 256 seeds, twice: no era and drawn eras, 80 s each on 48 leased cores) and the verifier benches; the two packs exported and with the hash lane for PC 1; the second candidate (warp-uniform block selection) has no pack form without a generator change, which the no-code rule holds this week, so its row stays modelled. A CORRECTION TO THE CA4 FILE'S VERDICT, FOUND BY LANE C: the counter-asic-4 crate's per-load acceptance (BiasedIndexBit) counts the era window's fixed top index bits 26 and 27 as biased, so under any drawn era it refuses every per-load program (0 of 256 on every form today, 5,536 of 7,862 bias rejections naming those two bits); 20.2a-close's "1.4 percent accepted, 42 of 64 seeds exhaust" (the per-load class's death at 00:0x) was read across drawn eras and so measured the instrument on most rows; on the no-era census the sound form (16 x 256 x 1) reads 0.927 rejection per candidate and 234 of 256 seeds accepted, the iterated 16 x 27 form 0.989 and stays dead; the one-line instrument fix (skip bits at or above 28 minus the site's k_off) is a research-crate change, made today as a research-only change behind the pack by the coordinator's order, and the sound per-load form's verdict is REOPENED as a measured candidate (its energy and rate rows on the 5090 through the hash lane; chip-model-v3 5.11's note on the per-load closure to be re-worded when the re-read lands). THE REOPENING APPLIED (the research lane, 11:5x BST): the reopened wording in counter-asic-4-research.md (20.2a-close and rank 4), class-v6-rotating-family.md (section 7c as layer 5) and chip-model-v3.md 5.11's note, with one precision: the 22:5x UTC census ran the bare class with no era, so its 0.986 is the iterated form's own no-era figure (lane C's 0.989 agrees the 16 x 27 form is dead); the artefact in any drawn-era read before the fix; the fix already on counter-asic-4 as of 10:5x UTC (BiasedIndexBit judging only the bits inside each site's window mask through verify::window, per site), uncommitted until the suite's line lands (the box-2 slot since 10:31Z), so lane C re-reads on that branch once pushed, not making the change twice; the chip-model 5.12 rows (the SRAM store, the base die, PIM's blindness, the M5 Max denominator) in the same tree, riding the same commit before 15:00. A MIRROR NOTE (11:52 BST): lane B read silent 25 minutes by the mirror; its first cut landed at 11:25 and its next clock is the full report by 09:00 tomorrow, so the silence is its finished state, not a fault; the mirror now skips lanes whose clocks are done. A MASTER-ONLY DEPLOY AT 11:53 BST (the build-server lane, on main's own builder-programme landing d86ea00a: /build, /grants, /faucet, /swap asserted; the served sha a9f03598, master's tip; the checks ok; 38 miners rows): it carried the audit lane's 2119e4f3 (the RandomX history correction with the Antminer X5 and RandomX v2, the governance line, the first six class v4 watts rows), which main ordered served tonight and the audit lane cleared for the next scheduled deploy; the "random reads" sentences not yet corrected as served; the coordinator's trigger stands for the 13:30 correction. LANE C'S KNOWN-FAILED TEST FOR THE INSTRUMENT (11:5x BST): igneum-pow/tests/v6_window_bits.rs, the sound form (16 x 256 x 1) accepting on at least 4 of 8 seeds under drawn eras 0 to 7 with 0 window-bit refusals (0 of 8 before the fix), the no-era bit-0 refusal on seed 3 standing; 2 passed, 0 failed on build-1 against a local overlay of the same nine lines, the overlay reverted, the test file an offer to the research lane's suite; the re-read on the research lane's commit by 15:00; meanwhile build-1 runs the lane's uniformity read at 2^20 nonces on 64 seeds for the two sound per-load forms and the class v4 shape (the F8-form top-0.1-percent item share against a uniform control, the per-site distinct ratio) on a harness over the crate's trace_load_indices (the master F8 tool mirroring class v4's execution order), about 20 minutes on 24 leased cores. THE RANDOM-READS CORRECTION ON MASTER (the site audit lane, bf54b08d at 11:54 BST, gate green on db038279; an hour and a half ahead of 13:30): the litepaper's lead reads "dependent reads spread over a multi-gigabyte dataset that changes daily", the table row "the dependent reads are", the "chain of random reads into a table too big for a chip to carry" sentence standing with the measured clause after it (the 0.995 floor on every accepted program over 4,900 drawn eras; about half of epochs with one load site biased at the era's stride rotation bit; about 1.6 percent of a hash's reads to a chip storing half the dataset, nothing to a full store; the fold before the rotation in the next class); evidence row 18 with lane D's family-gate.md and adv-cache-2's section 2.3 as sources; the ledger row AP-F8-7 (AP-F8-6 taken on class-v5): "Open, priced: 1.6 percent at f = 1/2, nothing at f = 1; the served sentence corrected 8 October 2026", the disposition class v6 layer 1's fold with the bias test as guard; the public ledger and page regenerated; no pinned sentence touched; the fud-ledger's quoted history standing; the build-server lane deploys bf54b08d. BUILD-1 AT 11:55 BST (the coordinator's own read): load 107.6 on 96 cores; the lease table: the family gate 32 cores (the random stratum, 10,000 seeds), 16 (the lossy cap, 3,000), 16 (width 4, 3,000, restarted), lane C's uniformity read 24 of 48; 88 of 96 cores held, none waiting, no pre-emptions in the last ten minutes. THE 11:55 BST LOAD LINE (the build-server lane, all four boxes at the minute): build-1 (96 threads) load 113.7, the pool holding 32 for the family gate's random stratum plus 16 and 16 for its corners and 24 for lane C's uniformity read (88 of 96 held), the release and v5 builds outside the pool; build-2 (96) load 81.3, the pool holding 32 for the attack-pass F8 census (the thirds); build-3 (32) load 25.1, the pool holding 16 for the family gate's lossy-base stratum and 2 for the hash lane's x16 rows; build-4 (96) load 89.0, the pool holding 4 x 8 for the attack-pass F9 chunks 0 to 3 plus F1's 40 and F4 done; no release-class waiter on any box; the builders loaded, none idle. The founder's order at 11:2x is met at the minute: every box above 80 percent of its threads bar build-3 at 78 percent of 32, which the two queued build-4 corners and the next v6 pack take. A SHARED-DEVNET FACT FROM THE FLEET (not this lane's, with the shipper and the infra lane): the Hetzner live seed 188.245.5.161:26611 is still on the old override object (digest eada4bda) 1 h 40 min after the 0.3.20 sweep (the fleet never touches Hetzner nodes, so it was outside the sweep); the 0.3.21 wipe canary c22-1 took five digest-mismatch rejects from it; an app with the packaged peers is refused at the seed and syncs through node1 and the hub only, a fresh joiner with only the seed cannot join, the 14 voters and the hub are unaffected; the owner puts the floor file ov16-floor-900000.json (sha 294f1f80) and the c4459193 pin on it. 0.3.21's STAGING (the node lane): the order dry-merges onto 55768f88 with nothing moving to 0.3.22; the late-join fix is 52e96c94 (70e4601e rebased onto 55768f88, exec suite 33 green with both new tests); f067f7c1, b0444f51 and 437f0438 merge clean in order; 2e32d5f6's one conflict (DST_ADDRESS beside pool-finish's DST_BINDING in consensus/core/src/finality.rs) kept both; the live-file digest eada4bda after each (every switch at never); the staging waits on the shipper's sweep-end word; the re-pin held. PC 2 DOWN AGAIN (main, 16:5x UK): the founder takes PC 2 down for cable work (PC 1 back but his desk); both PCs out of the sweep's waves, each updates on its poller on return; no PC job to PC 1; the Windows G1 completed before the outage, nothing reruns. 0.3.21's SECOND GATE LINE on 55768f88 (sha256 279b1b690e854fc9): the ten-minute mixed-version gate beside the 5899f603 pair, 13:37:40Z to 13:47:52Z, SUMMARY PASS (one digest b0afb2ee on five nodes; 223 new and 381 old blocks accepted by the old hub, 0 rejected; counts equal at 319, 486 and 604 through both clean joins and the restart step at 13:45:22Z; no panic); the node lane's two lines on 0.3.21's first candidate complete, in plan 6.9 on ca3-v4-node; the fleet's set on it (the bare-child 12 GB line, the wipe, the kept read, the cases) is the fleet's. 0.3.21's FIRST GATE LINE on 55768f88 (sha256 279b1b690e854fc9, the string read back; pairing igneum-pow 8c728ca3 at byte 5): the digest gate 13:35:41Z to 13:37:19Z SUMMARY PASS (a89be8a7 on both binaries with the peers; db9a85f9 refused, no peer; the live file's eada4bda unmoved); the ten-minute mixed-version gate from 13:37:40Z, line about 13:50Z. The 0.3.21 order as the shipper sent it: 55768f88; f067f7c1 and 70e4601e; b0444f51; 6eb21fc9; db28d331; then the re-pin from 8bdcbdd8 on the coordinator's word; suites between, the digest read after every one; the mirror's release-0.3.20-node back at the pin c4459193, release-0.3.21-node open at 55768f88. THE LATE-JOIN COMMIT (N9's second half, the node lane): 70e4601e on the box mirror as branch proof-hold-fix, from c4459193, two files (igneum/exec/src/proving.rs, protocol/flows/src/v10/proving.rs); the gap was the fetch side on the joiner (the served record ran the native check against the joiner's trailing exec state before anything was stored, the check refused it, the proof was never held, the body rule read "not held" for 20 s and failed the IBD); the fix holds the proof by hash before the checks (the pool entry still needs them) and the serve side says when it holds fewer than asked; the exec suite 32 passed at 13:26Z with the known-failed shape first, the flows check green 13:28Z, igneumd on build-1 at the 0321 worktree path built 13:32Z, sha256 17649eeb2f7d1290, string read back; with the testnet lane (the resume form, B alone); it joins the 0.3.21 staging as its own commit. THE WIPE CANARY ON c19-1, c4459193 (sha 45be9b02d1b002f5, string read back): FORM END rc 0 at 13:50:53Z. Wipe synced 13:35:50Z (57 minutes, inside the 98-minute class); mining 13:36:00Z to 13:47:07Z, 66 mined, 66 accepted, 0 rejected, isSynced true at the tip throughout; the hub holds 41 of its blocks in its last 700 with 0 rejects (13:47:09Z); the restart on its kept datadir at 13:47:15Z: the old process stopped at once (the new process's first lock line seven seconds after the marker; the watchdog held nothing, the b7cc37e7 fault closed), synced again at 13:48:39Z after 84 s, 109 templates read with max 3,432 ms and 0 timeouts; the kept read on pool-1's 0.3.17 copy on the same pod passed at 13:38Z (the rewrite line once, a clean second start). The pin's set on c4459193: the digest gate PASS, the mixed-version gate PASS, the wipe canary PASS, the kept read PASS, the restart PASS, the 12 GB line proves and verifies (paid is a race, not a gate); CASES END from c20-1 (about 14:50Z) is the last pin line. THE INTEROP FACT stands from the void run: the 5899f603 hub accepted 235 object-byte-5 blocks from the 8097d600 node with 0 rejected, one digest on all five nodes on the live sixteen-field file. The gates: the digest test and the kaspa-pow vector test (the amended devnet epoch-0 id 1a4230699a6b9c60 must equal, c120d7963abdcd96 must differ, the v3 control unchanged) on the box; the mixed-version Devnet 2 gate (the amended 0.3.20 node beside a 5899f603 node for ten minutes on the live file without the v4 fields) after the Mac build; the fresh-join canary the 0.3.20 cut's | | Main's rulings (7 October, morning) | no generator change to v4 on the live devnet; the record's null is the window model with numbers, sent by the hash lane to the attack-pass lane so AP-F8-1 re-gates against it; a fault beyond the model (a low-entropy source at site 15) stops at the coordinator with the two options priced (a 0.3.19 class amendment before the flip, or the flip held at the floor), nothing shipping without the founder's word; the tighter tail, an acceptance bound on the hot-set share, is a CLASS V5 item (sent to the v5 lane a6410f3b8abefb762 with the 64-seed census as its gate; the bound's number follows from the model) |

AP-F4-1, the weak-day MUL draw (the attack-pass lane, 7 October, morning): PASS against v4, a class v5 rule

The cryptanalysis brief's rank-3 question (a weak-key class in the day's rotation and multiplier draws, MEMHARD's untested all-equal ROT draw) is now measured: docs/analysis/attack-pass/f4-weakday.md (branch attack-pass). No weak class: the cheap days are the tail of a sum (the exact convolution predicts the census to 0.6 percent). Against the DSP-bound datapath (M2) PASS, 0 of 2^28 days over 1.1x. On the LUT-adder metric (M1, every multiply in adders, census median 231 adders per mixer application) 5,476 of 2^24 days over 1.1x (3.26e-4, 342x the 2^-20 gate); the worst in 2^24 1.173x; the worst in the public calendar's first 100 years chain day 29,337 at 1.121x (M2 1.000x). Priced: a per-day LUT-recompute FPGA gets at most 12.1 percent more hash rate on that day (reads and shadow untouched), 12 days a century, 0.004 percent of a century's hashes; 0 for a stored-dataset FPGA or any chip; one bitstream a day under USD 3 compiled ahead on the public calendar. Consequence per tier: nothing for any GPU miner or pool; the chip model is unmoved. The rule for the NEXT class (sent to the v5 lane with F4's harness as the gate; v4 untouched): reject a MUL block with NAF sum under 163, NAF weight at least 4 per word, at least 4 distinct ROT amounts, redraw from the next stream values, 6.1e-4 rejection per day, the first calendar redraw day 22,633; no devnet or testnet pack changes.

AP-F1-1, the shadow redundancy bound (the attack-pass lane, 7 October, 12:3x UK): PASS against v4, a class v5 rule

Over 100,000 class v4 programs the shadow block's peephole-removable instructions (a register written twice from one source with no write between) average 0.62 percent of the 256 per pass, maximum 5.078 percent, 1 in 100,000 over 5 percent; nothing crosses a pass; clang -O3 removes the same instructions from the honest kernel, so it is a bound on the shadow's useful work, not a chip shortcut (docs/analysis/attack-pass/f1-shadow.md). Consequence per tier: nothing for any miner or chip; the chip model is unmoved. The rule for the next class (sent to the v5 lane with F1's harness on 64 seeds as the gate; v4 untouched): the generator refuses a shadow block whose honest-compiler simplification exceeds 3.0 percent (the v5 lane's fraction, 4af21977: the bins from 3.0 percent up hold 384 of 100,000 draws, about 4e-3, under one attempt lost per 250 seeds, inside the 2.0 rule's bounds) and redraws from the next stream values; it lands in generator.rs behind the v5 class once ca3-v4-amend is merged into class-v5.

8. Close

Closed 6 October 2026, 18:1x UTC. The lanes: item 1 (ca3-analysis), item 2 (ca3-derive), items 4 and 5 (ca3-detector), item 3 (ca3-crypto-brief), items 6 and 7 (ca3-reserve), item 8 (ca3-shadow), the PC 1 AMD jobs (ca3-pc1-amd), the hash gates (ca3-v4-hash) and the node gates with both preconditions (ca3-v4-node and the fork): thank you, every one of you, for the numbers and for the faults you found in your own work and in mine before they reached a cut.