igneum/docs/analysis/class-v6/1p5x/lab/table.md

The 1.5x laboratory candidate table (LAB; current as of 12:2x UK 9 October 2026 by date; the interface: scratchpad/lab/INTERFACE.md)

Score = the WORST comparison over the cohort (same node and one node ahead), the candidate's GPU energy per accepted work over the lowest credible specialist energy for the same work (interface section 3). The working scope since 11:5x UK (8a): the same-node board is the energy claim; the die and node-ahead chips are coexistence rows. The coexistence table (8b, under the rulings of 8c) is the headline beside the score. Every ratio names its adversary, column, clock state, card and set (8c.1). PASS is never written here. Every chip figure is a WITNESS (E_D) unless marked BOUND, CLAIMED or SCREEN. Energies in nJ per hash (per lane-work for X10).

The approved claim wording (8c.9), verbatim: "The current model finds that existing GPU electricity costs are below the assessed DRAM-board specialist's all-in costs at the tested tariffs and stated lifetime assumptions. This supports a conditional entry-deterrence result. It does not yet establish post-deployment competitiveness, viable GPU replacement or new entry, or coexistence against the modelled SRAM fleet at sufficient scale. Those outcomes remain separately assessed."

The controls and candidates

id	kind	tree, packs, kits	resource line	cohort rows (board power, stock on every rented pod, lock refused everywhere; wall BLOCKED; median of three)	adversary rows (set v2, instruction convention, complete machine)	worst score (band), labelled	coexistence (8b under 8c)	status	next move (owner, clock UK)
ctl-v6	control (frozen)	1a938abe4; the signing object 0x2a1d6caab4c24564 at 2^30 words = 4 GiB (pack x1-ctrl-ds30.tgz 7606c13d, twin 7629ed95; CONTROLS 12:2x on main's correction, build-1:/srv/artefacts/lab/controls/frozen-v6/ with sidecars); kits: l8off c20999d1 (CUDA 218ca414 / 9bfcf728 Linux), gen-6 bb66a546 (Linux CUDA 804a6f7f, OpenCL 371dbb27); COHORT's rows on kit bf9b85d6, worker f5f3846c; the 1 GiB pairing only a cross-check row	4 GiB; 256 loads per hash of ONE 32-bit word each (1,024 bytes consumed of 8,192 moved; the readwidth fact of record, 8a.1); 62,120 instructions (102,612 counted); state class; layer 8 ON; cold verification 8.3 to 8.6 ms per warp of 32 on one core (the record; the fresh F2 row 13:30)	STOCK (COHORT 12:17, fp b1f90e91cadb15b6 PASS on every cell): RTX 3090 pod 55006505 (capped 260 of 350 W) 8,429 at 30.80 MH/s; RTX 3090 pod 55006552 (capped 220 of 420) 7,109 at 30.90; RTX 5090 pod 55006481 (384 of a 500 W cap, uncapped in effect) 5,597 at 68.66, f 0.811; RTX 5090 pod 55006478 (capped 400 of 600) 5,828 at 68.64; RTX 5080 pod 55006521 (189 of 330, clean) 5,410 at 35.03, f 0.806; the 3090 twins read f 1.02 (meaningless on a capped card). KNEE: the house record only (5090 at 1,300: 4,011). In flight: 4090a (repeat triple at 3.98 percent spread), 4090b, 5080b, uncapped 5090c and 3090c. AMD, Intel: NOT RUN "no rented card; the house rigs unreachable by software"	v2 (ADVERSARY 12:0x to 12:1x; commits f9cb259cc routed lanes, 923f76e74 coexistence, 7c6b538f1 price sheet on class-v6-adversary): the cheapest same-node DRAM board a = 1,543 (1,328 to 1,947) = 2.60x (2.06 to 3.02) at the 5090 knee, 2.70x a node ahead; the split chip memory 527 / ALU 167 / tax 849 against the card's 3,642 / 369 / 0; the tax ladder: the record's static 2.60x, half 3.28x, zero (the bound) 4.43x; ProgPoW's premise 1.01x to 1.02x; the N2 die a = 337 = 11.9x (coexistence)	PARTIAL over {3090, 5090, 5080 at stock; the 5090 knee from the record}; the 4090 cells pending; AMD and Intel NOT RUN. The worst cell: the RTX 3090 at stock on the same-node DRAM board, set v2: 5.46x (4.33 to 6.35) same node, 5.68x a node ahead; the die at that cell 25.0x. The other cells on the board: 3090 (capped) 4.61x, 5090 stock 3.63x, 5090 (capped) 3.78x, 5080 stock 3.51x, 5090 knee 2.60x; the record's rented 4090 at stock (8,091) would read 5.24x	ctl-v6 on set v2 (WITNESS; a 100,000-machine fleet, a 24-month straight-line life, design USD 35 M board chip and 300 M die, the card sunk at USD 30.6 per MH/s on v6 at the knee, 15.7 of record beside it): the same-node board, edge 2.60x at the knee, chip capital USD 14.04 per MH/s (die 0.34, memory 5.42, board 3.15, design 5.13); GPU electricity-only 0.056 / 0.111 / 0.167 USD per TH at the three tested tariffs against the chip's all-in 0.244 / 0.265 / 0.287: cost ratio 4.4x / 2.4x / 1.7x (the curves meet about USD 0.33 per kWh, the reviewer's linear read; ADVERSARY's exact figure owed); the stored-half hybrid, edge 3.80x, USD 9.17: 2.9x / 1.6x / 1.1x; the N2 die, edge 11.9x, USD 1.59: 0.5x / 0.3x / 0.2x, the GPU owner's electricity above the chip's all-in once the fleet passes 14,300 dies at ten cents (break-even 14,300 to 25,000 under the growth schedules; no schedule kills the die at 100,000 dies); the node-ahead board, edge 2.70x: 4.4x / 2.4x / 1.7x. NEW BUYER (8c.7): picks the chip on every row and tier (the board 0.24x to 0.43x a new card's all-in at ten cents, the die 0.04x; indifference USD 9.7 per MH/s on the 5090 knee, 10.5 on the 5080, 5.4 on the 5090 stock, 2.6 on the 4090; the hold is the project share below about 13,500 boards). The two-phase rows, the revenue column, the used-card column and the exact meeting tariff: NOT RUN (ADVERSARY, this afternoon)	MEASURED-partial (the 4090 cells pending)	COHORT: the 4090 and uncapped cells; the read-headroom row (8c.8) with CONTROLS; ADVERSARY: the two phases, revenue, used-card, the meeting tariff, the growth-scaled new buyer; LAB: the full score when the 4090 rows land
ctl-progpow-094	control	CONTROLS building the official 0.9.4 reference from source with its test vectors on build-5 (pid build-5-lab-controls-progpow.pid), by 14:00; ADVERSARY's v2 rows use the KAWPOW census as the proxy	the equivalence contract before any number; 16 KB per hash of DRAM traffic (ADVERSARY)	NOT RUN (the record's 4090 stock row 6,920 is ADVERSARY's numerator)	v2 (proxy): the board 4.24x at the 4090 stock numerator (the 32-register lane costs more than the 8-register one), a_same 545 = 12.7x; the board bandwidth-bound at 16 KB per hash (93 MH/s per board), USD 6.89 per MH/s against 29.7; ProgPoW's premise 1.1x to 1.2x (no twin)	proxy, 4090 stock, board, v2: 4.24x; NOT the lab's score (the pinned build, the cohort rows and a twin pending)	v2 at ten cents, proxy: the board holds 1.1x (the GPU's electricity above the chip's all-in at fifteen cents); the die pushed out above 14,200 dies	NOT RUN (proxy)	CONTROLS 14:00; COHORT rows 15:00 with a twin; ADVERSARY re-prices on the pinned object
ctl-fishhash	control	CONTROLS building Iron Fish's implementation on build-9 (pid build-9-lab-controls-fishhash.pid), by 14:00; ADVERSARY read cpp/FishHash.cpp	32 x 3 fetches of 128 B = 96 random reads over a fixed 4.83 GB dataset, about 9,400 lane-instructions of 64-bit multiply-add and FNV	NOT RUN	v2: a_same 162 (three N2 reticles, fused lane), USD 0.35; the board 1,044 (872 to 1,251), 124 MH/s per board bandwidth-bound, USD 4.78; 95 percent of the board's energy is the memory path	waits on COHORT's card row	NOT RUN	NOT RUN	CONTROLS 14:00; COHORT 15:00
ctl-coop-arx	control and candidate	CONTROLS: the cooperative ARX kernel and CPU reference bit-exact at 2^16 for chain lengths 24 / 264 / 1,032 / 4,104 ARX ops per fetch per lane (build-2, pid build-2-lab-controls-arxcoop.pid); the document and rows 13:00	64 coalesced 256 B fetches; target f at or under 14.8 percent non-ARX energy; spills, sync, generation and finalisation counted	NOT RUN (the card MODELLED by ADVERSARY: 35 nJ per coalesced read, 8.5 pJ per ARX instruction at the knee)	v2 (card MODELLED, SCREEN) at 1.6 M ARX per hash: the board 2.40x (1.96 to 2.86) same node against the routed 32-register fused lane, 2.98x ahead; a_same 5,024 (near-memory, fused) = 3.15x; USD 13 to 15 per MH/s against 15.7	SCREEN, 5090 knee modelled, board, v2: 2.40x	v2 at ten cents, card modelled: the board holds 1.1x; the die holds 1.5x	SCREEN	CONTROLS 13:00; COHORT's 4090 and 5090 rows 15:00; ADVERSARY re-prices within the hour
cand-x10 (variants alu-130k / 260k / 520k and sector-118 inside it)	candidate (the founder's third review; the scoped same-node board claim; 8a, 8a.1)	SEARCH: the kit at build-1:/srv/artefacts/lab/cand-x10/kit/ (sector.cu 16417ce6, run-x10.sh, 18 fixtures PASS on a rented 4090 at 11:11 UTC, 112 registers, no spills); the accepted-work contract APPROVED (per lane-work = per digest over 32, both printed)	dependent 32 B sector loads, every byte folded; 118 loads as written; the FAULT OF RECORD: 7 of every 8 loads re-read the same sector, about 16 real misses per lane-hash (8a.1); the verifier under 10 ms owed	SEARCH's first rows (a rented 4090 at stock, SCREEN until COHORT's pairs): 118 loads 810 to 845 nJ per lane-work (25.9 to 27.0 uJ per digest) at 264 to 275 W; 64 loads 567 at 294 W; a tenth of v6's 8,091 on the card class, the cache hits of the fault, not a design gain	v2 with the card MODELLED (SCREEN): sector-118 the board 634 (553 to 798) = 3.00x (2.38 to 3.44) at a card modelled at 1,900 nJ, 3.03x ahead; the split chip 243 / 22 / 369 against the card's 1,650 / 70 / 180; the fold gap 1.2x to 3.9x by core; the die 73 (26x); the ALU ladder 130k / 260k / 520k: the board 4.67x / 2.89x / 1.63x (1.27 to 2.06), 5.52x / 3.56x / 2.08x ahead (the card = v6 by the reviewer's construction). Every modelled-card row re-priced within the hour of COHORT's measured row; the 16-real-misses fault means the chip's memory term in these rows is also overstated for the object as written	SCREEN; the verdict line waits on COHORT's measured pairs (v6 and X10, the same card, the same session)	v2 at ten cents, card modelled: the board holds 2.2x; the die pushed out above 5,800 dies	SCREEN (the object as written carries the fault)	COHORT: run cand-x10 and cand-x10b paired with v6 on the 4090 and 5090 pods now (the kits are staged); ADVERSARY: re-price on the measured rows and on the 16-miss trace; LAB: the verdict line within the hour of the pairs
cand-x10b	candidate (main's ratified address rule on X10: load n reads the two registers the previous load's fold wrote last; zero repeats in every trace)	SEARCH: hash-x10b.ts, fixtures-x10b.txt (18), sector.cu under -DX10B; the kit lands under build-1:/srv/artefacts/lab/cand-x10b/ with its fixture line; queued on the same 4090 pod behind the x10 rows	as X10 with 118 real dependent sector misses per lane-work; fixtures 18 of 18 PASS under -DX10B; the kit at build-1:/srv/artefacts/lab/cand-x10b/kit with trace.json	SEARCH's first row (a rented 4090 at stock, sampler rule, SCREEN until COHORT's pair): 118 loads 3,653 nJ per lane-work at 66.1 M lane-works per second and 241.5 W, 31 nJ per dependent sector read, the card at its 7.8 G dependent reads per second ceiling; the 64-load and lock rows queued	set v2's same-node board on the 118-miss object: 634 (553 to 798), WITNESS, the split chip memory 243 / fold 22 / tax 369	the 4090 at stock, the same-node DRAM board, set v2: 5.8x (4.6 to 6.6); v6 on the same card class 5.4x: the fold buys nothing on the ratio (REG-06 confirmed); the term that holds it above 1.5 is the card's memory path (31 nJ per read against the chip's about 2); PARTIAL: the locked 5090 and 5080 and the AMD card NOT RUN	NOT RUN (ADVERSARY re-prices on the measured row)	MEASURED-partial; FAIL CLOSED per the review (no added arithmetic, rotation or set growth)	COHORT: the v6 and x10b pairs on the uncapped 4090 and 5090 after the dataset-size decider; SEARCH: the 64-load and lock rows; ADVERSARY: the coexistence row on the measured card
cand-14, cand-12, cand-13 (SEARCH's top three on set v2, the hand-off 13:2x UK)	candidates	packs at 4 GiB on the signing pair with SHA256SUMS and trace.json at build-1:/srv/artefacts/lab/candidates//pack-ds30 (the ds28 screening pack beside); self-test PASS (the gen-6 worker --check on the rented 4090), census 8 of 8	cand-14: w32m8g+sh128x18+state+fold+labw0f0f140c0d0000190000+ilp4+flat (a MAD-heavy table: add 15 sub 15 xor 20 rotl 12 rotr 13 mad 25, four register banks, 32 B entries, 256 reads, 27k instructions, no window layer); cand-12: mx8+sh128x36 on the same table and banks, 4 B entries, 40k instructions; cand-13: w32m8g+sh64x54, 37k instructions	NOT RUN (COHORT: paired with v6 at stock and at the knee on the 4090 VM, behind the ledger session and the X10 pairs)	v2 (SEARCH's model; ADVERSARY's v3 pages for cand-11 to cand-20 beside): board 2.42x / 2.43x / 2.43x at the 5090 knee, 5.20x on the provisional 3090 stock row; the die 14.4x / 11.6x / 13.6x; the frozen object on the same model 2.66x and 12.2x	SCREEN: the realisable space sits between 2.4x and 2.7x on the board cell and above 10x on the die; the top three gain 9 percent on the board through mad (the one family priced near the card, 2.9x) and the ILP-4 banks; no candidate screens near 1.5 on any cell; the measurement at the knee decides whether the 9 percent exists (at stock the ALU sits in the reads' shadow)	NOT RUN	SCREEN	COHORT after the ledger; ADVERSARY re-prices on the measured rows
cand-01 to cand-09, cand-ilp2, cand-ilp4 (SEARCH batch 1)	candidates (the workload-search system)	staged at build-1:/srv/artefacts/lab/candidates/ (12:17 UK by the box clock) with trace.json; ADVERSARY's trace watcher prices each within the hour; the GPU self-test on a one-shot 4090 pod by 13:30; the top three to COHORT and ADVERSARY by 14:00 at ds30	the six knobs with explicit limits; the ARX-only region 48 to 64 reads, 170k to 225k instructions per unit; the ilp variants test the card's dependency structure (11.8 pJ per instruction at the lock on the drawn block against 6.2 on an ILP-4 chain)	NOT RUN	NOT RUN (priced on v2 within the hour)	SCREEN on set v3 (ADVERSARY 12:3x, the card figures SEARCH's screened values; the worst cohort cell the 3090 at stock in every one): cand-01 to cand-10 (arxr48/64 shadow classes, 48 to 96 scattered reads, 169k to 339k instructions): the board 3.1x to 3.3x at the 5090 knee and 6.2x to 6.7x at the worst cell, a (the die, the three-quarter hybrid or near-memory, 574 to 1,168 nJ) 3.9x to 4.2x and 7.7x to 8.4x (9.7x to 10.9x a node ahead); cand-11 to cand-19 (labw classes, 256 scattered reads of 4 to 32 bytes, 27k to 112k instructions): the board 2.4x to 2.5x at the knee, 5.1x to 5.5x at the worst cell, a 8.3x to 19.0x and 17.6x to 40.9x (the full SRAM die serves 256 reads at 187 to 495 nJ); cand-16 and cand-20 (sh512x4, sh256x9 at 64 and 48 reads, 20k to 22k instructions, the 5090 at 0.8 to 1.0 uJ): a 11.0x and 9.6x, boards 2.6x and 2.7x. NONE UNDER 1.5x ON ANY CELL: the die binds every candidate with 256 reads; the board's own tax holds the board cells at 2.4x and above	v3 coexistence rows per candidate on the twenty pages (the new-buyer column included)	SCREEN	SEARCH: the self-tests 13:30, the top three on v3 at 14:00; COHORT measures the top three

COHORT's denominator run on ctl-v6 (from 11:49 UK)

Rented by id through the handover gate (two hosts per card: 5090 x2, 4090 x2, 3090 x2, 5080 x2; drivers 570 to 595), the gen-6 worker f5f3846c on kit bf9b85d6, the x1-ctrl-ds30 pack (0x2a1d6caab4c24564) with its read-only twin (X7's twin, kernel 93a6a5ce, the address path kept by construction, twin_addr none accepted), three timed runs per pack per state interleaved, rows at build-1:/srv/artefacts/lab/ctl-v6/vast-/ (rows.jsonl, SHA256SUMS, the .tgz) linked under /srv/artefacts/lab/cohort/ctl-v6// and the cohort's own table at /srv/artefacts/lab/cohort/TABLE.md. Every pod refuses the lock: stock only. The capped-host finding (12:17): f near 1 on a capped card is meaningless; the gate now refuses capped hosts for the f cells; the 4090b pod that never answered was destroyed and re-rented. AMD and Intel: no RX 7600 to 9070 or Arc card on either provider (AMD there is MI300X and MI350X only), the house rigs unreachable by software; NOT RUN "no rented card; the house rigs unreachable by software" on every candidate (build-1:/srv/artefacts/lab/NOT-RUN-amd-intel.md); the hourly provider check retries. Spend: USD 750 at 12:03.

Adversarial sets

set	date	contents	candidates scored on it
v0 (the record)	9 Oct, X0 amendment 5b and X5	the placed 8-lane 18-family core (6.55 pJ per lane-op at N5), the GDDR7 board, the hybrids at 0.25, 0.50, 0.75, the N2 full-SRAM die, recomputation; X7's HBM3 and near-memory paths; X8's systolic int8 array	ctl-v6 (the record: board 2.35x, die 7.8x); SEARCH's cost model (recalibration owed)
v1	12:0x UK (ADVERSARY, 0344ec150 on class-v6-adversary)	v0 plus a bandwidth ceiling on every DRAM design (1.79 TB/s at 85 percent), a register file sized to the work (the routed 8-register flop lanes), fused dependent operations (the tail CLAIMED), HBM3 at one and eight stacks and near-memory as complete machines, recomputation priced from the Ethash-family generators, the die on as many reticles as the dataset needs; calibration reproduces X0 5b (1,706 vs 1,707 nJ; the die 511 vs 513)	the four controls (ctl-v6 board 2.57x)
v2	12:0x to 12:1x UK (ADVERSARY, f9cb259cc the routed lanes, 923f76e74 coexistence, 7c6b538f1 the price sheet; tools/chip-model/floor-k-lab with the routed power logs)	v1 with the routed fused-ARX lanes (ASAP7 routed with SPEF, 1,200 ps, timing met: arxf 8-register window 1.87 pJ per fused add-rotate-xor triple, 464 um2, against the single-op lane's 2.16 pJ per op; arxf32 32-register window 5.42 pJ per triple, 1,316 um2): the ARX-fused rows WITNESS; the non-ARX fused groups (mul-xor, 64-bit multiply-add, math and merge) CLAIMED-partial until the two lanes in the flow on build-4 land (the 64-register fused-ARX window that X10 carries as "x1.6 claimed", a fused multiply-xor lane), about 12:3x; every modelled-card row labelled "card": "MODELLED" and SCREEN; the coexistence tables, the new-buyer column, the growth schedules (growth-schedules.json) and the price sheet with the break-even sensitivity (the board breaks even at ten cents only with devices under about USD 8 to 10 each, a fleet above a million machines and a 36-month life together)	every control and candidate (ctl-v6 board 2.60x, die 11.9x; ctl-progpow-094 4.24x proxy; ctl-coop-arx 2.40x screen; cand-x10 3.00x screen)
v3	12:2x UK (ADVERSARY b2b9ee0b9; v3/ beside v2/ under lab/adv/; the JSONs in scratchpad/lab/adv/ now v3)	v2 plus two more ROUTED lanes (the 64-register fused-ARX window 9.90 pJ per triple, 2,469 um2, replacing the "x1.6 claimed"; the fused multiply-xor pair 4.13 pJ over 32 registers, replacing the claimed tail on the FNV and merge steps) and two corrections (a shadow class's window is the 8 registers its shadow runs on, as v6; a sized lane pays for a window above 8, so the 64-register sized lane is dearer than the placed core's SRAM window)	every control and candidate: ctl-progpow-094 a_same 669 (10.3x), board 3.94x (proxy); cand-x10 Sector 2.92x; cand-x10 at 520k ALU the board 1.03x (0.83 to 1.14) same node, 1.35x ahead, SCREEN with the card assumed = v6 (the measurement ordered: SEARCH builds the point, COHORT pairs it; the card's own 520k instructions at 5.9 to 11.8 pJ are 3 to 6 uJ, so the P03 line decides first); cand-01 to cand-10 a_same 574 to 1,168, the board 769 to 1,472 (about 3.1x to 3.3x against their screened 5090 knee figures, a 3.9x to 5.4x)

Rejections and regression hits

when	source	what
12:1x UK	SEARCH, the first screen (4,000 draws, seed 1)	1,762 int8 mixes by REG-04; 122 scattered-ARX designs at or under 32 reads by REG-05; 343 on the verification or granularity limits (F2); SCREEN rejections, none measured
12:1x UK	SEARCH on cand-x10	the Sector reference as written re-reads the same sector for 7 of every 8 loads (16 real misses per lane-hash): the object is measured as written (its own row) and the corrected address rule measured beside it as cand-x10b; the author's energy split and the 10 percent budget do not describe the object as written

Faults

when	source	what	state
11:49 UK	COHORT	no AMD (RX 7600 to 9070) or Intel Arc card rentable on either provider; the house rigs unreachable by software	the two tiers NOT RUN with the reason on every candidate; hourly retry
12:1x UK	SEARCH	a parse fault on +arxr48+flat in batch 1	fixed in the cut; a 20-minute slip on the 13:30 clock, absorbed
12:1x UK	COHORT	the 4090b pod never answered on the provider's ssh proxy	destroyed and re-rented on another host
12:17 UK	COHORT	the read-only twin reads f near 1 on a power-capped card (the saved ALU power goes to clock)	the lab rule 1.11: f on uncapped cards only; the gate refuses capped hosts for the f cells; capped rows stand named
12:2x UK	LAB	the line to main of 12:1x carried "13:1x UK" (main's clock, not date)	the lab's lines carry date from here; reported once

The shipping row (the claim's phase B is NOT LIVE until a shipped package runs a prover; main 12:4x UK: the most important 2.0 shipping item)

item	what the claim needs on the record	state	owner
the two-phase result it serves	ADVERSARY 545f3f8a0: with the ratified 80/20 split (D04, token-value/README.md: the 80/20 split emission allocation only) a GPU earns the mining share plus the proving share, a hash chip the mining share only; the proving share at which the chip's operating advantage disappears at ten cents is 9 percent for the board, 13 for the hybrid, 20 for the die, against the ratified 20: with proving live the GPU out-earns the board chip in phase B. The stated assumption on the phase B row: all proving stays on the GPU cohort; a chip maker who fields GPUs to prove is a GPU miner with a sidecar	NOT LIVE	ADVERSARY (the row), the release lane (the package)
which shipped packages prove today, at what VRAM, by what switch	the Windows and Mac apps: the VRAM threshold and the switch by file and line; the HiveOS package: none (mines only); the 24 GB threshold (proving turns on at 24 GB) stated against the proving manifest and the app's settings code	BLOCKED: the file-and-line facts from the release lane and the app lane	the release lane aa4391fd50c62e28f
whether a 16 GB card can prove a smaller instance	the proving instance sizes against the 16 GB tier (the B3 feasibility rows explored 32, 128 and 512 MiB per instance for Track B; the live prover's own instance size by its manifest)	BLOCKED: the prover's instance table	the release lane with the proving lane
the share of the live cohort that can prove	the workers page's card census (the share of cards at 24 GB and above; the share at 16 GB)	NOT RUN: the fleet lane's workers.json read	the fleet lane
a HiveOS prover beside the miner	a named 2.0.3.1 item beside snapshot sync, with the memory and VRAM rules from this row; no new research	NOT RUN: scheduled by the release lane	the release lane aa4391fd50c62e28f
the 4 GiB proving cap defined precisely (8c.10)	which of the mining state, the proof-generation allocation, the verifier requirement or the advertised hardware profile it limits	NOT RUN	CONTROLS (the definition), ADVERSARY (the economics)

The read-headroom row (8c.8), answered 12:4x UK (CONTROLS and SEARCH, WITNESS)

card	achieved sector reads per second on v6 at 4 GiB (rate x 256)	the activation bound (JEDEC-family timing approximations, named so)	nJ per 32 B sector read (stock)	the fold	the ILP lever (SEARCH, in-session ABBA)	reading
RTX 4090	7.86 G	at its tFAW form, 7.9 G	26.4 to 28.4	the whole-sector load free (a32x = a4); the full fold +1.0 nJ (+3.7 percent)	cand-ilp4 rate +0.00 percent, joules -0.64 (8,560 against 8,615); cand-ilp2 +0.00 / +0.00	AT the limit: no card-side headroom; the ALU in the reads' shadow
RTX 5090	17.6 G	within a third of its tRC form	18.9 to 19.8	the full fold +1.2 nJ (+6.2 percent)	not yet paired	AT the limit; flat from 1 to 8 GiB (no TLB cliff for a flat stream)
RTX 5080	8.97 G	CONTROLS owed
RTX 3090	7.91 G (capped pods)	CONTROLS owed

The miner-side lever "more loads in flight per core" is CLOSED on v6 by these rows; the phase B lever on the card is its memory system itself. The "2.4x at 4 GiB" reading is WITHDRAWN (a contention fault of the CONTROLS lane: the 4 GiB bench shared the card with the sector sweep; clean ABAB on a 5090: the 4 GiB object costs 3 percent of rate against the 1 GiB research pack).

The shipping row's facts (the release lane, 12:5x UK, release-2.0.3 at 034cdad1, app/igneum-app/src)

The Mac and Windows apps carry the prover (SP1 6.8.1 through igneum-prove-host), ON by default on an NVIDIA card of 23,552 MiB or more (provedefault.rs:23-24; a 24 GB card reports 24,564), mining or not, on Linux or Windows with WSL2; OFF with the reason on 16 to 24 GB, under 16 GB, Windows under 32 GB RAM, Apple silicon, AMD-only; the prover refuses to start under 12 GB (provedefault.rs:31) and a card under 12 GB holds the prover or the miner, never both (engine.rs:41, :2717). HiveOS: none (h-run.sh has no prover section); the HiveOS prover is SCHEDULED as a 2.0.3.1 item beside snapshot sync (cut by 18:00 UK, the rule-33 canary on a 24 GB 4090 by 19:00). A 16 GB card proves no shard today: the floor 13,874 MiB for an empty shard and 15,670 beside the miner (provedefault.rs:8); the v1 shard (30,000 pgas, 4.7 M cycles) 20,434 alone, 22,210 beside the miner; the devnet's prototype shards until the fee switch at DAA 210,000 need 32 GB (28,307 alone, 30,039 beside; VRAM_MB_PROTOTYPE_SHARD 31,000, provedefault.rs:27, :135); aggregation 16,751 MiB with the miner (24 GB; prover.rs:1122); no smaller instance exists (provedefault.rs:9 open). The Hive package applies the app's device.rs:63 mode table (Simultaneous at or above 23,552 MiB, ProveOnly, MiningOnly). Phase B therefore reads LIVE today only on Windows and Mac where a 32 GB NVIDIA card is present, NOT LIVE on the 24 GB tier until DAA 210,000 and on HiveOS until the cut.

Results of record, 13:0x UK

• THE DECIDER (COHORT, uncapped 5090 pod 55012544, 575 W default, driver 580.173.02, worker f5f3846c, 250 x 2^24, three runs each, one session; build-1:/srv/artefacts/lab/ctl-v6-decider/vast-55012544/): the 4 GiB signing object 68.63 MH/s at 410.4 W = 5,979.9 nJ per hash, twin 4,806.2, f 0.804, spread 0.46 percent, fp b1f90e91cadb15b6 PASS; the same program at 2^28 (1 GiB) 70.63 MH/s at 414.7 W = 5,871.2 nJ (fp 01f51b9d4805e5e6); the research pack hl-v6-all as staged under tas/same-work-20261008-01 (program id 0x4de7b836cc40a4ea, not the l8off kit's 0x9d40978601a7df2a) 70.63 at 402.2 W = 5,694.8 nJ. VERDICT: the 4 GiB object costs this worker 2.9 percent of rate and 1.8 percent of joules per hash against its own 1 GiB export; occupancy identical (96 registers, 20 blocks per SM, 3,400 resident lanes per SM); reads 17.57 G per second at 4 GiB against 18.08 at 1 GiB. The 3.4 against 7.9 G reading was CONTROLS' instrument; withdrawn. The uncapped 5090 ctl-v6 cell: 5,979.9 nJ at stock = 3.88x (3.07 to 4.50) on set v2's same-node board; the 5090 knee stays the record's 2.60x.

• The TLB rows (CONTROLS, both cards, mode a4 at 118 loads, build-1:/srv/artefacts/lab/controls/frozen-v6/tlb/): the 4090 8.02 / 7.92 / 7.87 / 7.84 G reads per second at 1 / 2 / 4 / 8 GiB (26.07 to 26.81 nJ per read), the 5090 18.11 / 17.76 / 17.60 / 17.52 (19.11 to 19.77 nJ): a flat random stream loses 2 to 3 percent of rate from 1 to 8 GiB on either card, no cliff; the layer-8 windows at 2^30 touch the whole 4 GiB as a flat stream does; the live object's cost is the 2 to 3 percent page-walk margin.

• The 4 GiB cap defined (CONTROLS, 8c.10): the MINING DATASET floor and nothing else: docs/spec/01-lottery-hash.md lines 849 to 850 (4,096 MiB from genesis, one step, no later step; the dataset policy 70a6c703, register row 10; the cache 2^26 words, line 434); the proof-generation allocation carries no 4 GiB figure (proving/igneum-prove/host/src/memory_profile.rs TIERS lines 115 to 121: full 26 GiB free, 24gb 20 GiB, 16gb 14 GiB, small 0; the ELF manifest pins no memory line); the verifier is independent of the dataset size (spec 01 line 702: at most 4,096 item derivations per unit from the 256 MiB cache; the F2 row 10.63 ms per warp); the advertised hardware profile (docs/design/app-audit-2026-10-08.md row F8) is constrained only through the miner's resident set pushing a co-resident prover into the small tier (memory_profile.rs line 117).

• ctl-progpow-094 at the live DAG (CONTROLS): the official CUDA kernel's mix digests at Ethereum epoch 871 (block 26,154,532, DAG 8,380,217,984 bytes) equal the CPU reference's on both nonces: F1 holds at the live size; the live rate on the rented 4090 at stock 58.75 / 58.76 MH/s (0.96 TB/s of coalesced 256-byte entries) against 62.58 at the 1 GiB DAG: the live DAG costs 6 percent; the by-construction read-only twin gpu/pp_twin built, rows queued; the KAWPOW live size (epoch 609, 6,182,403,712 bytes) queued.

• ctl-coop-arx on the 5090 (CONTROLS, stock, sm_120): 105.3 M units per second at 72 ops (1.72 TB/s, the DRAM ceiling; the twin 103.8), 14.32 at 1,032 and 3.66 at 4,104 (ALU-bound, equal to the 4090's 14.18 / 3.69); five chain lengths F1-complete (CHAIN 86 fingerprint 84f43aecf5d8a8cd on CPU and GPU).

• THE PROVING CORRECTION (PROVING LIVE and the release lane): the prototype-shard 32 GB clause (provedefault.rs) is Devnet 1's (params.rs:3082 LIVE_13); Devnet 4 runs fees_v1_activation_daa 0 (params.rs:2307 on 27f54124; the node reports shardBudget 30,000 pgas), so a 24 GB NVIDIA card proves the v1 shard and aggregates beside its miner NOW (13,523 to 14,899 MiB peak beside the miner on the fleet's 4090s, 117 to 120 s per 8-block segment, 0.99 to 1.88 IGN paid); on chain 4465 at tip 31,719 (11:50Z) 663 paid v1 segment records = 653.93 IGN to 30 prover keys; 0 segments proven in the last 600 blocks (payments paused since the hub roll at about 11:00Z, the cause under fix). The proving row reads NOT LIVE "paid on Devnet 4 to 30 keys, epoch evidence pending" until docs/analysis/class-v6/1p5x/lab/proving-live.md lands with one full epoch of paid rows (by 16:00). Phase B therefore reads live today for the 24 GB tier on Mac and Windows once that record lands, and on HiveOS from the prover package's entry (cut by 18:00); the 16 GB tier holds no shard.

• X10 pairs: the first 4090 pair carried valid v6 rows (8,692 nJ at 30.69 MH/s, f 0.859) and valid X10 rates (x10b 66.1 M lane-works per second at 118 loads = the v6 pair's 30.69 x 256/118 within 1 percent: memory-bound exactly as v6; the x10b ladder 64 / 96 / 118 / 128 loads 122.1 / 81.3 / 66.1 / 60.9 M scales as 1/loads) but ZERO watts on every X10 row (the 40-batch default ran a quarter second, under the sampler's 8 s warm-in); kit r3 (sha 323e3970) sizes the batches per variant (45 to 85 s), adds cand-x10's fixtures and an x10b by-construction twin (-DX10B -DTWIN: the address rule kept, the fold one xor per loaded word, the mix and shuffles removed; its address stream a dependent chain of the same count and width, named so in twin_addr), and the driver refuses any row with watts 0.0 at staging; both pairs re-rented on uncapped 4090 and 5090. ADVERSARY's interim: the Sector card from its rate at the pod's v6 watts, 4,039 nJ per lane-work MODELLED-from-rate (bounded below at about 3,470 by the twin's ALU share), the cheapest DRAM board (650 nJ) 6.2x on the 4090 at stock.

• THE LEDGER ORDER (the founder, 12:5x UK; the LEDGER lane a101aa8329d1e82bf): the lab's lanes feed the GPU NETWORK LEDGER first: every live GPU chain measured the same way on the same rented 4090 and 5090 in one session each (Igneum v6 at 4 GiB, KAWPOW via ProgPoW 0.9.4 at the live DAG, FishHash, Etchash via the pinned chfast hashimoto at ETC's current DAG, Autolykos2 if the in-house rule and the clock allow), the set v3 board ratio and the ProgPoW-premise ratio per chain, the two-phase rows with each chain's actual split (only Igneum pays provers), the E9 Pro calibration line (ADVERSARY models the one real chip against Etchash; the gap to its public rate and power stated as the model's calibration). COHORT's ledger session is renting (v6, FishHash full and twin, ProgPoW 1 GiB class now; the live-DAG binary pp_harness_26154532 from CONTROLS pulled in if it lands in time, else a second short session); CONTROLS' Etchash harness is built and F1-checked against chfast at blocks 0 and 12,750,000 (ETC epoch 425). The ledger table on the record at docs/analysis/class-v6/1p5x/ledger/README.md 15:30, the kit 16:30, the page 17:30; the registry cell ledger:cross-chain beside lab:candidate on R15-09, NOT RUN until the kit's rows reproduce. The candidate search continues fail-closed at lower priority (the 520k-ALU point and the headroom row close their records; no new families).

• The 4090 decider CLOSED (CONTROLS, one quiet session, stock, the 4 GiB signing pack): the kit zip 4 worker f5f3846c 30.661 MH/s at 20 x 2^22 and 30.693 at 50 x 2^24; the build-1 worker 804a6f7f 30.663 and 30.692 on the same pack and shape; the 1 GiB research pack 31.313: the two builds are the same instrument to four figures, the batch shape moves nothing, the live 4 GiB object costs the 4090 2.0 percent of rate (3 percent on the 5090); the 13.16 was the shared-card read, withdrawn (build-1:/srv/artefacts/lab/controls/frozen-v6/decider-4090.log). ctl-progpow-094's by-construction twin on the 4090: 77.42 MH/s at the 1 GiB DAG and 60.20 at the live 8.38 GB DAG against the full kernel's 62.58 and 58.75: at the live size the card is at its memory limit (the ALU hidden under the reads). ctl-fishhash on the 5090: F1 PASS (fingerprint f841605125ce375e equal to the 4090's), 45.37 MH/s full against 39.71 for the twin (19.73 / 17.75 on the 4090). The F2 row re-run on the same pinned core: 10.440 ms per warp for the signing object at 2^30, 5.134 for the class v4 calibration (frozen-v6/f2-verifier-build5.txt).

• CONTROLS' done line (13:0x to 13:1x UK): the four controls and the ledger rows staged under build-1:/srv/artefacts/lab/controls/ with SHA256SUMS (frozen-v6 with tlb/, coop-arx, progpow-094, fishhash, sector-read, etchash, autolykos; 25 MB). Autolykos2 landed in-house and bit-exact (hashlib reference against the CUDA harness at N = 65,536 and at Ergo's live N = 227,251,815, 7.27 GB; 216.2 / 201.8 MH/s full / twin on the rented 4090; the live-block end-to-end row owed). coop-arx's OpenCL text F1-complete on two OpenCL platforms at all five chain lengths (the AMD tier runs the moment a card is reachable; Metal owed). Open on that lane: the knee rows (every rented pod refuses the lock; COHORT's VM-host lock hunt reports by 14:30), the Metal text, the Ergo live-block row.

• ADVERSARY (12:5x to 13:0x): phase B tier rows on the on-chain read (commit 82330b04c; 47f16b86f with Etchash on the mirror): the 24 GB-and-up NVIDIA tier on Windows and Mac LIVE on Devnet 4 and out-earning the board chip in phase B (the GPU's contribution per TH after electricity 0.341 against the chip's 0.288 after its recurring cost at ten cents on the flat path); HiveOS NOT LIVE until the 2.0.3.1 package; the 16 GB tier never (mining share only, 0.046 per TH behind the chip). ctl-etchash as a control (64 x 128 B reads over about 3.3 GB) with the calibration line: the modelled DRAM board 765 nJ per hash against the shipped Antminer E9 Pro's 598 (3,680 MH/s at 2,200 W, the public figure as the ledger lane quotes it): the model 1.28x pessimistic for the chip, a witness. Phase A and B for Ravencoin, Ethereum Classic and Iron Fish in their own units (commit d7db3e596, README section 14): no fleet recovers a board chip's spend on any of the three on any path (each chain's 24-month mining emission under one design cost: RVN about USD 2.9 M, IRON 1.4 M, ETC 83 M at a 10,000-board fleet); phase B with no prover income: on Ravencoin the chip's operating advantage stands in full at USD 0.123 per TH; on ETC the mining revenue per TH (0.0087) is below the board's recurring cost (0.031) and the E9 Pro's electricity alone (0.017), a loss on both sides at ten cents. The reading: on every chain in the set the board chip's phase B advantage is real and its phase A recovery is not at today's emissions; the proving share is the one term that lets Igneum's live GPU tier out-earn the chip in phase B.

• The boxes (the build steward, 13:1x): the lab's ended box runs' pid files removed as stale after each pid's command line was read dead; the steward's defaults on build-4, build-5 and build-6 stand until a lane claims with a live pid file.

• THE 4090 DECIDER (COHORT 13:10, uncapped pod 55012546, 450 W default, driver 570.172.08, worker f5f3846c, 250 x 2^24, three runs each, one session; build-1:/srv/artefacts/lab/ctl-v6-decider/vast-55012546/): the 4 GiB signing object 31.52 MH/s at 275.1 W = 8,728.3 nJ per hash, twin 7,398.0, f 0.848, spread 1.06 percent, fp PASS; the same id at 2^28 32.14 MH/s = 8,600.1 nJ; the research pack 32.15 = 8,448.2; occupancy identical (88 registers, 20 blocks per SM). CLOSED on both denominator cards: the 4 GiB set costs 2.0 (4090) and 2.9 (5090) percent of rate and 1.5 to 1.8 percent of joules; reads 8.07 G per second at 4 GiB against 8.23 at 1 GiB; the batch-shape question closed by CONTROLS' own pair (20 x 2^22 and 50 x 2^24 equal to four figures), so no fix pair exists to measure. The uncapped 4090 ctl-v6 cells: 8,369 / 8,692 / 8,728 / 8,751 nJ over four pods (host spread 4.5 percent, drivers 570 to 595): the scoreboard's 4090 figure is the median 8,710 with the spread, the worst cell 8,751 = 5.67x.

• Autolykos2 priced on set v3 (ADVERSARY 13:1x, README section 15): the same-node board 198 nJ (172 to 249) = 5.8x on the 4090 at stock from CONTROLS' 216.2 MH/s at 250 W claimed (MODELLED-from-rate until COHORT's session row); the die on four reticles 46 nJ (25x); premise 1.01x; phase A no recovery on any path (Ergo's 24-month mining emission about USD 0.6 M); phase B mining only, the chip's advantage USD 0.024 per TH standing in full.

• SEARCH handed build-9 back (batches 1 and 2 done and exported); its measurements continue on the rented 4090 (x10b 64-load, alu-520k, the v6x2 pair, batch 2's self-tests); row folders at build-1:/srv/artefacts/lab/rows/lab-search-4090-pod/ with SUMS; the lane record docs/analysis/class-v6/1p5x/lab/search/README.md on branch lab-search.

• The "no emergency intervention" row (8g): Devnet 4 on finality rule v3, paused since lock 1980, the chain on PoW through the pause, nothing certified reversed, proving unaffected once the finality gate on provers was lifted; the first new lock expected 15:30 to 17:00 UK; the vote key label-derived (no key file).

• THE 520k CELL CLOSED (SEARCH 13:2x, the rented 4090 at stock, fixtures 9 of 9 PASS, 97 registers, no spills, two passes): cand-x10 variant alu-520k 15.8 M lane-works per second at 351 to 366 W = 22,152 and 23,225 nJ per lane-work (709 to 743 uJ per digest) against the frozen v6's 8,594 nJ per hash in the same session: 2.6x to 2.7x v6's joules per unit, the P03 10 percent budget failed by 160 percent (about 42 pJ per instruction on this text; the 41,536 shuffles per lane-work at the card's dearest family); set v3's 1.03x (the card assumed equal to v6) scales to about 2.7x on this cell. REJECTED (F4). NO MEASURED OR SCREENED CELL ON ANY CARD SITS UNDER 1.5x ON THE SAME-NODE BOARD after the X10 family, the twenty search candidates and the four controls; the best cell is the frozen v6 on the 5090 at its knee, 2.60x (2.06 to 3.02), WITNESS, set v2 and v3.

• 8c.8 CLOSED: the v6x2 confirming row (two lane-hashes per thread, fingerprint equal) 30.697 against 30.697 MH/s, 8,574 against 8,594 nJ (-0.2 percent); fifteen headroom cells flat at 7.85 to 7.86 G reads per second against the memprobe ceiling 8.1: the 4090 is at its bound. cand-x10b at 64 loads 122.2 M lane-works per second = 1,993 and 2,020 nJ per lane-work (31.1 nJ per read).

• A LOCKABLE RENTED HOST (COHORT 13:23): Vast VM offers (KVM, GPU passthrough, the driver in the guest) hold -lgc; the 4090 VM 55018643 (driver 575.51.03) locked 0 to 1,500 and restored; the five-chain ledger session runs there at stock and at the knee the recipe picks from a clock ladder (1,200 to 1,900); the 5090 VM at the record's 1,300 once it boots; the stock sessions mid-run on the uncapped containers 55017318 (4090) and 55018470 (5090). The scoreboard's claim column gets measured knee rows on rented cards for every chain today.

Open rows (NOT RUN)

row	owner	clock
the card's random-read headroom per cohort card against its memory-timing bound and the chip's 148 MH/s (8c.8)	COHORT with CONTROLS	this afternoon with the scoreboard
the two-phase coexistence rows, the revenue column, the used-card column, the growth-scaled new buyer, the exact meeting tariff per row (8c.2 to 8c.7)	ADVERSARY	this afternoon
the 4 GiB proving cap defined precisely (8c.10)	CONTROLS (the definition), ADVERSARY (the economics)	this afternoon
the comparative review of what other GPU chains publish on chip resistance (8c.9)	unassigned; NOT RUN until done	none
the units rule in every control's contract (revenue per accepted work in the algorithm's own units)	CONTROLS	with each pin
the founder's bundle (8d)	LAB	14:00