igneum-labs 2939f4264d Class v6 census: the post-review object's (c''') read (hl-v6-all 4de7b836cc40a4ea, generator 6, PASS: the rule with the floor, 256 of 256 at r 0.129, the window trace standing), with the a326de8ea read beside it ... Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com> Documents-only replay of e5d7e171c (e5d7e171c4) for the box mirror master		2026-10-08 19:38:32 +00:00
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amd-intel-energy	AMD and Intel energy on class v6 (GPU-03 AMD and Intel cells, ECO-05 named cause): per 32 bits of bus the AMD and Intel cards burn the 5090s watts but do 0.21x to 0.47x its random reads; the window costs the RX 7600 and the Arc B580 no rate per unit of work; the B580 class v6 rows (11.01 MH/s, fingerprints equal, watts unreadable unelevated); hash-identical kernel candidates ranked (0 to about 10 percent); the RX 7600 metered knee owed to a queued PC 1 job	2026-10-08 19:21:27 +00:00
floor	Class v6 floor lane 4: the RX 7600 (8 GB) measured on PC 1 (13.88 MH/s at 113 W, 8.14 microjoules, the card-in job 15:50 UK) added to the tiers table and the AMD estimates re-based on it; 10 of 10 on build-3	2026-10-08 15:04:38 +00:00
logs	Class v6 census: the post-review object's (c''') read (hl-v6-all 4de7b836cc40a4ea, generator 6, PASS: the rule with the floor, 256 of 256 at r 0.129, the window trace standing), with the a326de8ea read beside it	2026-10-08 19:38:32 +00:00
rows	test registry: the hash lane's batch 1 (tools/ci/batches/hash-lane-20261008-batch1.json: bench:pc1-packs, bench:pc1-amd, bench:fleet-pods, census:class-v6, suite:pow as RUNNING with their evidence rows under docs/analysis/class-v6/rows)	2026-10-08 18:33:08 +00:00
amd-intel-energy.md	AMD and Intel energy on class v6 (GPU-03 AMD and Intel cells, ECO-05 named cause): per 32 bits of bus the AMD and Intel cards burn the 5090s watts but do 0.21x to 0.47x its random reads; the window costs the RX 7600 and the Arc B580 no rate per unit of work; the B580 class v6 rows (11.01 MH/s, fingerprints equal, watts unreadable unelevated); hash-identical kernel candidates ranked (0 to about 10 percent); the RX 7600 metered knee owed to a queued PC 1 job	2026-10-08 19:21:27 +00:00
census-packs.md	Class v6 census: the post-review object's (c''') read (hl-v6-all 4de7b836cc40a4ea, generator 6, PASS: the rule with the floor, 256 of 256 at r 0.129, the window trace standing), with the a326de8ea read beside it	2026-10-08 19:38:32 +00:00
census-w16-mix.md	Class v6 census: the recommendation amended on the coordinator's close (W = 16 dead on energy by floor lane 5's card rows; the order is W = 8 pins, the index fold first, then the re-weight at W = 8 through this harness before it enters)	2026-10-08 13:09:44 +00:00
coexist-rows.md	docs: class v6 coexistence rows on an RTX 3060 12 GB and an RTX 4060 8 GB (5.5 GiB miner beside the compressed shard prover, verbatim run-log rows, the reconciliation with the 6 October 8.9 GB row and the 16 GB rule)	2026-10-08 15:48:20 +00:00
coexistence-model.md	Igneum 2.0 D4: the placed energies (the complete GDDR7 machine 1.6x node-for-node, 1.9x a node ahead; the hybrid 2.4x / 2.9x; the die 2.4x / 3.3x; per-dollar unchanged) and the three chips scored at them, no verdict changed; the served energy sentence on them; the proving-payment pin in the code behind its constant, the guest's mirror owed	2026-10-08 16:05:40 +00:00
connected-state.md	Publish the 2.0 evidence set on the public mirror (main's word): coexistence-model.md, operator-simulation.md, connected-state.md, coexist-rows.md and the class v6 design record leave the export-exclude list, the lane records and logs stay excluded; the zone word redacted in connected-state.md; the mirror-follows-master note beside every evidence column	2026-10-08 17:29:00 +00:00
family-gate.md	Class v6 family gate, 6.10: the hash lane's layer-8-off draw through the acceptance on class-v6 542cd7028 against the same-crate windowed control (PASS: r 0.18 against 0.27 at width 4, the (c''') cost 2 against 13 percent, 0 hot sets and 0 over 1.2x at 2^20, the bit-R share up with the windows gone, the fold the lever); the harness port diff at 542cd7028	2026-10-08 17:54:46 +00:00
hardware-future.md	Class v6 research lane B: the hardware future, five years out (first cut and the full report in one file)	2026-10-08 10:17:50 +00:00
history.md	Class v6 history lane, revision 3: the dataset-floor schedule priced per tier and against the chips (section 4.2a, main's ask of 11:2x UK)	2026-10-08 10:38:53 +00:00
invention.md	Class v6 invention: the 5090 rows for the two per-load packs (the sound form costs the card 15 to 20 percent more per shadow instruction than the whole block, +19 W unlocked and +6.6 W at the knee at class v4's count; rank 1's GPU column corrected, the verdict restated with the honest sign)	2026-10-08 11:45:37 +00:00
mixed-fp32.md	Class v6 mixed FP32: section 6.1, the k lane's synthesised FP32 rows (FMA lane 3.4 pJ at N3, k 0.65 on the unit, 0.15 blended at the lock); the score 3.2x / 3.5x; the verdict stands	2026-10-08 16:07:14 +00:00
multi-family-adversary.md	multi-family adversary: clock stamps read from the Mac	2026-10-08 16:10:22 +00:00
operator-simulation.md	Igneum 2.0 D4: the placed energies (the complete GDDR7 machine 1.6x node-for-node, 1.9x a node ahead; the hybrid 2.4x / 2.9x; the die 2.4x / 3.3x; per-dollar unchanged) and the three chips scored at them, no verdict changed; the served energy sentence on them; the proving-payment pin in the code behind its constant, the guest's mirror owed	2026-10-08 16:05:40 +00:00