igneum-labs
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f37691e983
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Merge ca3-coord-record 978ea619 into master (gate: green on 978ea619, recorded by tools/ci/pre-push.sh; landed on the build mirror)
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2026-10-08 08:48:19 +00:00 |
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igneum-labs
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978ea619e6
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Counter ASIC 3.0 status: main's morning words (the look landed, the floor sentence to row 17, CA4 parked, the Mac rule lifted for the F8 tail, route (A) at 10:45 BST), the build-server lane's honest state and the deploy and pairs plan, the fourth cut 5b673577 (floor 68,400), the Arc B580's self-test fault on both classes and the Intel kit held out of 0.3.24, the design pass on master (e59b127a)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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2026-10-08 08:40:46 +00:00 |
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igneum-labs
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e59b127a30
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Merge ca3-coord 9d30354d into master (gate: green on 9d30354d, recorded by tools/ci/pre-push.sh; landed on the build mirror)
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2026-10-08 08:39:08 +00:00 |
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igneum-labs
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9d30354d14
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Site: the bench table's lead-cell width rule applies on desktop widths only (above 1,100 px); on the phone grid the lead cell has no max-width, so the rate cell no longer sits over the card name at 390 px (the box's sweep read the 360 px cap covering the lead text on a 390 px viewport)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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2026-10-08 08:32:43 +00:00 |
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igneum-labs
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550219386f
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Site: the bench table's lead cell wraps on desktop (the row rule's nowrap outranked the lead cell's normal by specificity, so the class v4 line ran under the rate cell at 1280 px and above; the overlap sweep on the box read it COVERED, the Mac's gate had skipped the sweep for want of a browser)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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2026-10-08 08:32:43 +00:00 |
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igneum-labs
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d7bd60384b
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Site: the bench table's desktop row is six columns (the class v4 cost and the date move under the card name as the muted second line), the card layout below 1100 px, the wrapper scrolls as a safety (the overlap gate read the eight-column row clipped at every desktop width)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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2026-10-08 08:32:43 +00:00 |
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igneum-labs
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4f071764ea
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Site: the bench table's phone layout gives every cell its own grid area (the overlap gate read the quiet cells stacked under the Details button at 390 px)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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2026-10-08 08:32:42 +00:00 |
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igneum-labs
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0f2b5cf6fd
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Site: the GPU bench table's design pass in the site's own language (the founder, 7 October 2026): the vendor mark and name lead, the rate as the big tabular number, MH per wall watt in the ember tint for the best desktop card, watts and the class v4 cost quiet, the tuned state a pill, the date muted mono; the Hive values, the source and the note in a Details row; cards you can buy and datacentre under hairline headings, the datacentre collapsed; 56 px rows on desktop, a two-line card per row on a phone; the best desktop card as the lede, the rates note under a disclosure; header sort with the arrow and the ember underline
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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2026-10-08 08:32:42 +00:00 |
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igneum-labs
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eebc243e34
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Merge ca3-coord-record 8e4eb37b into master (gate: green on 8e4eb37b, recorded by tools/ci/pre-push.sh; landed on the build mirror)
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2026-10-08 07:19:20 +00:00 |
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igneum-labs
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8e4eb37b2e
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Counter ASIC 3.0 status: the 9070 XT bench row on master (the AMD watts no longer owed), the hot-table ldcs rows (a dead lever; the hot family latency-bound), the PC 1 list main set closed on measured rows
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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2026-10-08 07:13:01 +00:00 |
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igneum-labs
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4b603b28f5
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Merge ca3-v4-amend 2fa54cc6 into master (gate: green on 2fa54cc6, recorded by tools/ci/pre-push.sh; landed on the build mirror)
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2026-10-08 07:11:38 +00:00 |
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igneum-labs
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2fa54cc664
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bench-log: the hot-table packs on the RTX 5090, ldcs against base, unlocked and at the 1,300 MHz lock (36 rows, all PASS; ldcs dead, the hot packs lose 2 percent to the lock where mx8 loses 7.5)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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2026-10-08 07:05:19 +00:00 |
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igneum-labs
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7786307e66
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Merge spec-accept-23 f9794b87 into master (gate: green on f9794b87, recorded by tools/ci/pre-push.sh; landed on the box mirror)
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2026-10-08 06:35:03 +00:00 |
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igneum-labs
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1d48fc3f98
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CA4 hot-table job: the first kit flattened the eight hot packs into one folder (the job exited 2 in 0 s, pack hot32k4 missing); kit b carries packs/<name>/ for all nine, the fetch and run ids take a b suffix
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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2026-10-08 06:30:27 +00:00 |
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igneum-labs
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a5a0a687c4
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Merge ca3-v4-amend 11f88bdd into master (gate: green on 11f88bdd, recorded by tools/ci/pre-push.sh; landed on the build mirror)
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2026-10-08 06:29:02 +00:00 |
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igneum-labs
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f9794b8712
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Bench table: the RX 9070 XT row takes the app's own power reading at the stock point (202 W at 18.9 MH/s, 0.093 MH/W; the G1 ladder's 18.8 to 19.2 as the rate; the status row of 8 October 2026), tune state "no lever" (no AMD knob in 0.3.20), the class v4 cost unchanged, Hive values none; /miners rebuilt
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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2026-10-08 06:28:55 +00:00 |
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igneum-labs
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41f90af1b6
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Merge ca3-coord-record 14c453b4 into master (gate: green on 14c453b4, recorded by tools/ci/pre-push.sh; landed on the build mirror)
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2026-10-08 06:27:36 +00:00 |
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igneum-labs
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489f4ff5bd
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Merge ship-docs-0321 b8e0772d into master (gate: green on b8e0772d, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge)
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2026-10-08 06:25:18 +00:00 |
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igneum-labs
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14c453b4ca
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Counter ASIC 3.0 status: the 5080 Ember tune (the lock worth +40 percent per watt over the stock climb; the knob's case), the knob on release-0.3.24 (8bb0e288), the 9070 XT tune (no AMD knob in 0.3.20; 18.9 MH/s at 202 W; the AMD core-clock knob a morning item), the hot-table job the last on PC 1
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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2026-10-08 06:21:16 +00:00 |
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igneum-labs
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b8e0772d1d
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release 0.3.22 section 21: the core-clock knob cherry-picked onto release-0.3.24 (the union with the efficient-point ceiling), the measured Ember line from PC 1
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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2026-10-08 06:19:49 +00:00 |
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igneum-labs
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11f88bdde6
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PC 1 Ember per-card job: a card the app cannot steer stores one baseline row and logs no progress line; count the stored curve before calling the run empty (the 9070 XT run exited 1 on a real row)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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2026-10-08 06:18:25 +00:00 |
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igneum-labs
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9d85a9f29c
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Merge ca3-v4-amend fa420559 into master (gate: green on fa420559, recorded by tools/ci/pre-push.sh; landed on the build mirror)
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2026-10-08 06:16:47 +00:00 |
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igneum-labs
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481eef0425
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Merge ca3-coord-record 544e4037 into master (gate: green on 544e4037, recorded by tools/ci/pre-push.sh; landed on the build mirror)
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2026-10-08 06:14:22 +00:00 |
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igneum-labs
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544e4037b5
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Chip model 5.11 and new-pow 5.1: the per-MAC figures corrected by the per-lane tile count (32 MACs per tile, not 1,024; the 4090's 0.056 pJ is 1.8 pJ, the 5090 reads 2.9 and 1.5 at the shadow's premium), the tensor-tile column withdrawn (a chip's k on tile work 0.03 to 0.3, below the ALU shadow's); Counter ASIC 3.0 status: the microbench's correction, the night's closing sentence on measured rows, the CA4 file's commits
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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2026-10-08 06:08:07 +00:00 |
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igneum-labs
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ec63f87846
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Merge ca3-coord-record 89ef71e6 into master (gate: green on 89ef71e6, recorded by tools/ci/pre-push.sh; landed on the build mirror)
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2026-10-08 06:06:49 +00:00 |
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igneum-labs
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fa420559b3
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PC 1 Ember per-card job: the curve line cast an integer plus a string and threw (the 06:0x 5080 run's rows lost); string interpolation instead, and every card's stored curve printed at the start
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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2026-10-08 06:06:24 +00:00 |
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igneum-labs
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89ef71e6c0
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Counter ASIC 3.0 status: the microbench on the 5090 (20 probes at both states; shfl 55.8 pJ, mul 13.9, mulhi 39.6 against the ARX op's 11.3; int8 mma 1.36): the re-weight's re-opening condition not met on measured rows, the tile block's case in measured picojoules
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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2026-10-08 06:00:29 +00:00 |
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igneum-labs
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cf6d1c8d7f
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Merge ca3-coord-record db91345e into master (gate: green on db91345e, recorded by tools/ci/pre-push.sh; landed on the build mirror)
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2026-10-08 05:30:14 +00:00 |
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igneum-labs
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db91345e43
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Counter ASIC 3.0 status: rank 2 closed in the CA4 file (the premium is the ops' energy whatever carries them), the op-mix re-weight's case to main as HOLD with its four-line basis and the condition that re-opens it
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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2026-10-08 05:23:57 +00:00 |
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igneum-labs
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d74a29cdb0
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Merge ca3-coord-record a86e62e5 into master (gate: green on a86e62e5, recorded by tools/ci/pre-push.sh; landed on the build mirror)
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2026-10-08 05:22:56 +00:00 |
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igneum-labs
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a86e62e5be
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Counter ASIC 3.0 status: the SM-sparse reading exists (a quarter of the SMs holds 98.2 percent of the class v4 rate at the same draw; the premium is the shadow's ALU work, the SM-sparse candidate dead; the op-mix re-weight's case to main)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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2026-10-08 05:16:37 +00:00 |
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igneum-labs
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66b85c4e99
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Merge ca3-coord-record 7c4a74fd into master (gate: green on 7c4a74fd, recorded by tools/ci/pre-push.sh; landed on the build mirror)
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2026-10-08 04:43:18 +00:00 |
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igneum-labs
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03a62fc514
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CA4 microbench job: the kit's class v4 pack as the --pack argument (the exe's parser demands one before the microbench branch; the probes read none); republished as -c after the sparse run
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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2026-10-08 04:37:08 +00:00 |
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igneum-labs
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7c4a74fd90
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Counter ASIC 3.0 status: F1's record on master (7d22bc0b; lane (d) complete with its box-hours), the v5 lane's night closed (class-v5 1095eaa8 gated GREEN, 72 checks)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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2026-10-08 04:37:03 +00:00 |
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igneum-labs
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004738ac5a
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Merge ca3-coord-record abda374a into master (gate: green on abda374a, recorded by tools/ci/pre-push.sh; landed on the build mirror)
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2026-10-08 04:36:04 +00:00 |
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igneum-labs
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abda374a41
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Counter ASIC 3.0 status: class-v5's F1 row on both mirrors, the CA4 packs on the 5090 (the tile premium 0.103 W per tile unlocked, 0.050 at the lock; every sound pack memory-bound), the prototypes' first sentence on measured rows (neither beats class v4's premium; the per-load class dead; the tile block at parity with the ALU shadow and worse at the chip's k), the k column's basis measured
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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2026-10-08 04:29:48 +00:00 |
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igneum-labs
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7d22bc0bab
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Merge attack-pass 28e76a0b into master (gate: green on 28e76a0b, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge)
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2026-10-08 04:29:30 +00:00 |
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igneum-labs
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0730ff1fa8
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Merge ca3-coord-record 1be7ba27 into master (gate: green on 1be7ba27, recorded by tools/ci/pre-push.sh; landed on the build mirror)
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2026-10-08 04:28:50 +00:00 |
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igneum-labs
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4559fcc200
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Merge ship-docs-0321 a5ddc127 into master (gate: green on a5ddc127, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge)
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2026-10-08 04:27:46 +00:00 |
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igneum-labs
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28e76a0be6
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attack-pass lane (d): F1 shadow redundancy on the frozen class v5 tip f2267bb6, 10^5 programs, max 4.688 percent, 0 mismatches, PASS (the 0.3.24 gate line; AP-F1-1 FIXED-AND-PASSED on v5)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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2026-10-08 04:22:29 +00:00 |
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igneum-labs
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1be7ba2776
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Counter ASIC 3.0 status: the census harness's progress line and flushed partial (known-failed PASS), F1 PASS on class v5 (100,000 programs, max 4.688 percent saved, 0 soundness mismatches, 05:20 BST); the attack board on class v5 complete
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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2026-10-08 04:22:26 +00:00 |
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igneum-labs
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a5ddc1270f
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release 0.3.22: the attack-pass record lines (F9 and F1 PASS on the full 10^5), PC 1 overnight
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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2026-10-08 04:22:12 +00:00 |
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igneum-labs
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cf09054040
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CA4 packs and hot-table jobs: $pid is PowerShell's read-only automatic variable (the 04:04Z packs run threw at its first pack); $progId instead; the packs job republished as -b
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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2026-10-08 04:11:17 +00:00 |
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igneum-labs
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28eb22d07e
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Merge ca3-coord-record 595b0a7b into master (gate: green on 595b0a7b, recorded by tools/ci/pre-push.sh; landed on the build mirror)
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2026-10-08 04:08:59 +00:00 |
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igneum-labs
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09598f434b
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attack-pass: F1 record section 12, the census flush and its known-failed test (2,000 rows after a kill at 2,000, PASS)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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2026-10-08 04:08:52 +00:00 |
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igneum-labs
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d6a278e465
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CA4 microbench job: the installed worker's NVRTC DLLs copied beside the fetched exe and the exe run from its own folder (the loader refusal the research lane named)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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2026-10-08 04:06:36 +00:00 |
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igneum-labs
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26d722fc04
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CA4 microbench job: the research lane's exact command (no --device flag), every line echoed when the exe refuses (the 03:54Z run exited 2 after one unseen line); republished as -b after the packs
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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2026-10-08 04:04:53 +00:00 |
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igneum-labs
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595b0a7bd2
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Counter ASIC 3.0 status: the pass's close at master 4b45b2bd, the fourth --variant fix (the capture's off-by-one, ca4sparse5), adv-accept off build-1 for F1's census and one holder yielded to the flush test, adv-cache-2 closed (2^36 reads at the control's values)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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2026-10-08 04:02:45 +00:00 |
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igneum-labs
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18693ac228
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Merge ca3-coord-record 2bdd0b3a into master (gate: green on 2bdd0b3a, recorded by tools/ci/pre-push.sh; landed on the build mirror)
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2026-10-08 04:01:49 +00:00 |
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igneum-labs
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27b0adcae9
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CA4 SM-sparse rerun (c): the research lane's ca4sparse5 exe (the parameter-capture fix); the card-free check's NVRTC compile result gates the run
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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2026-10-08 03:56:27 +00:00 |
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