Sections 15 to 19: every GPU block gaming and AI paid for, priced against the best public 4 to 5 nm chip figure with its k band, verifier cost and the edge at the measured premium (the one-sentence answer: nothing reads k above 1 with certainty; the int8 tensor tile is the only block near or above 1, so the tensor shadow with a SIMD byte-dot verifier is the new rank 3); the capex column added to the chip model (both sides capex-dominated at 7x to 10x their electricity; the per-unit capex wall unreachable by 3x to 7x; the project wall doubled from USD 100 M to about USD 200 M of break-even cap by the shadow-per-load design, the mission lane's method); the microbench of 20 probes documented as built (section 18); the owed list.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
proto-cuda/nvrtc/worker.cpp, cuda_api.h: `--microbench [--mb-seconds 60] [--mb-only a,b]` runs 20 probes one at a time at full residency for the window, each compiled by NVRTC on its own (a refused form drops that probe with its error on the row): the sleeping-SM floor, int32 add-xor-rotate, multiply, mulhi, byte permute, LOP3, warp shuffle, FP32 FMA, FP16x2 FMA, tensor tiles at u8 m8n8k16, s8 m16n8k32, f16 and bf16 m16n8k16, e4m3 m16n8k32, L2-resident chases at 32 and 64 MiB (dependent and 4 independent), the 1 GiB DRAM chase (the hash's control), a point-sampled u32 texture fetch and a linearly filtered float fetch (cuTexObjectCreate loaded optionally). Each RESULT line carries the counted operations per second, lanes, registers, UTC start and end stamps for a 1 Hz power sampler, and a checksum. Gate: mingw cross-compile on igneum-build-1 under lease pool (class measure, label "ca4 research"), exit 0 with -Wall -Wextra clean, 21:20 UTC; exe sha256 49aa60c4b28ed77a54655476d0f07c06a54aa22e4f6f6ccadd4019b84cbf0268; unrun on a card (the hash lane's PC 1 queue).
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
docs/analysis/counter-asic-4-research.md (excluded from the public export): edge = (E_card + F) / (E_mem + k F); at zero premium the stored-dataset chip keeps E_card / E_mem, 3.6x on a 5090 locked at 1,400 MHz (measured card, modelled chip), about 2x at that card's idle-plus-memory bound, 1.7x on the M5 Max; class v5 at zero shadow leaves it at 5.1x to 9.1x; the shadow buys 2.1x at k = 1 for the measured 88 W (81.8 W at the knee) and turns against us below 1.8 pJ per op; per-card classes, the refresh as a cost, proof of useful work, memory shaping and the tensor block priced out with their arithmetic; ten designs ranked with the chip edge, the 5090 and 4070 premiums, the verifier cost, agent hours and what breaks each; the recommendation in five sentences; consequences per tier.
proto-cuda/nvrtc/worker.cpp: opt-in SM-sparse variants sp<N> and sp<N>-w<W> (a persistent grid of N blocks of W warps over the dispatch's nonces; the bound kernel rewritten at compile time with exact anchors into a unit function plus a wrapper of the kernel's name; made on demand by name, never in the default race; refused on variant-5 packs and with minBlocks). Gate: mingw cross-compile on igneum-build-1 under lease pool (class measure, label "ca4 research"), exit 0 with -Wall -Wextra, 22:48 UTC; exe sha256 ee8d0e70dd101f125f42c0c7cf07481a794ee18a1317acf68561b37ea18d72be; unrun on a card (the hash lane's PC 1 job run-ca4-pc1-ca4sparse-5090-20261007 is its first run).
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
the project lead's /live screenshot: a fixed tall box with the lanes in its top third and dead space under them. The renderer now knows
the height it wants: top padding + axis padding + lanes shown (at most maxLanes 7, narrowLanes 4 on a phone, never under 2)
times laneHeight (46 px, 40 on a phone, 26 compact; the mount option laneHeight overrides). It reports it through
onSize(heightPx, {lanes, laneHeight, narrow, compact}) whenever it changes and through getWantedHeight(); stats() carries
laneHeight, padT, padB, capacity, wantedHeight and autoHeight, so a page that sizes its own box reads no constants. With
autoHeight (on by default when the host set no CSS height on the canvas, which is read before the first size(); forced either
way by the option; never in compact mode, the app's card keeps its own height) the renderer sets canvas.style.height itself
and lets every lane through instead of fitting the lanes to the box. Every current host sets a height (/live 420, the hero
500, the app's card 220 and its Inspect view 420), so the frames are unchanged: the parity test on build-2 stayed equal on
every comparison. The site lane switches /live and the home fold to the hook.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
- /live (the project lead: "make it more efficient, key at the top"): the key (Included, Excluded, Selected chain, Your block, Proven,
Locked checkpoint), the "Click to inspect · Drag to explore" hint and the window stepper sit on one row above the scene
(hint left, key centred, stepper right; on phones the key wraps and the stepper goes under it); the blue-score range stays
as a small line under the canvas; the canvas height comes from the lane count (one lane per key in view plus the others
lane, capped at the renderer's 7, 4 on phones: padT 58 + lanes x 46 (40 narrow) + padB 38, read from scene/live-dag.js
2.0.3 layout(); a sizing hook was asked of the parity lane, which owns that file); the graph column no longer stretches to
the inspector; the inspector keeps its rows with tighter spacing and Clear is a small button beside its title.
- Every other route carries the slim bar, the app's buttons, pills and cards from site.css section 10 with its content
untouched: /app (OS marks on its platform line), /miner (the download tabs take the OS wells), /miners and the bench table
(the vendor badge in front of every card name), /explorer, /block, /address (hash titles wrap), /journey, /bench, /evidence
(status pills wrap in their cell), /litepaper, /ledger (status badges wrap at 390), /claims, /randomx, /provenance, /dev-fee,
/faucet, /metamask, /404.
- Data tables fill their frame on desktop and scroll inside it on phones; no column squeezed to a sliver.
- The overlap lane's detector over all 23 pages at 390 and 1440, dark and light, on build-2: 0 overlaps.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
