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igneum-labs
4ae285f25e Counter ASIC 3.0 status: the close (items 6, 7 and 8 closed; the chip model before and after; the class v4 candidate mx8+sh256x27 ready for the gate run; nine decisions for the project lead; the owed list) 2026-10-06 08:48:18 +00:00
igneum-labs
ca40decd9e Merge branch 'ca3-reserve' into ca3-coord 2026-10-06 08:45:48 +00:00
igneum-labs
0d47586d8f Counter ASIC 3.0 items 6 and 7: the RTX 5090 step-cost rows (PC 2 job run-ca3-family-pc2-20261006, every family bit-exact, mm8 included) in the bench-log and the reserve document 2026-10-06 08:45:02 +00:00
igneum-labs
94cb5993d3 Merge branch 'ca3-derive' into ca3-coord 
# Conflicts:
#	docs/bench-log.md
 2026-10-06 08:31:10 +00:00
igneum-labs
ee5afcfe03 Counter ASIC 3.0 item 2: the RTX 5090 rows from PC 2 (bit-exact on CUDA, +1.1 s NVRTC per pack, the card-off key finding) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 08:30:15 +00:00
igneum-labs
13013a3abd Counter ASIC 3.0 status: the detector's two calibration findings answered (8bbc524 merged; max r 0.10) 2026-10-06 08:29:28 +00:00
igneum-labs
340096939e Counter ASIC 3.0 status: PC 2 clear, the detector and vendor-share dry rows on the live tables, the restart constraint 2026-10-06 08:26:52 +00:00
igneum-labs
55f3c5a158 Counter ASIC 3.0 status: the marker guard exists in CI already 2026-10-06 08:25:02 +00:00
igneum-labs
1c9ae00189 Counter ASIC 3.0 status: items 6 and 7 merged (5090 rows queued), the marker slip recorded 2026-10-06 08:24:50 +00:00
igneum-labs
c692253ea1 Merge branch 'ca3-reserve' into ca3-coord 
# Conflicts:
#	docs/bench-log.md
#	tools/observer/observer.mjs
 2026-10-06 08:24:29 +00:00
igneum-labs
236a588c67 Merge ca3-shadow (item 8's Mac rows) into ca3-coord: LoadClass carries derive_len and shadow; igneum-pow suite 96 passed 2026-10-06 08:11:03 +00:00
igneum-labs
e9463b504a Counter ASIC 3.0 status: the 5090 draws about 290 W at the hash, cap floor 400 W, clocks are the lever (item 8's job) 2026-10-06 07:59:42 +00:00
igneum-labs
162121de7b Counter ASIC 3.0 status: item 2's verifier headroom table and the crate suite 2026-10-06 07:51:42 +00:00
igneum-labs
e99322690f Merge branch 'ca3-derive' into ca3-coord 2026-10-06 07:51:42 +00:00
igneum-labs
3aaa0c837c Counter ASIC 3.0 status: PC 2 clear about 08:35Z, the job order 2026-10-06 07:51:36 +00:00
igneum-labs
35ab9e4a29 Counter ASIC 3.0 status: item 2 interim (GO as reserve, NO-GO genesis-live at dr736), PC 2 clear about 08:35Z 2026-10-06 07:51:15 +00:00
igneum-labs
22134b3846 Counter ASIC 3.0 item 2: the verifier headroom per class under the 10 ms gate (the budget item 8 shares) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 07:51:13 +00:00
igneum-labs
399f974b95 Merge branch 'ca3-derive' into ca3-coord 
# Conflicts:
#	docs/analysis/chip-model-v3.md
 2026-10-06 07:51:00 +00:00
igneum-labs
b4b3f0d39a Counter ASIC 3.0 item 2: the design, the Mac measurements, the chip-model row and the PC 2 job 
docs/plans/counter-asic-3-derivation.md (the design, the acceptance test, the interpreter, the allowance argument,
the measurements, the PROPOSED reserve entry R0 for 1.13.2, what is owed), docs/analysis/chip-model-v3.md section 6
(the per-day derivation rows at 1.0x to 3x allowances), the bench-log entry, relay/playbooks/ca3-derive-pc2.ps1
(one PC 2 job: self-fetched packs zip, the installed worker through NVRTC, the card off only under test with its
key from settings.json). Verifier 4.875 / 4.944 ms per unit on one M5 Max core under the measure lock against
x8's 2.061 / 2.063; Metal build 29 ms against 22; hash rate equal; bit-exact on Metal and Apple OpenCL.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 07:50:01 +00:00
igneum-labs
9e3461251a Counter ASIC 3.0 status: items 4 and 5 closed, the owed list opened 2026-10-06 07:48:56 +00:00
igneum-labs
53b7de9e74 Merge branch 'ca3-detector' into ca3-coord 
# Conflicts:
#	docs/plans/funding.md
 2026-10-06 07:48:42 +00:00
igneum-labs
230e95566b Counter ASIC 3.0 items 4 and 5: the issuance trigger, the signal trigger, the FPGA lane and the layer 9 against layer 7 ranking 
docs/plans/funding.md rule 5: the bounty is escrowed and the benchmark live before daily
issuance crosses USD 20,000 a day, with the price-per-IGN table per halving period.
docs/plans/epoch-length.md section 11: the detector alert held 6 net windows recommends
the next shorter ladder step, per-tier costs at 2,400 and 600, the adversary's share per
compile class. Section 12: HBM FPGA parts with sources, reads in flight per watt against
the RTX 5090 (0.3x to 0.4x at Shuhai's measured rate, up to 1.9x at the unmeasured bank
ceiling), the two FPGA lanes in one table, and the ranking: layer 9 above layer 7.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 07:47:21 +00:00
igneum-labs
1765e892eb Counter ASIC 3.0 items 6 and 7: proposed reserve order and spec text (docs/plans/counter-asic-3-reserve.md), the vendor-share section on the benchmark page, the observer README row 2026-10-06 07:40:41 +00:00
igneum-labs
a3ce00f206 Counter ASIC 3.0 status: item 6's Mac step costs (interim) 2026-10-06 07:36:58 +00:00
igneum-labs
f8b1d4e644 Counter ASIC 3.0 status: the two claim drafts for the project lead with the rows that bound them (main's steering) 2026-10-06 07:35:09 +00:00
igneum-labs
1acac2e285 Counter ASIC 3.0 status: item 1 closed (verdict over 2x, the f = 1 chip), item 8 (latency-shadow program work) opened 2026-10-06 07:33:26 +00:00
igneum-labs
d961404cd8 Counter ASIC 3.0: mixer_mult = 8 in spec 1.13.1 and mixer-x4.md section 2 (item 3's finding); item 3 closed in the status file 2026-10-06 07:31:02 +00:00
igneum-labs
afb3df6098 Merge branch 'ca3-crypto-brief' into ca3-coord 2026-10-06 07:30:42 +00:00
igneum-labs
c8c3b1810c Counter ASIC 3.0 item 3: the mixer cryptanalysis line item and brief in funding.md 
One row in the funding table (USD 80,000 to 160,000 for two independent reviews, basis the four RandomX reviews of 2019 at their published per-firm prices and person-days) and a section "The mixer cryptanalysis brief (Counter ASIC 3.0 item 3)": the target shape from memhard.rs and accept.rs, the ranked break list with the chip-model number each moves, deliverables and timebox, the soundness suite to re-run, acceptance criteria in the RandomX audit style, candidate reviewers with citations, the risk column against the two-publish rollout, the timing against the testnet go checklist, and the consequences per user tier. Nothing else in the file is touched.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 07:29:45 +00:00
igneum-labs
233846e5f8 Counter ASIC 3.0 status: the run opened 07:3x UTC, machines and rules, five workers 2026-10-06 07:20:17 +00:00
igneum-labs
2542092b22 Merge branch 'master' into ca3-coord 2026-10-06 07:13:58 +00:00
igneum-labs
5aadaec8bc release 0.3.11: C35's cause on PC 1 and the ember-tune guard e600e63 in the next-cut list 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 07:03:10 +00:00
igneum-labs
bd93ae5023 Counter ASIC 2.0 status 07:03: PC 1 back, the 22:31Z quit source named (C35 closed), the Ember re-run on the project lead's word 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 07:02:44 +00:00
igneum-labs
66bc1784ef Counter ASIC 2.0: the crossing verdict PASS (05:21:48Z); H re-cut to about 19:12 to 19:20Z 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 05:58:24 +00:00
igneum-labs
dbddeba89c Counter ASIC 2.0: the coverage card counts corrected (47 mining / 18 chain mode / 6 proving-only) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 04:18:27 +00:00
igneum-labs
14c33be903 Counter ASIC 2.0: proving v1 segments confirmed from PC 2's log; decision 7 (segment length or cards) for the project lead 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 04:18:18 +00:00
igneum-labs
77495f88ad Counter ASIC 2.0: stamp 04:17 from the clock 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 04:17:13 +00:00
igneum-labs
eba1e419c6 Counter ASIC 2.0: proving v1's zero segments explained from prover.rs (coverage, not a fault); the morning line 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 04:17:08 +00:00
igneum-labs
cd66edfe04 Counter ASIC 2.0 status 04:17: proving v1 active with 0 segments proven (C47), the morning line 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 04:16:32 +00:00
igneum-labs
53a981b3f9 Counter ASIC 2.0 status 03:56: the crossing held (epoch 43 class v3 at DAA 154,814, 03:51:42Z); C46 on the next-cut list 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 03:55:26 +00:00
igneum-labs
ec20c5e19c Counter ASIC 2.0 status 01:34: the PC 2 chain closed (job 6's curve, the ledger suites, the job-runner finding) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 01:33:37 +00:00
igneum-labs
2d2414d450 Counter ASIC 2.0 status: stamp 01:13 from the clock 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 01:13:02 +00:00
igneum-labs
d82c15bfea Counter ASIC 2.0 status 01:16: the repro reading confirmed, the prover off on PC 2 since 00:49Z, job 5's parse failure 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 01:12:58 +00:00
igneum-labs
90fcb9411c Counter ASIC 2.0 rollout: PC job hygiene items (parse check, result writer, card-off confirmation) on the next-cut list 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 01:11:47 +00:00
igneum-labs
665bb9a3f7 Counter ASIC 2.0 status: heading stamped 01:10 from the clock 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 01:10:52 +00:00
igneum-labs
749f025f44 Counter ASIC 2.0 status 01:12: the repro run read as beside the miner, agg-cost-pc2-5 go 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 01:10:48 +00:00
igneum-labs
0f01a5d6f2 Counter ASIC 2.0 status 00:59: past DAA 144,000, N4 final, the queue state 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 00:59:27 +00:00
igneum-labs
2035fcf81c Counter ASIC 2.0 status: heading stamped 00:45 from the clock 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 00:45:34 +00:00
igneum-labs
0875f1d5c7 Counter ASIC 2.0 status 00:47: the M16 inline bench table, the repro run on PC 2 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 00:45:30 +00:00
igneum-labs
c23cbc8df6 Counter ASIC 2.0 rollout 6b: mine-and-prove measured beside the miner (sweep 4) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 00:38:58 +00:00