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Counter ASIC 3.0: mixer_mult = 8 in spec 1.13.1 and mixer-x4.md section 2 (item 3's finding); item 3 closed in the status file

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igneum-labs 2026-10-06 07:31:02 +00:00
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9
docs/plans/counter-asic-3-status.md
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@ -19,13 +19,20 @@ The test every result is judged against (the project lead, 6 October): a chip ma
| 1 | Partial-store chip and the time-memory curve | ca3-analysis | running | |
| 2 | Per-day item-derivation program (reserve entry, verifier gate, daily build) | ca3-derive | running (Mac first; 5090 job after PC 2 clears) | |
| 4 + 5 | Share-pattern detector, trigger rules, FPGA lane, layer 9 against 7 | ca3-detector | running | |
| 3 | Cryptanalysis brief in funding.md | ca3-crypto-brief | running | |
| 3 | Cryptanalysis brief in funding.md | ca3-crypto-brief | CLOSED, merged (43c3ead) | funding.md line item USD 80k to 160k, reviewer shortlist, ranked break list; verdict GO to commission (no outreach, no spend) |
| 6 + 7 | Reserve order with step costs, vendor-share metric | ca3-reserve | running (Mac first; 5090 job after PC 2 clears) | |
## 3. Measured numbers
(filled at each close)
## 3a. Corrections found by the run
| Found by | What was wrong | Fixed |
|---|---|---|
| item 3 (43c3ead) | spec 01 section 1.13.1's era table and `docs/plans/mixer-x4.md` section 2 still said `mixer_mult = 4`; the code (`LoadClass::MX8`, `V3_CLASS`) and spec 1.8.5 say 8 | both lines corrected on ca3-coord, 6 October 2026 |
| item 3 | the mixer's op count: 144 integer ops per application as written in `memhard.rs` (128 with RC and rk hoisted) against the 130 the chip model prices (`chip-model-v3.md` section 1, from spec 1.8.4) | items 1 and 2 asked to state which figure their rows use and why; the status close carries the answer |
## 4. The chip model, before and after
(filled at the close)

2
docs/plans/mixer-x4.md
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@ -34,7 +34,7 @@ has the measurement; it is under that bound, so B stays unimplemented.
### 1.8.5 Item derivation and dataset mapping
Item `t` (16 words) under mixer multiplier `m` (`m = 1` for program class v2, `m = 4` for class v3; a class
Item `t` (16 words) under mixer multiplier `m` (`m = 1` for program class v2, `m = 8` for class v3 as shipped, `LoadClass::MX8`, the x8 decision of section 6.4a at 22:05 UTC; `m = 4` was the candidate this file was written for, corrected 6 October 2026; a class
parameter, `LoadClass::mixer_mult`):
```

2
docs/spec/01-lottery-hash.md
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@ -436,7 +436,7 @@ The era seed `E_n` is the 32-byte output of the 1-hour VDF of section 4.4. One S
| Load count | 16 of 64 | not drawn | fixed, so every era is equally memory-bound |
| Output fold rotations | (7, 14, 21), (9, 18, 27) | each `1 + below(31)` | 1..31 |
| Mixer round count | 8 | not drawn | fixed, so the verify budget holds |
| Mixer applications per round `mixer_mult` | 4 (class v3; 1 under class v2) | not drawn | fixed at genesis (Counter ASIC 2.0, 5 October 2026: the M16 recompute chip's only measured lever; section 1.8.5 carries the form; `docs/plans/mixer-x4.md`) |
| Mixer applications per round `mixer_mult` | 8 (class v3, `LoadClass::MX8`, decided x8 at 22:05 UTC on 5 October 2026; 1 under class v2; corrected 6 October 2026, the row had said 4) | not drawn | fixed at genesis (Counter ASIC 2.0, 5 October 2026: the M16 recompute chip's only measured lever; section 1.8.5 carries the form; `docs/plans/mixer-x4.md`) |
| Epoch length `epoch_len` | 3,600 DAA s | one draw of the era stream consumed and not used (the value is set by signal) | the ladder 600, 900, 1,200, 1,800, 2,400, 3,600, 4,800, 7,200 (layer 9, `docs/plans/epoch-length.md`) |
`epoch_len` is the one era-table parameter set by miners rather than by the draw: 90% of blue blocks over a 7-day window carrying the same ladder index (3 bits of the header version, encoding Open in section 5.8) sets that length from the first day boundary at least 2 days after the window closes (section 5.7). It is not a code upgrade: the rule, the ladder and the window are genesis constants, and the chain carries no release. The era stream consumes its draw so that a future draw of this parameter changes no other parameter's value. The threat it answers is a per-program hard datapath (an FPGA fleet: 42 to 160 minutes per compile on a mid-size part, PRflow, FPT 2019, hours on large parts; at 600 s nothing it compiles ever runs); it does not answer a programmable chip, which the other layers answer. The floor 600 is set by the slowest compile-ahead measured (the Metal variant race, 38 s on the M5 Max, 6.3% of a 600-s epoch and inside the 600-s seed window; `docs/plans/epoch-length.md` section 6).