/income (through its generator, tools/launch/income-page.mjs, so the page check holds): pick a card (every current bench row, stock and tuned apart, inlined by the build; a tuned row at its tune point's rate), set a kWh price (the region's tariff from money.js, GBP 0.25 named as the default), type an IGN price (no default; the field says "no market yet: enter a price to see the figure"), read the network hash rate and the newest block's DAA from /api/live and the block reward from the chain's own rule (site/lib/emission.mjs at that DAA, 80 percent to the miner), and see IGN a day, electricity a day and money a day at that price, with the line that devnet and testnet IGN have no value. The arithmetic is site/lib/income-calc.mjs; site/lib/income-calc.test.mjs holds the known-failed case first (an empty, zero, negative or non-numeric price gives no money figure) and runs in the gate. The testnet tier tables stay below, named as the testnet's.
/economics: the emission as the node encodes it (release-0.3.25-node at e0644958, confirmed by the node lane: CURRENT on Devnet 3 and mainnet, TESTNET_1 on the testnet, each field with its file and line), the 80/20 split and the inactive silent-block bonus, the fee routes as the executor has them (base fee burned, the tip 80/20 with unregistered shares burned, external jobs designed and not in the code), the proving-fee market, the switchable 1 percent client fee and the fund it fills, the decimals per network; no price, no projection; "Not legal advice." alone. In the Learn group, the sitemap, the nav check and the capture routes; every page's chrome re-injected.
Bench table: class v4 watts rows 13 to 18 (RTX 2070 Super 204.2 W, +23 percent; GTX 1080 Ti 202.7 W uncapped, +63 percent; A100 500 W SKU 489.3 W, +78 percent; H100 695.1 W on its cap, +52 percent; RTX A4000 135.2 W at its stock cap, no premium; a tuned 2080 Ti board 161.1 W, the rate as a range by board).
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
- site/build.html and site/grants.html rendered by site/build.mjs from docs/build/build.md and docs/build/grants.md (the gate's site-only copy keeps the committed pages, as for /bench); site-relative links in the markdown renderer
- the nav's fourth group, Build (/build, /faucet, /grants), in the partial, the sheet, the footer, the sitemap and tools/ci/site-nav-check.mjs; the faucet leaves the Mine panel
- site/faucet.html is the Devnet 3 faucet: 10 IGN per address per day, 500 a day, chain id 4463, no value, resets without notice; the page posts to https://faucet.igneum.network/api/faucet and shows the balance
- infra/build-server/faucet: faucet.mjs (zero dependencies, signs with site/lib/eth.mjs, limiter self-test known-failed first, 100 IGN cap on the amount), the unit, faucet.sh install/status; live on build-1 behind Caddy since 10:16Z, funded 2,000 IGN by the fleet's funder at 10:01Z; first drip 0x8620e9d8 at 10:17Z
- docs/build: README, first-contract.md with its test script and the PASS line (24 s end to end through the public RPC and faucet, Foundry 1.8.5, Counter deployed at block 27055), rpc.md read from the node (75 methods probed, served and not served), faucet.md, verify-a-block.md, grants.md
- .forgejo/issue_template/grant.md: the grant application template on git.igneum.network
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
docs/analysis/class-v6/hardware-future.md: one table over PIM and PNM (HBM-PIM, AiM, LPDDR5X-PIM, UPMEM), HBM3E, HBM4 and the custom HBM4E base die, fine-grained DRAM on logic, LPDDR6, 3D DRAM, RLDRAM 3 and Folded Banks, FPGA with HBM2e, wafer-scale, CXL, optical I/O, chiplets and UCIe, and SRAM at N2: energy per dependent read, latency, cost per GB, availability to a non-hyperscaler, the k_read and shadow k bands, the edge per joule at zero shadow against the 5090 and the M5 Max, and the one layer of the four that blunts each with a number. The three findings: a 2 GiB SRAM full store on one N2 reticle is the strongest five-year chip (13x to 17x per joule, about USD 0.3 per MH/s) and no layer reaches it (layer 2 moves its capex, not its joules; the shadow at k = 0.5 holds 4.8x); per-bank PIM is blind (1.6 percent of reads in-bank at 2 GiB) and the custom HBM4E base die is the f = 1 chip with its controller in the stack (6.5x to 14x), untouched by layers 1 to 4; the denominator is the wrong card (the M5 Max at 0.78 microjoules halves to thirds every chip edge). Section 5 carries the k bands for the research lane's chip rows; section 7 the four decisions with defaults and deadlines; section 9 the sources with URLs and dates. tools/ci/export-exclude.txt: docs/analysis/class-v6 is research, not public export.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
At 09:46 UK the founder's gh had his other account active (his own work) and tools/ci/gh-account-check.sh refused every Igneum push from the Mac (the v5 lane's 56a50160 held local). The check now reads Igneum's directory: empty, it refuses naming the one step (the founder or main stores the Igneum token there with `GH_CONFIG_DIR=~/.config/gh-igneum gh auth login --with-token`; no lane does); another login, refused and named; the stored entry, passes; while tools/ci/github-suspended stands it skips with a line, because no gh call can succeed and the hook already refuses GitHub pushes, so the lanes land on the mirror meanwhile. Known-failed first: an empty directory, another login, the founder's directory never read (the fake gh records the directory it was given), the marker's skip, no gh. IGNEUM_GH_CONFIG_DIR overrides the path for the self-tests.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Intel's compiler turns rotate(x, (0u - n) & 31u) into a rotate LEFT by n: lane 0's register trace on the B580 diverged
at instruction 6 of iteration 0 (rotr) and nowhere before, in both exchange modes, with every other family and the
dataset kernels bit-exact. proto-opencl/intel_rotr.h rewrites the one helper line when the device's vendor or
platform string holds Intel (host.c's buildProgram and the prepare path), no other vendor sees a change, no pack or
consensus text moves. proto-opencl/test_intel_rotr.c (the pre-push gate runs it) feeds the line through the rewrite
under Intel, AMD and NVIDIA strings and asserts the outputs.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
(cherry picked from commit c6aa376a5d)
