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Author SHA1 Message Date
igneum-josh
aa4e9e0df4 Merge branch 'ca3-v4-hash' into ca3-coord 2026-10-06 17:39:24 +01:00
igneum-josh
ca61dec382 Counter ASIC 3.0 gates (hash): follow-up 1 on the program-id fix (7c22d0d merged): crate suite 97 of 97, the seven v4 packs re-exported byte-identical (generator 4, id c120d7963abdcd96), fingerprints unchanged on Metal and Apple OpenCL, Mac G2 16 x 1,024 of 1,024 through the v4 class token, the harness 4 of 4 on the class and on the era with the id assert_ne holding; the job scripts take the class token from the pack 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 17:38:48 +01:00
igneum-josh
7658369db7 Counter ASIC 3.0 status: the program-id fix merged (7c22d0d), the re-runs open 2026-10-06 17:26:11 +01:00
igneum-josh
f011d9b712 Counter ASIC 3.0 status: AMD G2 job ready (chain-seed packs, own kit) 2026-10-06 17:22:31 +01:00
igneum-josh
ff5c103f50 Counter ASIC 3.0 status: every gate green on the hash, the program-id blocker on the cut, the one line for Josh 2026-10-06 17:18:08 +01:00
igneum-josh
601f152103 Merge branch 'ca3-v4-node' into ca3-coord 2026-10-06 17:16:21 +01:00
igneum-josh
7a48950c3a Merge branch 'ca3-v4-hash' into ca3-coord 2026-10-06 17:16:21 +01:00
igneum-josh
c3ddf1e017 Counter ASIC 3.0 gates (hash): the RTX 5090 G1 and G2 JSON summaries 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 17:15:17 +01:00
igneum-josh
1ecb730462 Counter ASIC 3.0 gates (hash): the RTX 5090 G1 and G2 evidence from the collected job.log (eight fingerprints equal to the Mac's, 8 x 1,024 of 1,024); hash-gates.md and the bench-log entry closed 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 17:14:08 +01:00
igneum-josh
4f52d4f66e Counter ASIC 3.0 gates (node): G6 row, the two crates whose lines the relay upload does not carry 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 17:10:30 +01:00
igneum-josh
393bd7a374 Counter ASIC 3.0 gates (node): G4, G4b, G5 and G6 GREEN for class v4 (the three fast-time summaries incl. the known-failed case, node-gates.md, counter-asic-3-node.md) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 17:10:00 +01:00
igneum-josh
5e2fbdd0c6 Counter ASIC 3.0 gates (hash): the gate directory (hash-gates.md, G1 Mac, G2 Mac, G3 and verifier JSON) and the bench-log entry; the RTX 5090 G1 rows pending the collected job.log 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 17:07:55 +01:00
igneum-josh
4ce9d6589a Counter ASIC 3.0 status: job 1 closed (G1 AMD green, the 9070 XT ladder flat to 330,700 ops, watts owed) 2026-10-06 16:58:03 +01:00
igneum-josh
01b092d859 Counter ASIC 3.0 status: G1 AMD green on the candidate pack (interim, job 1 running) 2026-10-06 16:52:47 +01:00
igneum-josh
8aba68002b Counter ASIC 3.0 status: the Ember run 5 rows for the 5090 (the cap never binds, 0.41 MH per W flat) 2026-10-06 16:45:39 +01:00
igneum-josh
1fdb1e0d26 Counter ASIC 3.0 status: the PC 1 AMD scripts ready (checks pass, kit verified) 2026-10-06 16:40:42 +01:00
igneum-josh
c93a999e82 Counter ASIC 3.0 status: the gate run opened on mx8+sh256x27 (Josh 16:50 UTC), the gate table 2026-10-06 16:38:44 +01:00
igneum-josh
3213ee9942 Counter ASIC 3.0 status: the PC 1 AMD job queue (prepared, not published) 2026-10-06 16:13:22 +01:00
igneum-josh
18c762ee8c Counter ASIC 3.0 status: the close (items 6, 7 and 8 closed; the chip model before and after; the class v4 candidate mx8+sh256x27 ready for the gate run; nine decisions for Josh; the owed list) 2026-10-06 09:48:18 +01:00
igneum-josh
820f4d4eed Merge branch 'ca3-reserve' into ca3-coord 2026-10-06 09:45:48 +01:00
igneum-josh
12d8a9302a Merge branch 'ca3-shadow' into ca3-coord 
# Conflicts:
#	docs/bench-log.md
 2026-10-06 09:45:48 +01:00
igneum-josh
b85f0f18ed Counter ASIC 3.0 items 6 and 7: the RTX 5090 step-cost rows (PC 2 job run-ca3-family-pc2-20261006, every family bit-exact, mm8 included) in the bench-log and the reserve document 2026-10-06 09:45:02 +01:00
igneum-josh
70eaf06456 Counter ASIC 3.0 item 8: the RTX 5090 rows, the chip side on the measured 11 pJ per op, the verdict 
PC 2 job run-ca3-shadow-pc2-20261006 (card empty, every pack bit-exact against the Mac): the 5090 holds its rate to
150,800 ops per hash and loses 2.7 percent at 199,600 under the app's 431 W cap, which binds from 102,100 ops up and
takes the clock from 3,037 to 1,834 MHz (86 MH/s at 330,700 ops); 350 W at the control, 2.65 to 3.27 microjoules per
hash; marginal ALU energy 10 to 13 pJ per counted op. Clock rows OWED (nvidia-smi refused -lgc without rights). Chip
side at N = 100,000 and k = 1: 2.1x over the 5090 on GDDR7, 0.9x over the M5 Max. GO at mx8+sh256x27.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 09:44:57 +01:00
igneum-josh
bc148a85ec Merge branch 'ca3-derive' into ca3-coord 
# Conflicts:
#	docs/bench-log.md
 2026-10-06 09:31:10 +01:00
igneum-josh
54bc188a5d Counter ASIC 3.0 item 2: the RTX 5090 rows from PC 2 (bit-exact on CUDA, +1.1 s NVRTC per pack, the card-off key finding) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 09:30:15 +01:00
igneum-josh
1828e3e631 Counter ASIC 3.0 status: the detector's two calibration findings answered (9c7838e merged; max r 0.10) 2026-10-06 09:29:28 +01:00
igneum-josh
7bd1943231 Counter ASIC 3.0 status: PC 2 clear, the detector and vendor-share dry rows on the live tables, the restart constraint 2026-10-06 09:26:52 +01:00
igneum-josh
477729e9dc Counter ASIC 3.0 status: the marker guard exists in CI already 2026-10-06 09:25:02 +01:00
igneum-josh
fa603bc378 Counter ASIC 3.0 status: items 6 and 7 merged (5090 rows queued), the marker slip recorded 2026-10-06 09:24:50 +01:00
igneum-josh
fcce185eeb Merge branch 'ca3-reserve' into ca3-coord 
# Conflicts:
#	docs/bench-log.md
#	tools/observer/observer.mjs
 2026-10-06 09:24:29 +01:00
igneum-josh
45f30196b9 Merge ca3-shadow (item 8's Mac rows) into ca3-coord: LoadClass carries derive_len and shadow; igneum-pow suite 96 passed 2026-10-06 09:11:03 +01:00
igneum-josh
8b520c1eaf Counter ASIC 3.0 item 8: the CUDA text checked in the clang emulation and the OpenCL text on Apple OpenCL (gate G1 row) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 09:10:25 +01:00
igneum-josh
a050a54c65 Counter ASIC 3.0 item 8: the Mac rows 
The M5 Max ladder (Metal, packbench, IOReport GPU and DRAM watts without root): latency-bound to about 100,000 ops per
hash, the 5 percent point about 130,000, 11 to 27 W GPU at 100,000 ops, 0.78 to 1.40 microjoules per hash; the
verifier's law 2.06 ms + 3.2 us per 1,000 shadow instructions per warp on one core; every pack bit-exact. The
analysis file with the knob, the chip side (k = 1, 1.5, 0.3), the gates and the consequences; the bench-log entry;
the 5090 rows pending the PC 2 job (the playbook now carries the core-clock rows and the sh256x40 rung).

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 09:08:26 +01:00
igneum-josh
533a659287 Counter ASIC 3.0 status: the 5090 draws about 290 W at the hash, cap floor 400 W, clocks are the lever (item 8's job) 2026-10-06 08:59:42 +01:00
igneum-josh
a6a7ad6a39 Counter ASIC 3.0 status: item 2's verifier headroom table and the crate suite 2026-10-06 08:51:42 +01:00
igneum-josh
82211d3153 Merge branch 'ca3-derive' into ca3-coord 2026-10-06 08:51:42 +01:00
igneum-josh
2070915cff Counter ASIC 3.0 status: PC 2 clear about 08:35Z, the job order 2026-10-06 08:51:36 +01:00
igneum-josh
9142d95691 Counter ASIC 3.0 status: item 2 interim (GO as reserve, NO-GO genesis-live at dr736), PC 2 clear about 08:35Z 2026-10-06 08:51:15 +01:00
igneum-josh
bdc07d3a1d Counter ASIC 3.0 item 2: the verifier headroom per class under the 10 ms gate (the budget item 8 shares) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 08:51:13 +01:00
igneum-josh
08755f5680 Merge branch 'ca3-derive' into ca3-coord 
# Conflicts:
#	docs/analysis/chip-model-v3.md
 2026-10-06 08:51:00 +01:00
igneum-josh
dd5041b989 Counter ASIC 3.0 item 2: the design, the Mac measurements, the chip-model row and the PC 2 job 
docs/plans/counter-asic-3-derivation.md (the design, the acceptance test, the interpreter, the allowance argument,
the measurements, the PROPOSED reserve entry R0 for 1.13.2, what is owed), docs/analysis/chip-model-v3.md section 6
(the per-day derivation rows at 1.0x to 3x allowances), the bench-log entry, relay/playbooks/ca3-derive-pc2.ps1
(one PC 2 job: self-fetched packs zip, the installed worker through NVRTC, the card off only under test with its
key from settings.json). Verifier 4.875 / 4.944 ms per unit on one M5 Max core under the measure lock against
x8's 2.061 / 2.063; Metal build 29 ms against 22; hash rate equal; bit-exact on Metal and Apple OpenCL.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 08:50:01 +01:00
igneum-josh
6ced9e51ee Counter ASIC 3.0 status: items 4 and 5 closed, the owed list opened 2026-10-06 08:48:56 +01:00
igneum-josh
ed06814a51 Merge branch 'ca3-detector' into ca3-coord 
# Conflicts:
#	docs/plans/funding.md
 2026-10-06 08:48:42 +01:00
igneum-josh
c0642af0b2 Counter ASIC 3.0 items 4 and 5: the issuance trigger, the signal trigger, the FPGA lane and the layer 9 against layer 7 ranking 
docs/plans/funding.md rule 5: the bounty is escrowed and the benchmark live before daily
issuance crosses USD 20,000 a day, with the price-per-IGN table per halving period.
docs/plans/epoch-length.md section 11: the detector alert held 6 net windows recommends
the next shorter ladder step, per-tier costs at 2,400 and 600, the adversary's share per
compile class. Section 12: HBM FPGA parts with sources, reads in flight per watt against
the RTX 5090 (0.3x to 0.4x at Shuhai's measured rate, up to 1.9x at the unmeasured bank
ceiling), the two FPGA lanes in one table, and the ranking: layer 9 above layer 7.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 08:47:21 +01:00
igneum-josh
6422b6f0ee Counter ASIC 3.0 items 6 and 7: proposed reserve order and spec text (docs/plans/counter-asic-3-reserve.md), the vendor-share section on the benchmark page, the observer README row 2026-10-06 08:40:41 +01:00
igneum-josh
f3113514e7 Counter ASIC 3.0 status: item 6's Mac step costs (interim) 2026-10-06 08:36:58 +01:00
igneum-josh
192a683d08 Counter ASIC 3.0 items 6 and 7: family step-cost probes (Metal, CUDA), the PC 2 playbook, the M5 Max rows in the bench-log 2026-10-06 08:36:12 +01:00
igneum-josh
3ffa208769 Counter ASIC 3.0 status: the two claim drafts for Josh with the rows that bound them (main's steering) 2026-10-06 08:35:09 +01:00
igneum-josh
dda9fa3fcf docs/benchmarks/repro.md: carried from repro-bench b776199 2026-10-06 08:34:58 +01:00
igneum-josh
870363c0c7 Counter ASIC 3.0 status: item 1 closed (verdict over 2x, the f = 1 chip), item 8 (latency-shadow program work) opened 2026-10-06 08:33:26 +01:00