igneum-labs
d7a41aa60d
Merge class-v6-floor-invention-docs-2 8b7e7d28 into master (gate: green on 8b7e7d28, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 13:23:22 +00:00
igneum-labs
5547e6f1b6
Merge class-v6-census-docs 50c060b2 into master (gate: green on 50c060b2, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 13:16:21 +00:00
igneum-labs
8b7e7d2889
Class v6 floor lane 5 (invention): the three sourced precedents for the close (RandomX X5 1.0x to 1.5x after 46 months, the X9 unshipped; Ethash E3 36 months and the iPollo V2H about 14x; Kaspa KS0 21 months at 167x to the KS5 Pro's 725x); the w64 census and F8 row closed by the census lane (256 of 256 with and without an era): the class is sound and dead on energy
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 828307fee828307fee2
2026-10-08 13:11:56 +00:00
igneum-labs
50c060b277
Class v6 census: the recommendation amended on the coordinator's close (W = 16 dead on energy by floor lane 5's card rows; the order is W = 8 pins, the index fold first, then the re-weight at W = 8 through this harness before it enters)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of cfd0b1db9 (cfd0b1db936c45275e33697c5b283eb12b25a424) for the box mirror master
2026-10-08 13:09:44 +00:00
igneum-labs
c7555638b4
Class v6 census: W = 16 and the op-mix re-weight through the sub-version 3 rules (docs/analysis/class-v6/census-w16-mix.md): every candidate 256 of 256 without an era and 256 of 256 across eras 0 to 7 with the window-bit refusal on, 0 exhausted; W = 16 removes the product's low bits from the address by construction; the re-weight lowers r to 0.41 and raises the stride-bit refusals; the rows, logs, scripts and commands
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of d20eb04bd (cfd0b1db936c45275e33697c5b283eb12b25a424) for the box mirror master
2026-10-08 13:09:44 +00:00
igneum-labs
6babb93942
Merge remote-tracking branch 'build/master' into class-v6-invention
2026-10-08 13:04:40 +00:00
igneum-labs
7442ec25b3
Class v6 invention: the drawn-era re-read on the fixed instrument 2ae69eb4 (the sound per-load form 254 of 256 seeds at 0.819 per candidate under eras, 234 of 256 at 0.927 no-era; the 16 x 27 form dead on both; class v4's shape at sub-version 3's 0.67 on the same binary), the two TSVs, sections 0, 2.1, 3.3 and 4 updated
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 13:04:39 +00:00
igneum-labs
c4f90a0061
Merge class-v6-floor-invention-docs c62f15c0 into master (gate: green on c62f15c0, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 13:02:33 +00:00
igneum-labs
c62f15c0ad
Class v6 floor lane 5 (invention): the 5090 W = 16 stock row measured on a secure-cloud pod: the hinted form at sp170-w4 holds the 4-byte rate (145.7 against 142.6 MH/s) at 401 W against 316, +25 percent energy per hash, the second sector 4.7 nJ on the card (k about 0.24); the kill stands at stock; all five pods destroyed, USD 9 spent
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 39b8d058339b8d05838
2026-10-08 12:45:35 +00:00
igneum-labs
ef198fa37b
Class v6 floor lane 5 (invention): the second sector measured on rented 4090, H100 and 3090 at stock and KILLED: a hinted one-request load (ld.global.L2::64B) holds the 4-byte rate on Ada (63.65 against 64.73 MH/s) and fails on Hopper (-21 percent) and Ampere (-13), but the card pays the sector at about 8.6 nJ through its own fabric (296 against 225 W on the 4090), +34 percent energy per hash against the modelled chip's +33, k about 0.13; W = 16 stays out of class v6, W = 32 dies with it; the KEEP list is now two model corrections, one measured card figure and the Ethash precedent row
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 68315bf8339b8d05838
2026-10-08 12:45:35 +00:00
igneum-labs
79e06feb6f
Class v6 floor lane 5 (invention), corrected for the read-width naming: the whole 64-byte item is class w64 (W = 16 words), not w16; its card side is measured at two occupancies that disagree (the hash -47 percent at full occupancy, the probe -13 percent at its best lane count) and unmeasured in a one-request form, so rank 1 is conditional on one PC 1 job with a 95 percent pass line; the chip side unchanged (+33 percent GDDR7, +24 HBM3) and, on floor lane 3's wire figure, the SRAM die 66x to 19x; the three outcomes priced (5.3x dead, 3.4x, 3.0x to 3.2x)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 43fcf0fed39b8d05838
2026-10-08 12:45:35 +00:00
igneum-labs
251b76846a
Class v6 floor lane 5 (invention): the second sector as the one k = 1 lever (W = 16 words, the whole 64-byte item: the chip's GDDR7 read 2.0 to 3.2 nJ, E_mem +33 percent, the 5090 about +10 percent energy at +2.7 percent rate measured, every chip column down 10 to 15 percent, modelled); the tensor k band corrected to 0.2 to 0.7 (never above the ALU shadow); RT, proof of latency, drawn address map, video decode, row-straddle, scratch and independent chains killed with numbers; no 28 nm GDDR7 PHY exists so the chip's floor project is USD 20 M to 75 M; W = 32 held for v7
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of b13fc428f39b8d05838
2026-10-08 12:45:34 +00:00
igneum-labs
54ada47f91
Class v6 floor lane 3: the close is 15:45 UK (the founder's rule of 13:3x); the four clock references updated, later rows as amendments
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 8e9588de0 (8e9588de0) for the box mirror master
2026-10-08 12:29:15 +00:00
igneum-labs
88924ec8f4
Class v6 floor lane 3: section 2.2c (W = 16 across the three chips: the die 66x to 19x if the 5090 passes, 36x at the measured w64 row; GDDR7 4.4x, HBM3 6.7x) and section 4.3 (the capex wall on the corrected USD 20 to 75 M project floor: no chip project below USD 23 M a year of miner revenue, every DRAM-board project above USD 340 M)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 7bc9de4b4 (8e9588de0) for the box mirror master
2026-10-08 12:29:15 +00:00
igneum-labs
ee2d3c8606
Class v6 floor lane 3: section 2.2b, the shadowed SRAM rows re-folded on the k lane's synthesised core (0.11 microjoules of shadow at N3, absolute k about 0.1): 21x at W = 4 and 18x at W = 8 under class v4, 10x at the full shadow, 6x to 7x at the knee; finding 1, the public-claim row and the served sentence carry the range with the record's band marked
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of bed2aebe3 (8e9588de0) for the box mirror master
2026-10-08 12:29:15 +00:00
igneum-labs
0478a6c0eb
Class v6 floor lane 3: section 2.2a, the shadowed rows at the 5090's knee in both k conventions, absolute first (3.8x / 2.0x at W = 4; the record's 6.1x / 3.3x marked)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of d550dadda (8e9588de0) for the box mirror master
2026-10-08 12:29:15 +00:00
igneum-labs
7b523af541
Class v6 floor lane 3: W = 8 free by the measured w16 and w64 rows (one sector per load, the crate's width set caveat); the 5090's size rows (4, 8, 10 percent per hash at the knee at 2, 4, 8 GiB) as the floor's honest-side cost; the k convention at the lock stated both ways
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of e1e433638 (8e9588de0) for the box mirror master
2026-10-08 12:29:14 +00:00
igneum-labs
745e9effc0
Class v6 floor lane 3: the SRAM full-store die and the dataset floor (the read width as the wire lever, 66x to 31x at zero shadow and 5.7x to 5.4x with it; the floor as a ticket lever, 5.5 / 8.5 / 11.5 GiB; the capex wall on the spec's emission, USD 0.13 to 2.9 per IGN; the four candidates killed)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 708d01b4d (8e9588de0) for the box mirror master
2026-10-08 12:29:14 +00:00
igneum-labs
5f45de999f
counter-asic-4 documents: the branch's text at 086411627 taken whole for the documents-only landing (what the replayed commits did not carry: the branch's merge resolutions)
2026-10-08 12:28:21 +00:00
igneum-labs
6cacc7a548
Counter ASIC 4.0 research: 20.3c the hot-table rows as a record and the call (the replaced form is a per-watt gift to every miner and a larger one to the stored-dataset chip: a loss for resistance; ldcs a dead lever)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 13181a296
2026-10-08 12:28:18 +00:00
igneum-labs
018a015697
Counter ASIC 4.0 research: 15.1b the op-mix re-weight's hold on measured rows (shfl 4.9x the add; the chip's k on shuffle work would have to be 0.4 to 0.5 for 2.9x to be honest, unmeasured)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 5b4db2c78
2026-10-08 12:28:18 +00:00
igneum-labs
92be169c77
Counter ASIC 4.0 research: 15.1a the microbench rows (20 probes on the 5090 at both states) and the correction they force: a tile is 32 MACs per lane, not 1,024, so the int8 MAC costs 1.5 to 4 pJ measured (the 6 October 4090 figure 1.8, not 0.056); the tensor shadow is the worse lever (k 0.03 to 0.3); the shuffle at 55.8 pJ per op is the card's dearest instruction (the re-weight's GPU side against it); an L2 hit at 2.4 nJ kills the hot-table lever; the first sentence and the ranking corrected
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of a32060596
2026-10-08 12:28:17 +00:00
igneum-labs
46034fc9ad
Counter ASIC 4.0 research: 20.3b the SM-sparse reading (a quarter of the SMs holds 98 percent of the rate at the same draw; the draw follows the work, not the SM count): rank 2 dead on measured rows
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 03871c835
2026-10-08 12:28:17 +00:00
igneum-labs
65d408d164
Counter ASIC 4.0 research: 20.4 names the 1,430-tile point as the one the k column was priced at, the Apple side open, nothing served moving
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of efa39b1a0
2026-10-08 12:28:17 +00:00
igneum-labs
b6f9526f0d
Counter ASIC 4.0 research: 20.3 the card rows of the seven packs (the tile block carries the ALU shadow's premium at the same rate, 14 percent cheaper at the knee; 0.048 to 0.091 pJ per MAC measured on the 5090), 20.4 the chip-model rows, the first sentence on measured rows
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 5f3741950
2026-10-08 12:28:17 +00:00
igneum-labs
21a689c1fc
Counter ASIC 4.0 research: --bench honours --variant through the pinned race (the SM-sparse run of 00:22 to 00:41 UTC served base on all 48 rows); RESULT carries variant, sparse_blocks and block_warps, variant_not_installed is the known-failed line; 20.3a records the run and its knee rows (v4 309.9 W, v3 219.4 W, premium 90.5 W at 1,300 MHz)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 98974a8ec
2026-10-08 12:28:17 +00:00
igneum-labs
838946e9ca
Counter ASIC 4.0 research: 20.2a-close, the per-load 16 x 27 construction dead as a chain class (1.4 percent acceptance, 42 of 64 seeds without a program), the sound form named, rank 4 marked
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 413d19686
2026-10-08 12:28:17 +00:00
igneum-labs
bca81a905c
Counter ASIC 4.0 research: 20.2a the per-load fault fixed with clock readings, the drawn-era census (0 pairs across 16 eras), the Metal fingerprints (the tile reference bit-exact; the Apple emulation costs 35 and 78 percent of rate at 1,024 and 4,096 tiles per hash); 20.2b the biased-product-bits requirement from adv-cache-2
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of a84c19649
2026-10-08 12:28:16 +00:00
igneum-labs
9c25ba8bf5
Counter ASIC 4.0 research: 20.2 the verifier rows (AVX2 tile path 0.047 us per tile per unit, mm1430 10.14 ms loaded; the per-load placement derives 11 percent fewer distinct items per warp: a uniformity fault as drawn, with its fix)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of f3885df2e
2026-10-08 12:28:16 +00:00
igneum-labs
c1849034e5
Counter ASIC 4.0 research: section 20, the two prototypes built (what, where, gates; the verifier and card rows pending)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of a9c16353a
2026-10-08 12:28:16 +00:00
igneum-labs
dba2c3f57e
Counter ASIC 4.0 research, second pass: the k-above-1 hunt, the capex lever and the re-ranked list
...
Sections 15 to 19: every GPU block gaming and AI paid for, priced against the best public 4 to 5 nm chip figure with its k band, verifier cost and the edge at the measured premium (the one-sentence answer: nothing reads k above 1 with certainty; the int8 tensor tile is the only block near or above 1, so the tensor shadow with a SIMD byte-dot verifier is the new rank 3); the capex column added to the chip model (both sides capex-dominated at 7x to 10x their electricity; the per-unit capex wall unreachable by 3x to 7x; the project wall doubled from USD 100 M to about USD 200 M of break-even cap by the shadow-per-load design, the mission lane's method); the microbench of 20 probes documented as built (section 18); the owed list.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of ed83ae162
2026-10-08 12:28:16 +00:00
igneum-labs
94f6bc6eb4
Counter ASIC 4.0 research: clock stamps in UTC (the box compile at 20:48 UTC, the knee reading at 20:5x UTC)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 5fd67c216
2026-10-08 12:28:16 +00:00
igneum-labs
e239f05d19
Counter ASIC 4.0 research: the identity that forbids a zero-premium chip lever, the ranked designs, and the SM-sparse worker variant
...
docs/analysis/counter-asic-4-research.md (excluded from the public export): edge = (E_card + F) / (E_mem + k F); at zero premium the stored-dataset chip keeps E_card / E_mem, 3.6x on a 5090 locked at 1,400 MHz (measured card, modelled chip), about 2x at that card's idle-plus-memory bound, 1.7x on the M5 Max; class v5 at zero shadow leaves it at 5.1x to 9.1x; the shadow buys 2.1x at k = 1 for the measured 88 W (81.8 W at the knee) and turns against us below 1.8 pJ per op; per-card classes, the refresh as a cost, proof of useful work, memory shaping and the tensor block priced out with their arithmetic; ten designs ranked with the chip edge, the 5090 and 4070 premiums, the verifier cost, agent hours and what breaks each; the recommendation in five sentences; consequences per tier.
proto-cuda/nvrtc/worker.cpp: opt-in SM-sparse variants sp<N> and sp<N>-w<W> (a persistent grid of N blocks of W warps over the dispatch's nonces; the bound kernel rewritten at compile time with exact anchors into a unit function plus a wrapper of the kernel's name; made on demand by name, never in the default race; refused on variant-5 packs and with minBlocks). Gate: mingw cross-compile on igneum-build-1 under lease pool (class measure, label "ca4 research"), exit 0 with -Wall -Wextra, 22:48 UTC; exe sha256 ee8d0e70dd101f125f42c0c7cf07481a794ee18a1317acf68561b37ea18d72be; unrun on a card (the hash lane's PC 1 job run-ca4-pc1-ca4sparse-5090-20261007 is its first run).
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of b18684240
2026-10-08 12:28:16 +00:00
igneum-labs
72b33aaf84
Merge class-v6-family-gate bb52ac64 into master (gate: green on bb52ac64, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 12:12:39 +00:00
igneum-labs
680abc5cdb
Class v6 invention: the 5090 rows for the two per-load packs (the sound form costs the card 15 to 20 percent more per shadow instruction than the whole block, +19 W unlocked and +6.6 W at the knee at class v4's count; rank 1's GPU column corrected, the verdict restated with the honest sign)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 11:45:37 +00:00
igneum-labs
bb52ac640f
Class v6 family gate, the 17:00 cut: the harness as a plain diff at 3dc3117c (the founder-strings check refuses the patch form's author lines)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 11:35:25 +00:00
igneum-labs
da2a06e4b6
Merge remote-tracking branch 'build/master' into class-v6-invention
2026-10-08 11:35:21 +00:00
igneum-labs
958d49f498
Class v6 invention: the uniformity read at 2^20 on 64 seeds (the sound per-load forms clean, 0 over 1.2x and 0 sites under 0.995; the raw class v4 shape through the v2/v3 rule 41 of 64 hot at 7x to 36x, AP-F8-1's class as the harness's known-failed firing), the harness crate, the box OOM record, the offered window-bits test
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 11:35:11 +00:00
igneum-labs
a421b896f5
Class v6 family gate, the 17:00 cut: the last-resort rows corrected for class v5's verified scan (the finding at the corner is the correlation of one era's attempts, 1,000x the independent estimate, not an unchecked program); the harness patch series at 236ef3a5 (the lossy-share curve and the scan's verdict column)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 11:27:11 +00:00
igneum-labs
17a9bf682d
Class v6 family gate, the 17:00 cut: the measured coverage (24,000 drawn eras through the ring-B tests on build-1 and build-3, 54 core-hours), per stratum and per axis, with the bound arithmetic on the counts; four measured rows (the lossy corner of B = 4 exhausts the 256 cap in 1.2 percent of eras, the band capped at the lossy families; the (c''') floor's per-width calibration; the shape axis's draw cost; the era-stride bias at bit R in half the eras of every stratum); the census rows, logs, scripts and the harness patch series under logs/
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 11:25:26 +00:00
igneum-labs
68b624b82e
Merge class-v6-invention 5abdf181 into master (gate: green on 5abdf181, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 10:47:37 +00:00
igneum-labs
1c02320532
Merge class-v6-history fd32fdc5 into master (gate: green on fd32fdc5, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 10:45:04 +00:00
igneum-labs
28effe9e2c
Merge class-v6-family-gate 8551379f into master (gate: green on 8551379f, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 10:40:09 +00:00
igneum-labs
5abdf18115
Merge build/master into class-v6-invention (the export-exclude line for docs/analysis/class-v6 kept once, the history lane's wording)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 10:40:05 +00:00
igneum-labs
fd32fdc5ce
Class v6 history lane, revision 3: the dataset-floor schedule priced per tier and against the chips (section 4.2a, main's ask of 11:2x UK)
...
docs/analysis/class-v6/history.md 4.2a: main's 6, 10 and 14 GiB steps checked against every tier's room under the standing 75 percent budget rule (the card-lifetime method, the bench table's 32 measured consumer cards as the population): 6 GiB does not fit the 8 GB tier under the rule (78 to 82 percent of the card; it fits only at a headless-rig reading of about 85 percent), 10 GiB retires the 10, 11 and 12 GB tiers and the Apple 16 GB laptop at year 2, 14 GiB retires the 16 GB tier at year 4, leaving 24 GB and above; beside it the schedule that drops the tiers in the order main named (5.5 GiB at the v6 epoch, 8 GiB at two years, 11 GiB at four) with the year each tier falls and its share of the measured cards (6 GB 3 percent at day one; 8 GB plus the 10 GB RTX 3080 plus Apple 16 GB 25 percent at year 2; 12 GB 22 percent at year 4; 16 GB 28 percent at the 16 GiB step; 24 GB and above hold). Against the chips: the hybrid-bonded or soldered chip sized at launch dies at the first step it cannot carry (the E3's shape, 20 to 27 months) but a maker reading a public consensus field sizes to the step it wants (USD 160 more of GDDR7 on a USD 470 part; about 3x the memory die area for the Jasminer shape); the f = 1 GDDR7 chip's 32 GB board pays USD 0 through 16 GiB and keeps 5.1x; the SRAM store pays capex only at the cache doubling (USD 46 to 111 per die) and keeps 0.92x and 1.86x. The fleet's hashrate-weighted card census is owed. The arithmetic is checked by script against the card-lifetime working sets.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 10:38:53 +00:00
igneum-labs
d5c4b90d23
Merge class-v6-history 697fdd23 into master (gate: green on 697fdd23, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 10:35:30 +00:00
igneum-labs
8551379fc2
Merge build/master 0d7412ac into class-v6-family-gate (export-exclude.txt: both research paths kept)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 10:32:44 +00:00
igneum-labs
697fdd23a1
Class v6 history lane, revision 2: the synthesis lane's reading of the six items folded in, lane B's hardware file cross-cited
...
docs/analysis/class-v6/history.md: layer 2's open ceiling question replaced by the synthesis lane's resolution (the per-year ceiling as layer 2's first constant, the schedule's power-of-two step for the year; the state brings a step forward and never adds one), with the Ethereum-state figure kept as the reason the ceiling exists; the read-width rank reworded on the measured warrant (w16 latency-bound within 2.7 percent on the 5090 and the 9070 XT, within 1 percent on the M5 Max; the band is {4 B, 16 B}, nothing wider); the Jasminer X4 finding cross-cited to lane B's hybrid-bonded DRAM row (hardware-future.md 4.4, 13x to 17x modelled) as that row's shipped precedent at 5x on a planar node; the header records the 11:26 UK landing (eb71eaf3
2026-10-08 10:29:17 +00:00
igneum-labs
eb71eaf399
Merge class-v6-history 2b76937c into master (gate: green on 2b76937c, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 10:26:13 +00:00
igneum-labs
1dcb3882e1
Class v6 family gate (lane D), first cut: the parameter table with bands and margins, the sampling bound (rule of three, the union bound over the per-era tests' measured miss rates, the stratified corners), the three rings of per-era tests with known-failed shapes and clean-seed costs, the board over the testnet period and the proof-of-testing record format, the honest line; the harness running on the boxes and its first 16-era reading (the era-stride class at 130 to 511 sigma on one address bit in 7 of 16 drawn eras); docs/analysis/class-v6 excluded from the public export
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 10:25:17 +00:00
