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igneum-labs
a28ea58f9b Class v6 layer 4: lane D's measured resolution of the bucket bound (retired into one value-level index-bit test; seven known-failed cases of the fold; 300 sigma if a refusal is wanted before the fold) and of the width-4 floor (stays 0.995 at its measured cost) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 13:45:00 +00:00
igneum-labs
b114f24599 Class v6: floor lane 4's final table (the class v5 stock column measured on 14 card classes; the lock worth 34 to 41 percent on Blackwell and Ada; the 16 GB Blackwell knee the honest floor); layer 1's N row carries the measured price of a 4x shadow (1.58x the energy per hash on the 5090 and 4090) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 13:42:50 +00:00
igneum-labs
22a3ba3c50 Class v6 10.4: rented 5090 and 4090 stock rows on class v5 genesis (3.14 and 4.48 microjoules) and the measured price of a 1.5x heavier shadow (1.58x the energy per hash on both architectures; the 1p5x-knobs lane) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 13:41:12 +00:00
igneum-labs
784a8dbd35 Class v6 layer 5: lane C's document landed on master at bfe7607a; the F8-form no-era read clean on 59 of 60 seeds 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 13:12:35 +00:00
igneum-labs
161bb535e4 Class v6 10.0b: the precedent row replaced by floor lane 5's sourced pass (RandomX chipped at 46 months at 1.0x to 1.5x by the Antminer X5, correcting the chip-free premise; Ethash 36 months, 14x today; Kaspa 21 months, 167x to 725x) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 13:10:22 +00:00
igneum-labs
9c2ae21068 Class v6: the Kaspa precedent with the sourced 4090 row (170x the first chip, 730x the 2024 one); the census lane's acceptance rows for W = 16 and the re-weight on layer 1 (clean on acceptance; decided on energy) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 13:08:46 +00:00
igneum-labs
d1170a2ef5 Class v6 10.0a to 10.0c: cost per hash over the chip's 180-day life (under 1x only above about USD 300 M a year of miner revenue; the three-price table), the precedents sourced (RandomX design document sections 1 and 3.4, no chip in 70 months; Ethash 13x at 36 months; Kaspa hundreds of times at 20 months), the core-shape rule for the k lane's sweep; the served sentence in two units 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 13:07:45 +00:00
igneum-labs
c5f7125348 Class v6 10.3: the SRAM rows on the synthesised core (lane 3 b2563b78: 8.1x stock, 5.6x knee at class v4's shadow; 3.5x and 2.2x at the full shadow); 10.2 the net of the two corrections per node 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 13:05:05 +00:00
igneum-labs
ce1ccfb8ce Class v6: lane C's drawn-era re-read of the sound per-load form (254 of 256 at 0.819; the 16 x 27 form dead on both instruments; eras spread the bit-0 refusals); the hash lane's two F8-256 attributions on layer 4's bucket-bound row (both tests carried, labelled estimate) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 13:04:00 +00:00
igneum-labs
efdcf726c1 Class v6: the k lane's sequencer-core row is the headline (k 0.56 at the lock, 0.31 at stock, 0.50 against the M5 Max, absolute, N3, synthesis-only; the DRAM chip 2.8x at the knee and 4.1x at stock, inside the record's claimed band); the close table, the lead, the one-line floor and the served sentence re-folded on it 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 13:02:58 +00:00
igneum-labs
c1bf30676d Class v6 10.3: the W = 16 net on the 5090's measured 1.25x (lane 3 bbf1b1dc); the verdict stands on four cards 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 12:40:23 +00:00
igneum-labs
56276ff039 Class v6 10.5: the 5090 W = 16 row measured (the hinted sparse form holds the rate for +88 W, energy +25 percent; the verdict holds on every card) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 12:38:48 +00:00
igneum-labs
9e603e3af6 Class v6 10.3: W = 16 netted on measured energy (lane 3 a670ba28): the SRAM die lands where W = 8 puts it for free with the shadow on; W = 8 is the width, never 16 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 12:31:53 +00:00
igneum-labs
51ac13a43b Class v6 10.5: W = 16 killed at stock on measured rows (the 4090, H100 and 3090: the hinted form holds the rate on Ada, the card pays the second sector at 8 to 9 nJ, energy per hash +34 percent against the chip's +33; k about 0.13) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 12:30:37 +00:00
igneum-labs
aab62cad14 Class v6: the last two 20:00 and 19:30 references pulled to the close 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 12:28:29 +00:00
igneum-labs
931798eade Class v6: the coordinator's 13:30 UK clocks (floor rows by 15:30, the synthesis on master by 16:30; the decision stays the founder's) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 12:27:08 +00:00
igneum-labs
f21f256a05 Class v6 10.1: the 5090 SM ladder on four rented hosts (the ceiling held to 43 of 170 SMs, the occupancy 1.3 to 3.9 percent at best), the H100 power decomposition, the fraction a chip cannot strip per tier 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 12:26:11 +00:00
igneum-labs
9629fd8dbc Class v6 10.4: the honest denominator per tier (floor lane 4: the 16 GB Blackwell card at its knee is the honest NVIDIA floor, the 5080 2.06 measured; the only lever the operating point; the Ember tier table); the close table gains the 5080 row 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 12:24:39 +00:00
igneum-labs
b351f3fdf3 Class v6: 15:45 UK is the close (the founder's clock rule); later rows are amendments with their own time; no 20:00 event 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 12:21:47 +00:00
igneum-labs
00890f9ccd Class v6: 10.1 SM-sparse measured dead on the 4090, H100 and 5090 (the residual is the clock domain); lane 3's close rows (the capex wall on the corrected project floor: USD 23 M and 340 M a year; W = 16 per chip; the SRAM rows on the synthesised core); 10.0 carries them with the 4090 and H100 rows 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 12:20:55 +00:00
igneum-labs
f0146c2c22 Class v6 10.0: the provisional close frame for 15:45 UK (one table, honest tier per row, chip per column, default k 0.5 and the floor k per cell; the capex wall's two thresholds; the served line in one sentence; the three class v6 changes), every missing row's default stated 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 12:19:15 +00:00
igneum-labs
89ea648619 Class v6: 10.5 invention lane's KEEP/KILL table (the second sector conditional on the w64 job; everything else killed with its number); 10.2 reframed as per-unit floors with the sequencer-core row owed as the headline and k 0.5 the default; lane D's complete lossy curve and ring-C progress in 5.1b 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 12:17:42 +00:00
igneum-labs
4e7bac031e Class v6 10.2: the shadow's k from RTL (floor lane 2: k 0.18 at the lock at N3 absolute, a floor; the GDDR7 chip with the class v4 shadow 4.0x at the knee and 5.8x at stock against the served 2.1x; mulhi the worst lever on the card by 6x); the lead and the served-line review carry it 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 12:15:47 +00:00
igneum-labs
dd692978a8 Class v6 layer 4: lane D's 17:00 cut as 5.1b (24,000 drawn eras: the op-mix band's known-failed test reads 0 of 3,000 under the cap; the lossy curve's edge at +2 to +3; the (c''') per-width calibration; the bit-R bias law; the measured bound n) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 12:14:25 +00:00
igneum-labs
3f6ee5878d Class v6 layer 1: kit c, the multiply-heavy base table measured (three tables within 7 W unlocked and 0.6 W at the lock on the 5090) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 12:13:02 +00:00
igneum-labs
1bce620797 Class v6 10.3: the SRAM die's lock rows in both conventions, absolute first (2.0x at k 1, 3.7x to 4.0x at k 0.5, every read width; floor lane 3 d550dadd) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 12:10:23 +00:00
igneum-labs
ac0fe332f4 Class v6: the k convention rule for the floor and the served-line review (absolute rows the headline, the record's beside them marked; the k lane's rows re-fold lane 3's shadowed rows before the close) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 12:08:18 +00:00
igneum-labs
91cb431a92 Class v6: kit b rows (the mixer draw costs the card nothing, measured; the shuffle-heavy base table 7 W under stock; the 5090 at the knee pays 4 / 8 / 10 percent more energy per hash at 2 / 4 / 8 GiB, replacing size-independent); floor lane 3's W = 8 and k-convention update 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 12:07:08 +00:00
igneum-labs
78457959fb Class v6: 10.3 the SRAM die and the dataset floor (floor lane 3: the read width the only wire lever, 66x at 4 bytes at zero shadow, the shadow the whole hold at 2.7x to 3.0x at k = 1; W pinned at 4 words at genesis; the floor as a ticket, 5.5 / 8.5 / 11.5 GiB; the capex wall's p* table) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 12:03:48 +00:00
igneum-labs
5b7e219da1 Class v6: section 10, the floor (the five floor lanes' terms, what the document already holds measured for each, the default at 19:30 and the row owed) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 11:49:10 +00:00
igneum-labs
a10fa0d5ef Class v6: the sound per-load form's 5090 rows measured (shl4096x1 at class v4's count: 116 W over class v3 against the whole block's 152 unlocked, 59 against 84 at the knee; shl2304x3 19 W and 6.6 W over the whole block) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 11:44:21 +00:00
igneum-labs
b6799782d7 Merge build/master into counter-asic-4 (the sub-version 3 line, the derivation recorder, master's re-exported packs); chip-model 5.12; class v6 sections; the per-load bias test judges the window's bits only 
The merge: accept.rs takes master's shadow pass in run_unit (the per-load sub-blocks keep their place inside the loop; the end-of-iteration pass is empty for that class) and its Acc fields beside site_bit_ones; generator.rs records the per-load and tile id bytes through master's recorder (r.lit "perload", r.lit "mm8/" and the tiles field), nothing for the class v4 shape; export-exclude keeps both sides.

The fix (the invention lane's finding, 8 October 2026, 10:48 UTC): BiasedIndexBit judged every index bit, and under an era a narrow-window site's top k bits are fixed by design, so every per-load form read 0 of 256 under any drawn era for the instrument's reason; it now judges only the bits inside each site's window mask (verify::window) and the (c'') pass, which runs the unit with no table, accumulates nothing. The research file's 20.2a-close reads REOPENED (the 16 x 27 form dead on the no-era census on both instruments; the sound form mx8+shl4096x1 accepts 234 of 256 seeds no-era; its drawn-era verdict the invention lane's 15:00 BST read); chip-model-v3 5.11 the same.

chip-model-v3 5.12 (main's order, 11:3x UK): the 2 GiB SRAM full store on one N2 reticle (17x at zero shadow, 2.7x to 4.8x with it, USD 400 to 600 of silicon, an N2 project of USD 100 M to 500 M) and the custom HBM4E base die (6.5x to 14x, untouched by the four layers), per-bank PIM's structural blindness, the M5 Max at 0.78 microjoules as the honest denominator; lane B's figures, labelled.

docs/design/class-v6-rotating-family.md: section 0's lead on the SRAM store, 0.1 the per-tier schedule table, layers 2 to 4 with lane A's priced schedule (5.5 / 8 / 11 GiB), lane D's three rings and the op-mix band (B = 4 on the injecting families, the lossy sum capped; 8 of 663 eras exhausting at the uncapped corner), the index fold as a layer-1 rule, the measured M5 Max size rows (-12 / -20 / -22 percent of rate at 2 / 4 / 8 GiB), the 5070 Ti stock pair, the x16 mixer rows with build-3's sibling-loaded method (11.4 ms, admissible false on the measurement), 7a lane B, 7b lane A, 7c lane C's layers 5 to 7, section 9 the served-line review for main's 20:00 word.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 11:32:09 +00:00
igneum-labs
77be72c118 Class v6: 7b the history beside the four layers (lane A's verdicts taken where they bind: layer 2 gains the per-year ceiling as its first constant, layer 4 the per-era null, the reserve order and the width warrant stated) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:27:47 +00:00
igneum-labs
d8b2e2ee68 Class v6: 7a the hardware future beside the four layers (lane B's k bands: HBM4, the custom base die, DRAM on logic, the N2 SRAM store at 17x; the three changes taken into layers 1 and 2 and the denominator), section 0's one line extended 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:26:35 +00:00
igneum-labs
95c3a37483 Merge class-v6-history 49d7ff46 into master (gate: green on 49d7ff46, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 10:26:13 +00:00
igneum-labs
983d766481 Merge class-v6-hardware ffc3a54b into master (gate: green on ffc3a54b, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 10:24:52 +00:00
igneum-labs
837576edc2 Class v6: lane D's two facts: the index fold as a layer-1 design row (7 of 16 drawn eras with a product bit on address bit R at abs z 130 to 511; the chip row 1.6 percent of reads at f = 1/2, zero at f = 1; the known-failed test 7 of 16 to 0 of 16 with the fold), the F8 tail bound in sigma not ratio, the bias test ordered after the fold 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:24:51 +00:00
igneum-labs
49d7ff462b Class v6 history lane, first cut: every ASIC-resistant proof of work and its chips by mechanism, the four-layer mapping with a number per chip class, and the three lessons that bind on v6 
docs/analysis/class-v6/history.md: 21 chip rows by mechanism (what each chip specialised, what the design missed, the timeline, the v6 layer, closed or not, the per-joule number); in-depth sections for Ethash (the E3's DDR3, Linzhi's 4.4 GB beside 64 compute units, the Jasminer X4's DRAM hybrid-bonded onto a 40/45 nm die, the E9), ProgPoW (the Least Authority and Rao audits read from the PDFs, Kik, Linzhi's claim, the adopters), RandomX (the X5's RISC-V board at 1.46x, the X9 announced December 2025 and withdrawn May 2026 with zero units, RandomX v2 released 25 March 2026 with activation pending, the Qubic episode as the detector's lesson), Cuckoo (the GRN1's 512 MiB SRAM die, the G32, the iPollo G1, the 2025 bounty), Equihash (the Z9's single die, the Fudan parameter-following design), Scrypt and Argon2 (the BM1485's on-die scratchpads, Percival's lookup gap, MTP), the no-chip hashes, kHeavyHash, CryptoNight, X16R, Lyra2REv2, the compute rows. The four layers against the history layer by layer, with the E3's death dates, Autolykos's growth rule, the design-cycle and FPGA-compile clocks, and the honest verdict that the stored-dataset chip (class C) is not closed by any layer: 5.1x per joule at zero premium, 2.1x with the shadow at k = 1. Two corrections to the 5 October file (the X9, RandomX v2) and one claim marked unverified (the 5x fork-surviving chip). First cut for 15:00 UK; the full report by 09:00 UK on 9 October.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:19:10 +00:00
igneum-labs
ffc3a54bdc Class v6 research lane B: the hardware future, five years out (first cut and the full report in one file) 
docs/analysis/class-v6/hardware-future.md: one table over PIM and PNM (HBM-PIM, AiM, LPDDR5X-PIM, UPMEM), HBM3E, HBM4 and the custom HBM4E base die, fine-grained DRAM on logic, LPDDR6, 3D DRAM, RLDRAM 3 and Folded Banks, FPGA with HBM2e, wafer-scale, CXL, optical I/O, chiplets and UCIe, and SRAM at N2: energy per dependent read, latency, cost per GB, availability to a non-hyperscaler, the k_read and shadow k bands, the edge per joule at zero shadow against the 5090 and the M5 Max, and the one layer of the four that blunts each with a number. The three findings: a 2 GiB SRAM full store on one N2 reticle is the strongest five-year chip (13x to 17x per joule, about USD 0.3 per MH/s) and no layer reaches it (layer 2 moves its capex, not its joules; the shadow at k = 0.5 holds 4.8x); per-bank PIM is blind (1.6 percent of reads in-bank at 2 GiB) and the custom HBM4E base die is the f = 1 chip with its controller in the stack (6.5x to 14x), untouched by layers 1 to 4; the denominator is the wrong card (the M5 Max at 0.78 microjoules halves to thirds every chip edge). Section 5 carries the k bands for the research lane's chip rows; section 7 the four decisions with defaults and deadlines; section 9 the sources with URLs and dates. tools/ci/export-exclude.txt: docs/analysis/class-v6 is research, not public export.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:17:50 +00:00
igneum-labs
0182c50dca Class v6: the x16 quiet-core re-run (9.04 to 9.10 ms loaded on a quiet host, 10.1 to 14.8 under load): x16 stays admissible false at genesis, decided by the 2019-class core as ladder rung 3 is 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:16:17 +00:00
igneum-labs
c22a541d12 Counter ASIC 3.0 status: the founder's load order on the four boxes and its placement (lane D's family sampling, the attack families at scale, lane C's packs, the pin matrix, the cross builds), the drift class settled by a fresh-walk node, the pin candidate e0644958 confirmed, the Windows installer class and the detach fix, the tiers' class-flip pair gated (081b3ba7), the rpc up, two reds on the release line from the first ten minutes of the load order (the missing 60x field; the detach's test literal) with their fixes and defaults 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:14:50 +00:00
igneum-labs
be1ff694ca Class v6: the x16 mixer verifier measured on build-1 (8.69 ms cold alone, 10.11 ms with the sibling loaded against x8's 4.67 and 5.41): x16 inadmissible on the loaded reference core, the mixer band {4, 8} 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:14:50 +00:00
igneum-labs
a07d693710 Class v6: the 5070 Ti tier measured (a rented pod, stock: class v3 78.69 MH/s at 140.8 W, class v4 78.78 at 224.0 W, the premium 83.2 W, 10.3 pJ per counted op), the per-tier chip edges at stock 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:12:47 +00:00
igneum-labs
0c548b60c7 Merge ship-docs-0321 2a4a828b into master (gate: green on 2a4a828b, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-08 10:12:42 +00:00
igneum-labs
e458519a34 Class v6: layers 2, 3 and 4 written with their chip rows and per-tier rows, the gate plan (the family analysed as a family) and section 7 (what a fully general chip still gets); layer 1's three open numbers await the hash lane's rows or their defaults at 16:00 UK 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:04:29 +00:00
igneum-labs
2a4a828be0 release record section 24: the first lock on cc902690 (checkpoint 1931, 10:06:32 BST), the move's count and the three puller faults closed, 0.3.24 Windows take 2 (Inno stopped the app and copied nothing; the /IGNOTA=1 rule), 0.3.25 opened (tip 87d8862d, the ceiling cut e0644958, digest 1b37cb9d, the DMG 501ba293 staged, the clock), the tiers at the class flip, the signed apps pipeline (Igneum Labs LLC) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:03:40 +00:00
igneum-labs
e62adc83cf Counter ASIC 3.0 status: the 0.3.25 pairs and app tip (87d8862d on the ceiling cut e0644958, its fast-time PASS at 10:54), the tiers' class-flip UI half (d949e274), the four builder lanes and the class v6 declaration with its four research lanes spawned and the outline on the mirror, the Arc re-read and v5lock jobs live, the held-push cause (the branch's own hook predating the per-process fix) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:01:24 +00:00
igneum-labs
2fc3377cd0 Class v6, the rotating family: the outline, section 0 per tier and the four layers' table with their chip rows' shape and the open numbers (the hash lane's three rows due 16:00 UK; the document complete by 18:00 UK) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:00:21 +00:00
igneum-labs
6443f921e9 Counter ASIC 3.0 status: the 0.3.25 pairs on 7bd2940f and the re-pointed app tip c68aea33 (every input green at 10:33 bar the pin's gates and the crossing), main's sweep finding (class v5 17 percent under v4 on a power-capped A4000; a knee-locked card may lose a few percent at the crossing until Ember re-tunes) and its two orders with their defaults 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 09:48:45 +00:00
igneum-labs
daba2e69d2 Counter ASIC 3.0 status: the 10:05 move's read-back (36 of 36 on the pin by 10:12, the first lock 10:06:32, carrying resumed; three fault classes named), the tiers gated (d3d0704a), the knob's tip e2962b89, the 0.3.25 app line assembled at 10:29 (e0d4425f), the node line's tip 7bd2940f with the one-shot gossip fix and the drift item reclassified 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 09:31:37 +00:00