Commit graph

571 commits

Author SHA1 Message Date
igneum-labs
8970afc600 counter-asic-2-node.md: the integration merges (readwidth 06dcb31, origin/master ae699a4) and how each conflict was kept
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 22:34:28 +00:00
igneum-labs
19b30e31f0 Merge remote-tracking branch 'origin/master' into ca2-v3
# Conflicts:
#	docs/bench-log.md
#	proto-opencl/host.c
2026-10-05 22:34:07 +00:00
igneum-labs
47ae818b2f Merge branch 'readwidth' into ca2-v3
# Conflicts:
#	docs/bench-log.md
#	docs/plans/read-width.md
#	igneum-pow/src/emit.rs
#	proto-metal/packbench.swift
2026-10-05 22:33:39 +00:00
igneum-labs
68af6db901 counter-asic-2-node.md: gate run 4, a real Metal miner across the v3 boundary (3 v3 prepares and prepared lines, swap with no pause, 124 blocks on v3, 0 re-check mismatches); class-v3.mjs judges the Metal checks from the first v3 prepare on
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 22:32:45 +00:00
igneum-labs
8e47f84d17 Metal worker: a class v3 day is built from the pack (memhard.metal: the mixer multiplier, the cache size, the era layout), datasets keyed by (day, class, era); class-v3.mjs --metal runs node 0's miner on the Metal worker (gate G4b) and --genesis-bits
The Swift DatasetContext is the version 2 item construction; a v3 program over it would hash another dataset than
the node's (every found refused by the CPU re-check). servePackDataset compiles the pack's memhard.metal and runs
igneum_cache_fill and igneum_build as packbench does, releases the cache, and the v3 job path takes the pack
program and the pack day of its class and era only (need + error otherwise). The gate script's --metal mode drives
igneum-miner --worker <igneum-bench> --prepare-packs <dir> --exit-on-seed-change (the app's shape) on node 0 and
reports the PREPARE and prepared lines, need / mismatch / refusal lines, accepted blocks after the switch, the
CPU re-check counter and the swap line.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 22:25:28 +00:00
igneum-labs
104be2dbcf counter-asic-2-node.md: gate G4 run 3 PASS on the final class (x8 with the era, d5070e7): 182 / 122 blocks, 0 rejected, 0 forks; suite job 4 green (G6)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 22:20:16 +00:00
igneum-labs
37dab3f5a5 counter-asic-2-node.md: the verifier before/after table (the mixer fix), class v3 = x8, the merges and checks on d5070e7
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 22:15:18 +00:00
igneum-labs
d5070e744d Merge branch 'ca2-mixer' into ca2-v3 2026-10-05 22:11:29 +00:00
igneum-labs
9597374c4d verifier regression of e08909f fixed (derive_items out of line, one instance per cache size with the line mask a constant: v2 0.609 ms per unit against readwidth's 0.607, was 1.33); x8 into class v3 under the delegated rule (V3_CLASS = MX8; mx8-genesis and mx8-devnet-epoch0 re-exported through the seam, the devnet one with the era inside; the mx4 packs kept as the x4 record, generator 2); tests/packs.rs and tests/mixer.rs on the x8 class; mixer-x4.md 6.2a, 6.4a, 6.5 decision, 6.6 the regression; chip-model-v3.md headline x8 (0.92x with the factor); bench-log addendum with the PC 1 build rows
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 22:10:55 +00:00
igneum-labs
c302a5738e counter-asic-2-node.md: suite job 3's result (kaspa-pow test rewritten for the era-in-class rule), the G6 reading corrected (the PC runs the feature-gated tests)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 22:08:44 +00:00
igneum-labs
2fe2626d94 tests/scratch.rs: the Instr literals carry the era fields win and off (0), left out by the merge of ca2-mixer onto the era tree
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 22:05:57 +00:00
igneum-labs
301ad547ba generator.rs: LoadClass::MX8 carries the era and hot fields (None) the merge of ca2-mixer 829687b onto the era and cache tree left out
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 22:05:31 +00:00
igneum-labs
f2d3dcaf3b Merge branch 'ca2-mixer' into ca2-v3 2026-10-05 22:05:05 +00:00
igneum-labs
92ab4582b3 counter-asic-2-node.md: the three PC 2 suite jobs (the flake, the kaspa-consensus rerun passed, job 3 pending)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 22:04:29 +00:00
igneum-labs
829687b1ab mixer x4: the measure session (v2 / x4 / x8 verifier 1.33 / 1.94 / 2.79 ms per unit on a loaded core, 1.45x and 2.1x; the 256 MiB fill 172 to 175 ms; the Metal 1 GiB build flat at 21 ms, latency-bound), the verification-throughput consequences (C19), what is unverified and what is owed; the bench-log entry; the PC 1 two-card playbook; the measured verifier row in the chip model
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 22:02:28 +00:00
igneum-labs
d2d5f5d6f2 mixer-x4.md: the x8 packs' Metal and Apple OpenCL rows, the daily-build table per tier (5090, 9070 XT, M5 Max, gfx1036 per prepare, a scaled 8 GB-class row) and the x4 / x8 rule; chip-model-v3.md: the mixer row alone as the headline (layer 5 measured, not adopted, with the 5090 and 9070 XT g beside the Mac's), x8 rows at year 0 and year 4
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 22:02:23 +00:00
igneum-labs
147db8db44 mixer x8 candidate beside x4 (coordinator's rule, 5 October 2026 21:30 UTC): LoadClass::MX8 ("mx8", same stream, keys (r m + j + 1) x 0x9E3779B9), the two candidate packs mx8-genesis and mx8-devnet-epoch0 (generator 2 with the class in the id; the vectors are re-cut through the seam after the x4/x8 choice), tests/mixer.rs fuzz takes IGNEUM_MIXER_CLASS, the PC playbooks carry the x8 packs and the gfx1036 fallback; mixer-x4.md: the Metal fuzz row
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 22:02:23 +00:00
igneum-labs
86ef4eab1e chip-model-v3.md: the hot table in the added form priced with the Mac's g (0.93 / 0.87 at 32 / 64 MiB, the 5090's g pending the PC rows): 1.98x and 2.12x at the equal integer budget, 1.60x and 1.67x with the SRAM deducted; the margin section says which convention keeps the claim
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 22:02:23 +00:00
igneum-labs
36ef07fda2 mixer x4: tests/mixer.rs (200-program v3 fuzz with the Metal pack writer, stats beside v2, dataset edges at every multiplier, determinism against the pinned pack); scratch.rs edge literal gains era_bytes; mixer-x4.md: the v3 vector tables, the v2 diff, the Metal and Apple OpenCL bit-exactness rows, the soundness table so far
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 22:02:23 +00:00
igneum-labs
a99fa6375f scratch soundness (layer 3 of Counter ASIC 2.0): verify.rs scratch trace hook; tests/scratch.rs: rewrite and fill bijections, written-word bias and re-hit rates per class, hand-built slot edge programs against a hand model, static scratch-mask check over every emitted kernel of every scr pack with six deliberate breaks, 200-program CPU fuzz and pack writer for the Metal runs; packbench --batch-base for the launch-level nonce wrap
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 22:02:23 +00:00
igneum-labs
e3b7ac869b counter-asic-2-node.md: the cache merge done and checked, the mixer fix owed (54bbfcc is not it; its merge conflicts in bench-log.md and packbench.swift only)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 21:59:18 +00:00
igneum-labs
ae699a4af2 release-0.3.10 plan: the merge to master, the console card's stale commit string, the site build on a conflicted journey.json
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 21:58:34 +00:00
igneum-labs
def920b1ed counter-asic-2-node.md: the CPU hash rate across the switch in run 2 (approximate) and the verifier slowdown the era agent measured, to be re-measured after the mixer fix
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 21:58:22 +00:00
igneum-labs
2a9dbd8176 Merge release-0.3.10: the certificate-driven reorg (C4), EVM transaction relay (protocol 14), the pack loader fix and the rebuilt workers, the six-section miner, GPU hot-plug, elevated-job exit codes, the PC-built Windows node (static libstdc++), node 21d4c73c; shipped 5 October 2026 21:32Z
# Conflicts:
#	site/index.html
#	site/journey.json
2026-10-05 21:58:04 +00:00
igneum-labs
39ecd7c52b hot table (Counter ASIC 2.0 layer 5), measured and not adopted, on the ca2-v3 composed class (squash of tag ca2-cache-history-2026-10-05)
LoadClass::hot (Option<HotClass { mb, k, added }>) beside mix, slots, scratch, mixer_mult, growth and era; V3_CLASS = { era: None, hot: None, ..LoadClass::MX4 } (hot stays None: the hot code is behind the flag, measured and not adopted). Op::Hot, the hot slots drawn after the scratch slots, no width roll (v2_loads allows the added form's extra slots), the id suffix hot/<S><k>[added], the hot parsing inside parse_loads, the era branch first in name(). HotTable under seed_words("igneum-hot/" || epoch seed) with the cache chain and tag umHT, read at H[mulhi(src, HOT_WORDS)]; DatasetSource::hot attached by new_class_day and from_seed_bytes_class; the acceptance stand-in dataset_elem(idx, S[2], S[3]); the three emitters (hot argument after the init words, ht_segment and igneum_hot_fill beside the layout-aware cores); packfile.h hot fields beside class, era, attempt and mixerMult; OpenCL host, Metal packbench and NVRTC worker fill H on the device and self-test it. Eight packs under proto-cuda/packs-ca2-hot (replaced hot32k4 hot64k4 hot96k4 hot64k2 hot64k8, added hot32k4a hot64k4a hot96k4a) re-exported on the merged crate: vectors unchanged, program.h and program.json carry the mixer fields. docs/plans/hot-table.md (design, spec text, per-tier budget, chip model, Mac and PC measurements, the decision: layer 5 out of v3, the 3.0 note); bench-log entry and addenda with job ids and worker sha256s; the two PC playbooks.

Checks on this commit: cargo test --release 53 + 19 pass (the pinned v2, mx4, era, readwidth and hot packs); the pinned packs under proto-cuda/packs, packs-ca2-mixer, packs-ca2-era and packs-readwidth untouched; Metal packbench and Apple OpenCL --bench-pack on all eight hot packs (run lock, 2^20 at base 0): 96/96 lanes, hot table head, last line and FNV PASS, one fingerprint per pack on both harnesses, equal to the fingerprints before the rebase (hot32k4 679e5e83378d3790, hot64k4 d4c9e456b039fdef, hot96k4 7c98eceffee9fd73, hot64k2 f43b10a95879b8e5, hot64k8 c11309d743be9392, hot32k4a afb700b2d997c847, hot64k4a ba214baa9c1a9e85, hot96k4a 29e1916aed6deff5). No era or mixer behaviour changed: every resolution kept the ca2-v3 side and appended the hot branch.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 21:57:39 +00:00
igneum-labs
26ebf9cf29 release-0.3.10 plan: the ship (run 37374158235 after six dispatches through GitHub's outage, the fallback rehearsed on PC 1 and stood down), the rollout with per-machine times, the hand nodes and the seed, the digest sweep, the mixed fleet, the next cut and the open items
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 21:57:21 +00:00
igneum-labs
495c55280c counter-asic-2-node.md: gate G4 run 2 PASS on the composed class (era in the class on the mixer, 1558971): 181 / 124 blocks, 0 rejected, 0 forks; the PC 2 suite job id; the cache merge owed
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 21:53:37 +00:00
igneum-labs
1558971521 era layout (Counter ASIC 2.0 layers 4 and 8) behind the class flag, on the ca2-v3 seam: the 7-draw era stream from E_n (stride, interleave, width pinned at 4 B), per-site window draws (dataset, half, quarter at a 256 MiB floor), the strided windowed load address in the interpreter, the acceptance mirror and the three emitters, the interleaved dataset layout riding with the program (memhard::Layout, mh_t/mh_j/mh_addr, Epoch::dataset_word), V3_CLASS with the era drawn inside by generate_from_seed_bytes_program_class, --era / --era-widths on the CLI, six class v3 era packs (packs-ca2-era), tests, the design doc, host.cu/host.c deriving host words through the pack's mh_word, emu/test-layout.sh, the PC 1 playbook
Squashed from six commits (tag ca2-era-pre-squash) for one merge.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 21:41:33 +00:00
igneum-labs
b3d15a7304 counter-asic-2-node.md: the two owed items (gate run 2 on the composed class, per-day dataset reuse in the CUDA and OpenCL workers)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 21:39:11 +00:00
igneum-labs
08db83b2eb counter-asic-2-node.md: gate G4 run 1 PASS on the mixer-x4 class (181 / 124 blocks across the boundary, 0 rejected, 0 forks, 3 switch lines, v2 and v3 program ids), the summary JSON
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 21:38:37 +00:00
igneum-labs
9b5451f66a class-v3.mjs: node 2 connects to node 0 only (--connect takes one address); a thrown start stops the nodes
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 21:33:00 +00:00
igneum-labs
54132959be Merge origin/master (the explorer pages, the public API check, the CLAUDE.md note) into release-0.3.10; docs, site, observer and ci.yml only 2026-10-05 21:32:17 +00:00
igneum-labs
144fe8ba1e fast-time: the override file is merged as text, never through JSON.parse (a never height, 18446744073709551615, becomes 1.8446744073709552e+19 and the node refuses the file; first gate run 5 October 2026 21:30Z); class-v3.mjs and simnet.mjs
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 21:32:09 +00:00
igneum-labs
7053d206a1 counter-asic-2-node.md: the (program id, era seed) identity, the measured digest flip, the Mac suite results
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 21:25:09 +00:00
igneum-labs
36c5f13a5f fast-time: the proving v1 fields and pow_genesis_dataset_log2 in both override files (the fork's every-field test), README rows; class-v3.mjs reports the build time per epoch; docs/plans/counter-asic-2-node.md (the node side of Counter ASIC 2.0, gate result pending)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 21:04:39 +00:00
igneum-labs
f74a087443 mixer x4: the two pinned class v3 packs (proto-cuda/packs-ca2-mixer/mx4-genesis and mx4-devnet-epoch0, generator 3 on V3_CLASS = mx4, the devnet pack with era 0's stand-in), tests/packs.rs runs every pinned check over them plus v3_packs_are_the_v2_seeds_under_mixer_x4; igneum-pow --program-class v2|v3 and --era-hex through one epoch_of helper (export, bench, hash, hash-bound); fresh exports of igneum-genesis-mh and igneum-devnet-v4-epoch0 diff clean against the checked-in packs
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 21:03:27 +00:00
igneum-labs
e08909f138 mixer x4 and the cache growth rule (Counter ASIC 2.0, class v3 construction): LoadClass mixer_mult and growth, LoadClass::MX4 (v2 loads, no width roll), memhard::Shape in MixParams, m mixer applications per round with keys round_key(r m + j), Cache::fill_log2, the option C schedule (growth_doublings, cache_log2_words, dataset_log2_words, days_since_genesis) with its test table, day-sized Epoch entries, the three emitters (m loop only for m > 1, v2 text unchanged), program.h and program.json fields, packfile.h mixerMult, packbench and OpenCL host prints, --class mx4 and --days on the CLI; docs/plans/mixer-x4.md design and spec text, docs/analysis/chip-model-v3.md, the 5090 and 9070 XT dataset-build playbooks (measurements and vectors to follow)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 20:54:10 +00:00
igneum-labs
28635b165f Metal worker compiles a class v3 program from the pack a prepare line names; igneum-pow chain_dataset_day seam; pow_genesis_dataset_log2 in the override files
main.swift: servePackProgram reads program.h with the packfile.h checks (generator 2 or 3, the class line against
the generator, the seed bytes, IGNEUM_SEEDW_INIT against attempt_words, class and era against the line) and
compiles program_bound.metal; the program store keys on (seed, class, era); a v3 job with no resident v3 pack
program answers need + error; v2 lines unchanged (Swift generation, the variant race); a pack program never races.
verify.rs: Epoch::chain_dataset_day(day, class, days_since_genesis, genesis_dataset_log2) and days_since_genesis,
the entry the node builds every day cache through (the ca2-mixer growth rule fills the body).

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 20:51:24 +00:00
igneum-labs
06dcb310fb read-width: per-watt and per-pound rows (telemetry watts, list prices approximate) and the AMD consequence (C11); packbench prints Metal's currentAllocatedSize and recommendedMaxWorkingSetSize (C12)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 20:49:45 +00:00
igneum-labs
574cccd456 fast-time: program_class_v3_activation_daa in both override files (never), the README row, and class-v3.mjs, the rollout gate G4 script
class-v3.mjs: a 3-node private network (ports 29600 and up, igneum-devnet-960) on override-60x.json merged with
a CPU genesis difficulty (0x1f010000) and the class switch a few epochs ahead (default 150: inside epoch 2 at
60 DAA per epoch, so the switch rounds up to epoch 3 at DAA 180); one real CPU miner per node; reports blocks on
each side of the boundary, the class and program id of every epoch, rejected blocks (miners and nodes), the
sinks and block counts of every node, and every node's switch line; exit 0 when every check passes.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 20:40:30 +00:00
igneum-labs
17641afbe1 Workers: the program class and era on the serve protocol; a pack of the wrong class or era is refused (Counter ASIC 2.0)
packfile.h: pf_load refuses a generator other than 2 or 3 (spec 01 section 1.4.5), reads IGNEUM_PROGRAM_CLASS
(must match the generator) and IGNEUM_ERA_SEED_HEX; pf_pack_class_ok and pf_class_token are the one rule for
the `class=<v2|v3> era=<hex>` tokens a job or prepare line of a class v3 epoch ends with (a v2 line is the
line of before, byte for byte). CUDA worker.cpp and OpenCL host.c: a pair's identity includes its class and era
when the line names them, so a prepared pack of the right class wins over the resident pack of the same seeds;
right seeds with the wrong class answer `need` plus `error <id> pack <dir>: program class mismatch ...`, and a
prepare on a pack of the wrong class fails in plain words. Metal main.swift: refuses every class v3 line until
the Swift generator carries version 3 (the integration branch). emu/packfile-test.c: the generator rule, a v3
pack with its era, the token matcher, the contradicting class line (13 checks pass).
igneum-pow verify.rs: Epoch::chain_dataset(day, class), the one entry the node's day cache goes through, so the
ca2-mixer class-specific item construction and cache schedule have a seam.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 20:33:59 +00:00
igneum-labs
176b6f4e40 igneum-pow: the program class seam for Counter ASIC 2.0 (ProgramClass V2/V3, V3_CLASS placeholder, Epoch::from_chain_seeds, class and era in packs)
ProgramClass { V2, V3 }: V2 is the lottery hash exactly; V3 is generator version 3 on V3_CLASS, a PLACEHOLDER
set to w16 (LoadClass::fixed(4, 16)) that the integration agent replaces with the decided class. A v3 program's
id is program_id(3, seed, attempt) (spec 01 section 1.4.6). Epoch::from_chain_seeds(epoch, day, era, class,
label) and Epoch::chain_program build what the node's engine and the miner's export use; a v3 program records
the era seed bytes (Program::era_bytes). program.h and program.json of a v3 pack carry IGNEUM_PROGRAM_CLASS and
IGNEUM_ERA_SEED_HEX beside IGNEUM_GENERATOR 3; a v2 pack is unchanged (tests/packs.rs diffs the pinned packs).
packcheck: verify_pack_texts_chain / verify_pack_dir_chain refuse a pack of the wrong class, the wrong era, or
a generator other than 2 or 3 (PackFault::WrongClass); PackIdentity carries generator, class and era.

Tests: program_classes (generator.rs), program_class_and_era_are_checked (packcheck.rs); 42 + 11 pass.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 20:25:06 +00:00
igneum-labs
2d04a1c553 read-width: bench-log entry and docs/plans/read-width.md (three cards, probes, widths, the per-load mix, the scratch at 32 and 128 KiB, chip model, recommendation: keep v2; w16 the only width that passes the rules and closes nothing); test multiply made wrapping (dev-profile overflow check)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 20:24:40 +00:00
igneum-labs
357ccb9507 read-width: OpenCL scratch kernels declare the __local exchange buffer before the unit loop (AMD's compiler requires the outermost scope; round 3 on the 9070 XT); seven scratch packs re-exported, vectors unchanged
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 20:18:35 +00:00
igneum-labs
78b438bf59 CLAUDE.md: every number carries its consequences for each user tier (standing rule)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 20:18:34 +00:00
igneum-labs
d28a32e403 Merge commit '4163143' into ca2-v3
# Conflicts:
#	proto-cuda/nvrtc/packfile.h
2026-10-05 20:17:46 +00:00
igneum-labs
a094972548 read-width: packfile accepts a string-seed pack (any even-length hex epoch seed; the seed-word re-derivation still checks it); bench-only playbooks for the second PC round
Round 1 (run-readwidth-{5090,9070}-20261005) delivered the probes and refused every pack: pf_load demanded the chain's 32-byte epoch seed and the experiment packs carry igneum-pow --seed strings.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 20:09:58 +00:00
igneum-labs
8c898d3f60 read-width: CUDA worker --bench and --memprobe, scratch arena from the occupancy capacity; PC playbooks (card under test off in the app, restored after); harness arena label
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 20:05:57 +00:00
igneum-labs
22dc44141d read-width: scratch per warp is a class parameter (32 or 128 KiB, under the 6 GB working-set cap), distinct-address rule bounds dataset loads only; Metal pack harness; OpenCL --bench-pack, scratch args and 16-byte probe; packfile class fields; OpenCL emulator persistent launch
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 19:58:20 +00:00
igneum-labs
dc84789e34 read-width experiment (gate 1): load classes W=4/16/64, per-load width mix, scratch RMW variant behind a generator flag; 20 packs; CPU verifier and acceptance mirror; emulator shims
Nothing changes for the default class: the pinned packs are byte-identical (tests/packs.rs), the v2 draw stream is untouched.
LoadClass {mix, load_slots, scratch}: fixed widths w16, w64, w64x4 (4 loads of 64 B), era mixes 50/35/15 and 25/50/25 drawn per load with one extra below(100) roll, and the scratch variant scr0/2/4/8 (persistent warps, 1 MiB per warp, tagged lazy fill, measurement only). A wide load reads the W-aligned address and folds every word: x = dst ^ w0; x = (rotl(x, 11) * 0x9e3779b1) ^ w[j]. Program ids carry the class. proto-opencl/host.c taken from opencl-rdna4 23810df (--memprobe, select read-back).

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 19:46:54 +00:00