igneum-labs
81113bb2df
V6-07: the host bisect names 7dd7c35e1 (FixtureEnv field without the guest re-pin) as the 0-bytes fault; amendments
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 21:49:15 +00:00
igneum-labs
a556c3ad53
V6-07: the aggregate and chain floors at 8,500 MiB from the measured aggregation peak; the rows and their consequences
...
docs/analysis/floor-memory-profile-2026-10-08.md: the 3060 and 4060 rows on the default, unoverridden job path (the served 0317 host on the V6-07 server: 3060 shard 11.4 s at 7,601 MiB, the whole chain 27.4 s at an 8,306 MiB aggregation peak, both VERIFIED; 4060 shard 16.3 s at 7,504 MiB VERIFIED, the chain aborts at the aggregation's 486 MiB allocation on 176 MiB free), the host's profile and refusal rows (exit 78 under the floor and beside the miner on both cards, the miner unharmed), the recursion constant isolated (no change of the device peak), the known-failed first server, the master-host 0-bytes fault with its NOT RUN rows, and the consequences per card tier. memory_profile.rs: aggregate and chain floors 8,500 MiB (an 8 GB card proves shards and is refused the chain before setup), tests re-pinned; suite 7 passed on box 3.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 21:20:21 +00:00
igneum-labs
0d208582a5
V6-07: the host's row from the lesser of the engine's grant and its free reading; prover-floor.md names the free-memory rule
...
The window lane's engine half (reviewb-202 af5ade43
2026-10-08 19:54:26 +00:00
igneum-labs
c853fca1b5
Merge amd-intel-energy-docs c76d9f91 into master (gate: green on c76d9f91, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 19:29:11 +00:00
igneum-labs
c76d9f9180
AMD and Intel energy on class v6 (GPU-03 AMD and Intel cells, ECO-05 named cause): per 32 bits of bus the AMD and Intel cards burn the 5090s watts but do 0.21x to 0.47x its random reads; the window costs the RX 7600 and the Arc B580 no rate per unit of work; the B580 class v6 rows (11.01 MH/s, fingerprints equal, watts unreadable unelevated); hash-identical kernel candidates ranked (0 to about 10 percent); the RX 7600 metered knee owed to a queued PC 1 job
...
Documents only: docs/analysis/class-v6/amd-intel-energy.md and docs/analysis/class-v6/amd-intel-energy/ (the three job scripts, the Level Zero sampler source, the offline-compile prelude and ISA summary).
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Documents-only replay of d9e91c5d7d9e91c5d7a
2026-10-08 19:21:27 +00:00
igneum-labs
2e6914f8c9
The proving outcome ledger (review B F08): every claimed job ends in one outcome; the report reads paid completions, missed deadlines and wasted work by cause
...
tools/fleet/box-prover.py point 6: each claimed segment is an eligible job and closes once as paid, expired (unpaid, held_expired) or cancelled (disk, export, cut, chain, timeout, shards, statement, sign, refused), active until then; the row carries outcome, cause, deadline, margin at the claim, seconds spent (wasted unless paid) and the deadline miss; the state carries the counters and the wasted seconds by cause; every close is a RESULT outcome line, the run ends with a RESULT ledger line.
tools/fleet/prover-outcomes.py: the report over state files and logs (a log from before the ledger is reconstructed from its RESULT lines; a state row wins over a log row): outcomes, paid completions (segments, shards, IGN, median end to end, median time to pay, median margin), missed deadlines by cause with the median miss (never negative, none on a stale tip), wasted work by cause, throughput per hour and the paid share of the seconds spent, the open jobs. --self-test to known numbers (known-failed first), run by the gate. tools/fleet/night.py sums the fleet's counters into its hourly row. docs/analysis/proving-outcome-ledger.md: the definitions and how to read the three ratios.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:19:39 +00:00
igneum-labs
fe612e5f12
Review B (8 Oct 2026): second external review, findings, reproduction pack, dispatch
...
Documents only. Fourteen findings F01 to F14 with forty-four regressions,
dispatched by lane in dispatch.md; the regressions become suite REV in the
acceptance registry (CI steward).
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:49:43 +00:00
igneum-labs
c1bddb273d
test registry: the hash lane's batch 1 (tools/ci/batches/hash-lane-20261008-batch1.json: bench:pc1-packs, bench:pc1-amd, bench:fleet-pods, census:class-v6, suite:pow as RUNNING with their evidence rows under docs/analysis/class-v6/rows)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:33:08 +00:00
igneum-labs
20b0636f95
Class v6 census: the per-site address census (the review's A03): the known-failed v2 case reproduced at 15.15 percent; class v5 and the v6 candidate uniform to 2.7e-7 at the worst address on the live dataset; the cache shares the era windows' by design (the adversary's 72 percent = the Devnet 3 window draw)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of b10fe1351 (b10fe1351dea53344acfa5b764d8215dc77480f3) for the box mirror master
2026-10-08 18:11:09 +00:00
igneum-labs
1f6b90fa2f
Merge binding-review 781538f1 into master (gate: green on 781538f1, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge)
2026-10-08 18:03:43 +00:00
igneum-labs
acbbe44d99
Merge class-v6-family-gate 43adcf75 into master (gate: green on 43adcf75, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 18:01:23 +00:00
igneum-labs
781538f138
docs/analysis: binding review section 5a, the external review's A05 (FNV initialisation, the 64-bit fold): the argument, five measured lines, no change for 2.0, the class-version shape if one is wanted
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:55:49 +00:00
igneum-labs
43adcf75c5
Class v6 family gate, 6.10: the hash lane's layer-8-off draw through the acceptance on class-v6 542cd7028 against the same-crate windowed control (PASS: r 0.18 against 0.27 at width 4, the (c''') cost 2 against 13 percent, 0 hot sets and 0 over 1.2x at 2^20, the bit-R share up with the windows gone, the fold the lever); the harness port diff at 542cd7028
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:54:46 +00:00
igneum-labs
2da6fe9d59
docs/analysis/review-2026-10-08: the external algorithm review's evidence pack (evidence.md, results.json, harness.zip), 8 October 2026
...
The three files as they stand in the Mac checkout at 18:51 BST, on the coordinator's word, one documents-only commit:
evidence.md (45 KB), results.json (82 KB, parses; the delivered results), harness.zip (43 KB: a C and Python reproduction
harness, twelve files, data beside the evidence and not repository code). No chain path; the pack names no founder and no box.
2026-10-08 17:52:21 +00:00
igneum-labs
a67ad71284
Publish the 2.0 evidence set on the public mirror (main's word): coexistence-model.md, operator-simulation.md, connected-state.md, coexist-rows.md and the class v6 design record leave the export-exclude list, the lane records and logs stay excluded; the zone word redacted in connected-state.md; the mirror-follows-master note beside every evidence column
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:29:00 +00:00
igneum-labs
94d5b9eaf9
Merge class-v6-family-gate 08010e76 into master (gate: green on 08010e76, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 17:26:17 +00:00
igneum-labs
08010e76a4
Class v6 family gate, 6.9 closed: the best-mix table's exact or = 0 attempts rows at both widths on build-4 (r 0.29 and 0.16, 0 exhausted, the floors at the width's cost), the owed line closed; the harness ported onto class-v6 a7c2c082f for the layer-8-off acceptance
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:20:45 +00:00
igneum-labs
9954e451e3
Merge binding-review c2459ae0 into master (gate: green on c2459ae0, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge)
2026-10-08 17:19:14 +00:00
igneum-labs
96c086371f
Merge class-v6-connected-docs-2 1c33395a into master (gate: green on 1c33395a, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 17:15:34 +00:00
igneum-labs
c2459ae08f
docs/analysis: binding review of template, nonce, work and result (Igneum 2.0 register row): the chain of bindings from the code, the twelve reuse paths with their cost and rule, the measured lines, five open questions (epoch-seed VDF not in the node line, the day keyed on the timestamp)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:11:56 +00:00
igneum-labs
a74395f238
Class v6 census, lane 2: the six-pack sheet (fold, rw, foldrw, win, all PASS; rw2 FAIL on F8), the harness, the commands, the instrument's definition, the faults fixed, every pack's harness outputs under logs/census-packs
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 25098c1a2 (25098c1a276d80987262eda59a7f1beef8cd6ba4) for the box mirror master
2026-10-08 17:08:39 +00:00
igneum-labs
33af70442e
Merge class-v6-family-gate 8ce0956b into master (gate: green on 8ce0956b, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 17:01:32 +00:00
igneum-labs
1c33395a75
Connected state: the PC 1 lock row (the window +1.6 percent of energy per hash at the 1,300 lock, +5.9 unlocked; the score re-read at x 1.016: 1.08x node-for-node, 1.07x a node ahead; the verdict unchanged)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 042f5ba98042f5ba98a
2026-10-08 16:57:26 +00:00
igneum-labs
8ce0956b48
Class v6 family gate, amendment 6.9: the best-mix genesis table's acceptance for D1 (PASS: r 0.33 and 0.19 at widths 4 and 1, 0 exhausted, the floors at the width's cost, attack-f8 at the exact table 0 hot sets and 0 over 1.2x at 2^20; the exact or = 0 attempts rows owed with build-3 unreachable); the Igneum 2.0 pause recorded
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 16:54:11 +00:00
igneum-labs
04bda082fd
Merge counter-asic-4-docs-2 3d3ad22e into master (gate: green on 3d3ad22e, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 16:33:46 +00:00
igneum-labs
3d3ad22e89
Merge box/master ea27fdcd into counter-asic-4-docs-2 (the export list: both additions kept, operator-simulation.md and the pre-2.0 ledger copy)
2026-10-08 16:27:51 +00:00
igneum-labs
c3b05215a5
Merge class-v6-adversary-docs-2 0db43b65 into master (gate: green on 0db43b65, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 16:27:23 +00:00
igneum-labs
5087e14b8c
Merge box/master 33ffe78c into counter-asic-4-docs-2 (the export list: both additions kept, operator-simulation.md and the proving-pipeline record)
2026-10-08 16:14:15 +00:00
igneum-labs
0db43b6578
multi-family adversary: clock stamps read from the Mac
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 10b901a46 (10b901a46934c24ce9b44c74bc6fd4db7c40d2b0) for the box mirror master
2026-10-08 16:10:22 +00:00
igneum-labs
23f3073676
multi-family adversary: the placed full-core rows, the board and D2(b) at the placed energy, the transition matrix, the one page
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 7e715b50b (10b901a46934c24ce9b44c74bc6fd4db7c40d2b0) for the box mirror master
2026-10-08 16:10:21 +00:00
igneum-labs
6b6c5e783e
multi-family adversary: the placed board figures corrected to the model's output
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 2b30cfd0b (10b901a46934c24ce9b44c74bc6fd4db7c40d2b0) for the box mirror master
2026-10-08 16:10:21 +00:00
igneum-labs
a0abb94cdc
multi-family adversary: the placed genesis core rows, the 32-lane genesis row, the board at the placed energy, the D2(b) harness and its rows
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 90001aae6 (10b901a46934c24ce9b44c74bc6fd4db7c40d2b0) for the box mirror master; left on the branch: tools/chip-model/mf/flow/d2b.py tools/chip-model/mf/results/board-placed-base-n5.md tools/chip-model/mf/results/board-placed-full-n3.md tools/chip-model/mf/results/board-placed-full-n5.md tools/chip-model/mf/results/d2b-n3.md tools/chip-model/mf/results/d2b-n5.md tools/chip-model/mf/results/out/mf32base/logs/asap7/mf32base/base/1_synth.json tools/chip-model/mf/results/out/mf32base/logs/asap7/mf32base/base/1_synth.log tools/chip-model/mf/results/out/mf32base/logs/asap7/mf32base/base/power_synth.log tools/chip-model/mf/results/out/mf32base/reports/asap7/mf32base/base/synth_stat.txt tools/chip-model/mf/results/out/mf32base/results/asap7/mf32base/base/mem.json tools/chip-model/mf/results/out/mf8base/logs/asap7/mf8base/base/1_synth.log tools/chip-model/mf/results/out/mf8base/logs/asap7/mf8base/base/6_report.log tools/chip-model/mf/results/out/mf8base/logs/asap7/mf8base/base/power.log tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/2_floorplan_final.rpt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/3_detailed_place.rpt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/3_global_place.rpt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/3_resizer.rpt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/4_cts_final.rpt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/5_global_route.rpt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/5_route_drc.rpt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/5_route_drc.rpt-5.rpt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/VDD.rpt tools/chip-model/mf/results/out/mf8full/logs/asap7/mf8full/base/1_synth.log tools/chip-model/mf/results/out/mf8full/logs/asap7/mf8full/base/6_report.log tools/chip-model/mf/results/out/mf8full/logs/asap7/mf8full/base/power.log tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/2_floorplan_final.rpt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/3_detailed_place.rpt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/3_global_place.rpt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/3_resizer.rpt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/4_cts_final.rpt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/5_global_route.rpt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/5_route_drc.rpt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/5_route_drc.rpt-5.rpt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/VDD.rpt tools/chip-model/mf/results/sim/mf32base/gl2sim.log tools/chip-model/mf/results/sim/mf32base/sim_mix_s2000.log tools/chip-model/mf/results/sim/mf32base/sim_mix_s500.log tools/chip-model/mf/results/sim/mf8base/gl2sim.log tools/chip-model/mf/results/sim/mf8full/gl2sim.log tools/chip-model/mf/results/table.csv tools/chip-model/mf/results/table.md
2026-10-08 16:10:21 +00:00
igneum-labs
12ba299bd0
Class v6 mixed FP32: section 6.1, the k lane's synthesised FP32 rows (FMA lane 3.4 pJ at N3, k 0.65 on the unit, 0.15 blended at the lock); the score 3.2x / 3.5x; the verdict stands
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of e6d52e198 (e6d52e19845cdffe5bb24f26e6eeda400f1ef4a8) for the box mirror master
2026-10-08 16:07:14 +00:00
igneum-labs
befc1121cd
Class v6 mixed FP32: the final rows (fp24 CPU 2^24 equal on three cards, the quiet-core verifier, the 4090's fp24 and v5-genesis rows), every pod record
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 255be0264 (e6d52e19845cdffe5bb24f26e6eeda400f1ef4a8) for the box mirror master
2026-10-08 16:07:14 +00:00
igneum-labs
beaf234e29
Class v6 mixed FP32: the rows (census on build-4, the stock 5090, the 4090 and the capped 5090, the CPU-vs-CUDA fingerprints), the chip-side reading, KILL on the GPU budget and the full-board score; the pod scripts and the records
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of a324c941e (e6d52e19845cdffe5bb24f26e6eeda400f1ef4a8) for the box mirror master; left on the branch: tools/attack/v6-census/pod-bench.sh tools/attack/v6-census/pod-census.sh tools/attack/v6-census/sampler-summ.py
2026-10-08 16:07:13 +00:00
igneum-labs
2a7d8f9a34
Class v6 mixed resource: the FP32 candidate behind IGNEUM_FG_FP32 (fadd, fmul, ffma, fcvt in the shadow draw, xor-injected, the fp_in operand rule), the determinism rules in the emitter for CUDA, OpenCL and Metal, the CPU reference, the fingerprint subcommand, the report skeleton
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of c19e19b91 (e6d52e19845cdffe5bb24f26e6eeda400f1ef4a8) for the box mirror master; left on the branch: igneum-pow/src/accept.rs igneum-pow/src/emit.rs igneum-pow/src/generator.rs igneum-pow/src/main.rs igneum-pow/src/verify.rs igneum-pow/tests/mixer.rs
2026-10-08 16:07:12 +00:00
igneum-labs
143c514786
Igneum 2.0 D4: the placed energies (the complete GDDR7 machine 1.6x node-for-node, 1.9x a node ahead; the hybrid 2.4x / 2.9x; the die 2.4x / 3.3x; per-dollar unchanged) and the three chips scored at them, no verdict changed; the served energy sentence on them; the proving-payment pin in the code behind its constant, the guest's mirror owed
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only copy of counter-asic-4 df7c85c1c (its delta over master 919293896
2026-10-08 16:05:40 +00:00
igneum-labs
714cf36138
docs: Devnet 3 proving pipeline end to end, 8 October 2026 (the fleet lane's document, landed by the research-landing hand on the coordinator's word)
...
The document as it stood in the fleet lane's worktree at 16:46:43 BST (the same second as gpu-fleet 9991d7ce, which carried
tools/fleet/pipeline-collect.py and left this file untracked). Documents only; the collector stays on gpu-fleet.
2026-10-08 15:51:26 +00:00
igneum-labs
9915082b41
docs: class v6 coexistence rows on an RTX 3060 12 GB and an RTX 4060 8 GB (5.5 GiB miner beside the compressed shard prover, verbatim run-log rows, the reconciliation with the 6 October 8.9 GB row and the 16 GB rule)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:48:20 +00:00
igneum-labs
d846bfe5d8
Merge class-v6-connected-docs e6146368 into master (gate: green on e6146368, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 15:43:21 +00:00
igneum-labs
5405dd9f20
Merge counter-asic-4 03029526 into master (gate: green on 03029526, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 15:37:40 +00:00
igneum-labs
e6146368b5
Connected state: the chip rows (the k lane's re-optimised core: 4.4 pJ per lane-op at N5, k 0.71 at the lock), the score (3.3x node-for-node, 3.6x a node ahead; the window moves the chip's edge 1.10x against a 1.25x gate), verdict KILL as a class, what is kept and what v7 tests
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 6ccd2a6fe (6ccd2a6fe) for the box mirror master
2026-10-08 15:28:39 +00:00
igneum-labs
0647e8976c
Connected state: every GPU row at stock (5090 and 4090, harness and kit worker), the census TSVs and bench logs under logs/connected; the chip row, the score and the lock row still open
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of aa6f60af8 (6ccd2a6fe) for the box mirror master
2026-10-08 15:28:39 +00:00
igneum-labs
e9e88cf4f2
Connected state: the header-bound kernel in the pack (the NVRTC worker loads it: check PASS on a 5090), docs/analysis/class-v6/connected-state.md with the structure, the liveness rows, the census rows and the first GPU rows (the 4090, worker, lock and chip rows to follow)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of ecf98c0dd (6ccd2a6fe) for the box mirror master; left on the branch: igneum-pow/src/connected.rs igneum-pow/src/main.rs
2026-10-08 15:28:38 +00:00
igneum-labs
d1d2946038
multi-family adversary: the routed clock relaxation, the tier table, the statement, the data-local cost model and the dataset comparison
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 2db208912 (2db208912e5fc0656930aaabd7db74ec2a68ca8e) for the box mirror master; left on the branch: tools/chip-model/mf/Makefile tools/chip-model/mf/flow/collect.py tools/chip-model/mf/flow/mf32base.mk tools/chip-model/mf/flow/mf32base.sdc tools/chip-model/mf/flow/mf32full.mk tools/chip-model/mf/flow/mf32full.sdc tools/chip-model/mf/flow/mf8base.mk tools/chip-model/mf/flow/mf8base.sdc tools/chip-model/mf/flow/mf8full.mk tools/chip-model/mf/flow/mf8full.sdc tools/chip-model/mf/tb/tb_mf_common.vh
2026-10-08 15:28:35 +00:00
igneum-labs
30ba24bea1
multi-family adversary: the mf core RTL (SRAM window and imem, every bank entry, operand isolation, 5-phase slot), the flow, the collector, the board and hash models, the first rows (synthesis only, 8 lanes, full and base)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of a807edd84 (2db208912e5fc0656930aaabd7db74ec2a68ca8e) for the box mirror master; left on the branch: tools/chip-model/mf/Makefile tools/chip-model/mf/flow/board.py tools/chip-model/mf/flow/collect.py tools/chip-model/mf/flow/gl2sim.sh tools/chip-model/mf/flow/hash.py tools/chip-model/mf/flow/mf32base.mk tools/chip-model/mf/flow/mf32base.sdc tools/chip-model/mf/flow/mf32full.mk tools/chip-model/mf/flow/mf32full.sdc tools/chip-model/mf/flow/mf8base.mk tools/chip-model/mf/flow/mf8base.sdc tools/chip-model/mf/flow/mf8full.mk tools/chip-model/mf/flow/mf8full.sdc tools/chip-model/mf/flow/power.tcl tools/chip-model/mf/flow/sim.sh tools/chip-model/mf/results/board-mf8full-n3.md tools/chip-model/mf/results/board-mf8full-n5.md tools/chip-model/mf/results/hash-mf8base.md tools/chip-model/mf/results/hash-mf8full.md tools/chip-model/mf/results/out/mf8base/logs/asap7/mf8base/base/1_synth.json tools/chip-model/mf/results/out/mf8base/logs/asap7/mf8base/base/1_synth.log tools/chip-model/mf/results/out/mf8base/logs/asap7/mf8base/base/power_synth.log tools/chip-model/mf/results/out/mf8base/objects/asap7/mf8base/base/copyright.txt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/synth_check.txt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/synth_stat.txt tools/chip-model/mf/results/out/mf8base/results/asap7/mf8base/base/mem.json tools/chip-model/mf/results/out/mf8full/logs/asap7/mf8full/base/1_synth.json tools/chip-model/mf/results/out/mf8full/logs/asap7/mf8full/base/1_synth.log tools/chip-model/mf/results/out/mf8full/logs/asap7/mf8full/base/power_synth.log tools/chip-model/mf/results/out/mf8full/objects/asap7/mf8full/base/copyright.txt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/synth_check.txt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/synth_stat.txt tools/chip-model/mf/results/out/mf8full/results/asap7/mf8full/base/mem.json tools/chip-model/mf/results/sim/mf8base/gl2sim.log tools/chip-model/mf/results/sim/mf8base/sim_add_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_add_s500.log tools/chip-model/mf/results/sim/mf8base/sim_load_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_load_s500.log tools/chip-model/mf/results/sim/mf8base/sim_mad_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_mad_s500.log tools/chip-model/mf/results/sim/mf8base/sim_mix_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_mix_s500.log tools/chip-model/mf/results/sim/mf8base/sim_mixld_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_mixld_s500.log tools/chip-model/mf/results/sim/mf8base/sim_mul_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_mul_s500.log tools/chip-model/mf/results/sim/mf8base/sim_mulhi_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_mulhi_s500.log tools/chip-model/mf/results/sim/mf8base/sim_or_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_or_s500.log tools/chip-model/mf/results/sim/mf8base/sim_rotl_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_rotl_s500.log tools/chip-model/mf/results/sim/mf8base/sim_rotr_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_rotr_s500.log tools/chip-model/mf/results/sim/mf8base/sim_shfl_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_shfl_s500.log tools/chip-model/mf/results/sim/mf8base/sim_sub_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_sub_s500.log tools/chip-model/mf/results/sim/mf8base/sim_xor_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_xor_s500.log tools/chip-model/mf/results/sim/mf8full/gl2sim.log tools/chip-model/mf/results/sim/mf8full/sim_add_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_add_s500.log tools/chip-model/mf/results/sim/mf8full/sim_andn_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_andn_s500.log tools/chip-model/mf/results/sim/mf8full/sim_bfe_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_bfe_s500.log tools/chip-model/mf/results/sim/mf8full/sim_clz_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_clz_s500.log tools/chip-model/mf/results/sim/mf8full/sim_fwd_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_fwd_s500.log tools/chip-model/mf/results/sim/mf8full/sim_load_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_load_s500.log tools/chip-model/mf/results/sim/mf8full/sim_lop3_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_lop3_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mad_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mad_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mix1_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mix1_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mix2_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mix2_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mix64_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mix64_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mix_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mix_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mixld_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mixld_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mixw4_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mixw4_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mm8_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mm8_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mul_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mul_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mulhi_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mulhi_s500.log tools/chip-model/mf/results/sim/mf8full/sim_or_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_or_s500.log tools/chip-model/mf/results/sim/mf8full/sim_popc_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_popc_s500.log tools/chip-model/mf/results/sim/mf8full/sim_prmt_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_prmt_s500.log tools/chip-model/mf/results/sim/mf8full/sim_rotl_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_rotl_s500.log tools/chip-model/mf/results/sim/mf8full/sim_rotr_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_rotr_s500.log tools/chip-model/mf/results/sim/mf8full/sim_sel_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_sel_s500.log tools/chip-model/mf/results/sim/mf8full/sim_shfl_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_shfl_s500.log tools/chip-model/mf/results/sim/mf8full/sim_shfla_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_shfla_s500.log tools/chip-model/mf/results/sim/mf8full/sim_shl_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_shl_s500.log tools/chip-model/mf/results/sim/mf8full/sim_shr_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_shr_s500.log tools/chip-model/mf/results/sim/mf8full/sim_sub_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_sub_s500.log tools/chip-model/mf/results/sim/mf8full/sim_xor_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_xor_s500.log tools/chip-model/mf/results/table.csv tools/chip-model/mf/results/table.md tools/chip-model/mf/rtl/core_mf.v tools/chip-model/mf/rtl/mf32base.v tools/chip-model/mf/rtl/mf32full.v tools/chip-model/mf/rtl/mf8base.v tools/chip-model/mf/rtl/mf8full.v tools/chip-model/mf/tb/sram_models.v tools/chip-model/mf/tb/tb_mf32base.v tools/chip-model/mf/tb/tb_mf32full.v tools/chip-model/mf/tb/tb_mf8base.v tools/chip-model/mf/tb/tb_mf8full.v tools/chip-model/mf/tb/tb_mf_common.vh
2026-10-08 15:28:35 +00:00
igneum-labs
17b9901b67
Class v6 10.0m and 10.0n: the multi-family adversary's whole-machine rows (1.8x the 5090 node-for-node, the bank zero obsolescence credit, capex the larger half of the edge); the coexistence model landed (the board passes six conditions, the die fails five once sunk); the three statements re-read; the connected-state class killed; the window under 1 percent measured
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:27:51 +00:00
igneum-labs
03b7bf05a1
Class v6 floor lane 4: the RX 7600 (8 GB) measured on PC 1 (13.88 MH/s at 113 W, 8.14 microjoules, the card-in job 15:50 UK) added to the tiers table and the AMD estimates re-based on it; 10 of 10 on build-3
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 394da98a9394da98a91
2026-10-08 15:04:38 +00:00
igneum-labs
999fec1519
Merge class-v6-floor-denominator-docs-2 8384bfc7 into master (gate: green on 8384bfc7, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 15:03:47 +00:00
igneum-labs
8384bfc795
Class v6 floor lane 4: section 3 amendment, the memory clock is not a lever (floor lane 1's PC 1 ladder at the 1,300 lock: two driver states, the half-rate state costs 43 percent of rate for 37 percent of watts)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 6ef2a4ba86ef2a4ba86
2026-10-08 14:51:28 +00:00
