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igneum-labs
80736ef56b class v5 design page: section 14 carries adv-accept's multiplicity reading at the acceptance sample 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 19:40:48 +00:00
igneum-labs
a64aafb488 class v5 design page: section 14 carries adv-accept's class v5 check of the exemplar (the hot set does not move under the state dataset) and the known-failed test's reading 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 19:39:16 +00:00
igneum-labs
5eb809a1e9 class v5 design page: section 14 (the acceptance rule's class v5 part on the residual hot-set class, the two fixes, the floor taken), the witness row done, the class-walk exception, the harness skew and override-field rows 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 19:07:32 +00:00
igneum-labs
7674ea4325 class v5 harness: the accepted-after parser reads the miner's epoch-second line clock (it matched HH:MM:SS and counted nothing: the v5-fasttime lane's finding, 20:3x UK), with its own known-finished check (the honest miners must show accepted lines after the flip); the page's PASS rows say which two counts were parse misses and what they rest on until the re-run 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 18:38:42 +00:00
igneum-labs
03173925f2 class v5 design page: section 13's wire row done by the node lane (class-v5-node-wire 7737ebd9, version 1 with the last-field fallback, 43 exec tests), the witness row in progress 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 18:34:55 +00:00
igneum-labs
34ef31679c Merge remote-tracking branch 'build/master' into class-v5 2026-10-07 18:33:18 +00:00
igneum-labs
559362b329 class v5 design page: the M5 Max rows (class v5 +0.23 ms per warp over class v4 on one core, interleaved three times under the measure lock, both a quarter of the 10 ms gate); the time line 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 18:33:17 +00:00
igneum-labs
5e41217735 Merge build-server 65fdd39d into master on the box mirror (GitHub suspended since 18:02 BST; the box gate stamp stands in for CI; main's rule of 18:1x BST) 2026-10-07 18:23:34 +00:00
igneum-labs
65fdd39d5b Build boxes to near max (the project lead, 7 Oct 2026 19:4x BST): the bounded class is 88 of 96 cores with -j 88 (8 reserved for release builds, the seed and the observers), the jobs rule 88 alone / 44 shared, the spill line 80; checks updated. testnet-go.md: LG-2 waived by the owner, the new gate, the seeds held armed 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 18:23:14 +00:00
igneum-labs
d21ca54a24 Merge ship-docs-0321 9ee93d78 into master (gate: green on 9ee93d78, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-07 18:21:29 +00:00
igneum-labs
9ee93d782a release 0.3.22 section 7: the project lead moves the apps to Devnet 3 tonight (the clock), the pin 34a2dbaa with no heights and why, the app tree at 19:15 BST, PC 2's evening and the rules it added 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 18:17:15 +00:00
igneum-labs
3647ee02c9 class v5: the first class v5 pack, Devnet 3's epoch 0 (genesis 4020cb43... as epoch and era seed, day 20,733, the genesis state's 11 leaves under root 7e37a9fb...), generator 5, program id e5a4ac5978462156, exported on igneum-build-1 at 18:06:41Z; its Metal fingerprint 82b19cbde8557ea5 on the M5 Max at 18:07:09Z (vectors 3 of 3, cache and dataset PASS); the page's time line 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 18:07:55 +00:00
igneum-labs
5114936edf Merge build/master into ca3-coord (release-0.3.21.md keeps both sides); Counter ASIC 3.0 status: Devnet 3's proof window, the utilisation table, the bench table, the v5 gap list, the in-house pass, the PC 1 queue 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 18:05:34 +00:00
igneum-labs
d7d92a0c83 class v5: the design-to-code gap as section 13 (every item without code, test or measurement, with owner and hours: about 40 agent hours, 17 this lane's); the Metal pack bench takes a class v5 pack's leaves.bin (buffers 2 and 3 on igneum_build, the pack's FNV checked first) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 17:58:17 +00:00
igneum-labs
b35bf8f16f Counter ASIC 3.0 status: the Devnet 3 epoch-0 pack, the project lead's three orders and the in-house correction (class v5 now, the internal adversarial pass, the PC 1 measurements) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 17:54:43 +00:00
igneum-labs
f88783d09f Site and evidence: the chip model's next test is the internal adversarial pass (three lanes new to the hash code, outsider inputs only, reports published whole), not external lots; the one outside check staged on its escrow and the publish word (the project lead's correction, 7 October 2026) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 17:54:43 +00:00
igneum-labs
3a7ba78349 Merge remote-tracking branch 'build/ca3-v4-amend' into class-v5 
# Conflicts:
#	igneum-pow/src/generator.rs
 2026-10-07 17:53:53 +00:00
igneum-labs
82e9965a3c class v5: the harness records of the bytes-6 flip run (12:17 to 12:21Z) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 17:52:54 +00:00
igneum-labs
1a4ed8bb86 release 0.3.22: proving on Devnet 3 opens (first segment submitted 18:45 BST, the sizing), the 0.3.21 warm cases end and why the relay cell reads on Devnet 3 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 17:52:42 +00:00
igneum-labs
66190129a7 release 0.3.21 section 7: the Mac entry LIVE 18:41:50 BST, Windows as its own entry, the parallel installer shapes, the testnet 6ed56f63 line, the 0.3.22 pin candidate 34a2dbaa, the signing bonus paragraph 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 17:42:54 +00:00
igneum-labs
cfce2014fa release 0.3.22 section 6: DN3 GATE PASS, the two clocks, the tree order (a) to (f) with main's floor-file ruling, the project lead's nine-switch ruling and main's height mechanics, the testnet re-arm, the 0.3.21 Windows toolchain finding 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 17:40:37 +00:00
igneum-labs
31ca83daa1 release plans: 0.3.21 ships as the app tree over c4459193 (section 6, the GitHub exception window from 18:02 BST, the Windows path without windows.yml, the DMG 490919d9); 0.3.22 section 5 the Devnet 3 genesis on 69d1b56e at 18:06:19 BST (gates, pairs, the program id correction, the seed left off the sweep); rule 5 names the seeds in the wave list with a read-back line 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 17:25:23 +00:00
igneum-labs
ec3d55723c Counter ASIC 3.0 status: Devnet 3's pair agrees since 17:18Z (702 blocks, 0 rejected; first lock about 19:10Z on the 7,200-DAA window); the no-GitHub rule 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 17:20:43 +00:00
igneum-labs
e68b416f4b Counter ASIC 3.0 status: Devnet 3's epoch-0 program id fce15bf61030be57 (the id follows the seed; the pairing pin unchanged) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 17:12:25 +00:00
igneum-labs
7d9a81d8fb Counter ASIC 3.0 status: GitHub suspended (the mirror is the record), Devnet 3 mines on 69d1b56e from 17:06:19Z, the Hetzner seed still on the old object 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 17:09:33 +00:00
igneum-labs
4a2b7565e9 Counter ASIC 3.0 status: the 0.3.22 kaspa-pow suite green, master green on the pow fix, the chip texts live (incl. /claims), Devnet 3's first go refused on the genesis timestamp (8 Oct 00:00Z) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 17:03:06 +00:00
igneum-labs
0596574aa8 Counter ASIC 3.0 status: the pow stop-the-line executed (ca3-v4-amend on master as 2b9d50cc, igneum-pow byte-identical to c3d32437) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 16:48:07 +00:00
igneum-labs
2b9d50cc72 Merge ca3-v4-amend 6bb52c50 into master (gate: green on 6bb52c50, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-07 16:45:48 +00:00
igneum-labs
d960dc5cef Merge site-ui-5 70ddf80d into master (gate: green on 70ddf80d, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-07 16:45:01 +00:00
igneum-labs
6bb52c5007 Merge origin/master 90501503 into ca3-v4-amend (igneum-pow kept byte-identical to the frozen c3d32437 per main's stop-the-line ruling; the ledger keeps both sides) 2026-10-07 16:40:29 +00:00
igneum-labs
9b411c7ed8 Counter ASIC 3.0 status: the 0.3.22 re-pin staged (bd710a36, candidate fa7f854f, byte 7 from genesis) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 16:39:34 +00:00
igneum-labs
742ce2be53 Counter ASIC 3.0 status: the stop-the-line on master's pow suite (era-vdf's 61421005 against the pins), the hash lane's merge of 4f2f6097 ordered, the condition verified 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 16:39:05 +00:00
igneum-labs
4a5759e188 Merge remote-tracking branch 'origin/master' into site-ui-5 2026-10-07 16:37:57 +00:00
igneum-labs
5f9f9a4bbf site-ui-5: the capture set after the padding sweep and the launch-first chip text (every route at 390 and 1440 dark, the three bands, the full wallet page) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 16:37:57 +00:00
igneum-labs
e73fea9d8b site: the chip claim launch-first in the four public places (Counter ASIC lane, docs/plans/counter-asic-3-public-text-2026-10-07.md sections 1 to 4, on the project lead's "I thought we were making it 2.1 from launch?") 
Home row 03, the litepaper's chip section at /litepaper#chip-model (paragraph and table; the class v3 row last, "never the launch
state"), the miner page's line and evidence.md row 17 in its eight columns: 2.1x to 3.9x under class v4 from the first block,
class v5 removing the stored-dataset chip as a category, the 5x to 9x only as the class v3 baseline, the devnet's activation
height as a devnet fact. The litepaper's abstract carried the same claim in the old form ("5x to 9x today; class v4, now on
the vote") and now reads launch-first too. tools/ci/ledger-text-check.mjs follows the sentences (X35 on the home page and the
litepaper). No disclosure prize anywhere.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 16:34:12 +00:00
igneum-labs
c12b6012e4 Counter ASIC 3.0 status: Devnet 3 now (0.3.22, genesis by 17:30Z), the frozen sub-version 3 handoff (c3d32437, byte 7, id a785001687d8688a, gates green, open items stated), the chip text rewritten launch-first 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 16:32:40 +00:00
igneum-labs
2f53150c5a The chip claim, public text: rewritten launch-first (2.1x to 3.9x under class v4 from genesis; class v5; the 5x to 9x only as the class v3 baseline; the devnet's height a devnet fact) on the project lead's word 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 16:25:18 +00:00
igneum-labs
f127ce5198 Counter ASIC 3.0 status: the four-seed tail ruled accepted (AP-F8-1 closes), 0.3.21's first candidate passes the node gates; the lane stops for tonight 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 16:17:54 +00:00
igneum-labs
ed1d2ed885 Counter ASIC 3.0 status: the 0.3.20 record (publish 14:54:17Z, floor 900,000, digest 4bbbe816, sweep complete 15:39Z, earliest flip about 14 Oct 23:00Z); sub-version 3 at c3d32437 passes both gates with the named tail, the frozen generator for 0.3.22 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 16:11:02 +00:00
igneum-labs
4f2f60975b Counter ASIC 3.0 gates (hash): ledger AP-F8-1, F8's 64-seed gate and exhaustion count on c3d32437 (60 of 64, the four over = the named tail; 0 exhausted of 24,631), the node's draw-cost line 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 16:03:13 +00:00
igneum-labs
8d22c8f8ff Counter ASIC 3.0 status: release-0.3.21-node staged at 96161037 (byte 5, no re-pin), the set green, the floor file's digest 4bbbe816 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 16:01:00 +00:00
igneum-labs
8617bd4585 release plans on master: 0.3.20 live and swept (sections 38 and 39), the rules file with 4c and 14, the 0.3.21 plan as staged 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 15:41:42 +00:00
igneum-labs
6e638cf6ef Merge era-vdf 61421005 into master (gate: green on 61421005, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-07 15:31:24 +00:00
igneum-labs
84e6c82fb4 Counter ASIC 3.0 status: the hash lane's 78b7915e on origin, CI success; nothing in flight on the hash side 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 15:25:27 +00:00
igneum-labs
9f543aa970 Era VDF lane (7 October 2026): spec 04 sections 4.2, 4.4, 4.5 and 4.6 completed for the era path (the scheme byte and the hash-chain fallback, the cut rule under the O-4.3 reading, the day-of-blues input, the delay, the seed, the era constants as measured), spec 01 section 1.13.1 and era-layout.md section 8 updated, open items O-4.8 closed and O-4.10 to O-4.12 added, FUD ledger F11 updated, two decisions for the project lead in ledger-decisions.md, the record docs/analysis/era-vdf-2026-10-07.md (what was built, the parameters and measured rates, the harness gate with both runs, the cut rule for the finality lane, the verify gate, the tiers), the F7 re-roll harness against the real era cut (tools/era-vdf/reroll.mjs: --vdf off fires 6 of 6, --vdf on silent 0 of 6; the adversary evaluates asynchronously with the node's own code and is found by the node's own log line), the fast-time file's era fields 2026-10-07 15:24:22 +00:00
igneum-labs
4b4e1bc12f Merge master-pin-0320 b9b37480 into master (gate: green on b9b37480, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-07 15:20:54 +00:00
igneum-labs
16403d488d Merge ca3-coord c724ed86 into master (gate: green on c724ed86, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-07 15:18:58 +00:00
igneum-labs
4402e51e45 Merge bench-5060ti 8c019aa2 into master (gate: green on 8c019aa2, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-07 15:17:18 +00:00
igneum-labs
c724ed8632 Counter ASIC 3.0 status: the census at c3d32437 (0 lossy sites, 0 exhaustions, mean 2.086 attempts), CI success, the class check moving 2.0 percent of attempts 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 15:15:23 +00:00
igneum-labs
b9b37480a4 master re-pinned to the published 0.3.20 node (c4459193): packaging/windows/node-source.pin against the live payload-inputs.json, so windows-ci's payload inputs step reads green; release rule 14, master re-pinned at every publish 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-07 15:13:10 +00:00