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igneum-labs
6d0a52ea03 Litepaper and evidence: the hash's reads stated as measured (8 October 2026, lane D's family harness at 2^20 over 4,900 drawn eras and adv-cache-2's reading): "dependent reads spread over a multi-gigabyte dataset" in the lead, the measured clause after the chain-of-random-reads sentence (the 0.995 floor on every accepted program; about half of epochs with one biased address bit at the era's stride rotation; about 1.6 percent of a hash's reads to a chip storing half the dataset, nothing to a full store; the fold in the next class), evidence row 18 with its sources; ledger AP-F8-7 (Open, priced), the public ledger and the ledger page regenerated. Bench table: class v4 watts rows 7 to 10 (RTX 3070 196.4 W under a 193 W cap, +28 percent; RTX 3070 Ti 267.6 W uncapped, +48 percent; RTX 4060 no watts on any rented host; the 3080 Ti's deep-capped pair in its note, the first cap that costs rate, the uncapped rate standing) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:48:11 +00:00
igneum-labs
0defaba741 Merge spec-accept-23 ba08d6b8 into master (gate: green on ba08d6b8, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 10:45:43 +00:00
igneum-labs
1c02320532 Merge class-v6-history fd32fdc5 into master (gate: green on fd32fdc5, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 10:45:04 +00:00
igneum-labs
28effe9e2c Merge class-v6-family-gate 8551379f into master (gate: green on 8551379f, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 10:40:09 +00:00
igneum-labs
e08b5d70a6 Merge ca3-coord-record cf521c46 into master (gate: green on cf521c46, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 10:39:26 +00:00
igneum-labs
fd32fdc5ce Class v6 history lane, revision 3: the dataset-floor schedule priced per tier and against the chips (section 4.2a, main's ask of 11:2x UK) 
docs/analysis/class-v6/history.md 4.2a: main's 6, 10 and 14 GiB steps checked against every tier's room under the standing 75 percent budget rule (the card-lifetime method, the bench table's 32 measured consumer cards as the population): 6 GiB does not fit the 8 GB tier under the rule (78 to 82 percent of the card; it fits only at a headless-rig reading of about 85 percent), 10 GiB retires the 10, 11 and 12 GB tiers and the Apple 16 GB laptop at year 2, 14 GiB retires the 16 GB tier at year 4, leaving 24 GB and above; beside it the schedule that drops the tiers in the order main named (5.5 GiB at the v6 epoch, 8 GiB at two years, 11 GiB at four) with the year each tier falls and its share of the measured cards (6 GB 3 percent at day one; 8 GB plus the 10 GB RTX 3080 plus Apple 16 GB 25 percent at year 2; 12 GB 22 percent at year 4; 16 GB 28 percent at the 16 GiB step; 24 GB and above hold). Against the chips: the hybrid-bonded or soldered chip sized at launch dies at the first step it cannot carry (the E3's shape, 20 to 27 months) but a maker reading a public consensus field sizes to the step it wants (USD 160 more of GDDR7 on a USD 470 part; about 3x the memory die area for the Jasminer shape); the f = 1 GDDR7 chip's 32 GB board pays USD 0 through 16 GiB and keeps 5.1x; the SRAM store pays capex only at the cache doubling (USD 46 to 111 per die) and keeps 0.92x and 1.86x. The fleet's hashrate-weighted card census is owed. The arithmetic is checked by script against the card-lifetime working sets.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:38:53 +00:00
igneum-labs
d5c4b90d23 Merge class-v6-history 697fdd23 into master (gate: green on 697fdd23, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 10:35:30 +00:00
igneum-labs
cf521c467d Counter ASIC 3.0 status: the whole 60x file (six keys) landed on both lines, the index fold as a class v6 design row, class v5 level with v4 at the 5090's knee (the knee stands, the note off, the A4000's loss a cap effect), lane B's SRAM-store and HBM4E readings and main's three orders on them, the shipper's three readings and the cut tip edf77203, lane A's cut and verdict (the stored-dataset chip closed by no layer; the floor and a per-tier ceiling the numbers) with main's schedule to price, the snapshot digest stamp and the genesis difference as a gate on the pin, main's words 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:32:55 +00:00
igneum-labs
1fca12afbf Merge dex-devnet3 c64e809f into master (gate: green on c64e809f, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 10:32:52 +00:00
igneum-labs
5d1044ca25 Litepaper (and /claims, /randomx from it): the RandomX record as lane A's history reads it (docs/analysis/class-v6/history.md 2.3, 8 October 2026): one chip shipped, Bitmain's Antminer X5 (September 2023) at 1.46x per joule over a desktop CPU on silicon believed mining privately from about 2021; RandomX v2 released 25 March 2026 with its mainnet activation pending; the X9 withdrawn in May 2026 with zero units (the X36 sentence stands); "no chip shipped" and "seven years without a shipped chip" gone from every served sentence; ledger X34 and C2 corrected, pins moved, the public ledger and the ledger page regenerated. Governance line beside the class v5 crossing sentence (main's wording): classes rotate on findings and at least yearly, a class change is a release activated by block height; class v6 named as the design in progress with its four layers, dated 8 October 2026 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:32:47 +00:00
igneum-labs
8551379fc2 Merge build/master 0d7412ac into class-v6-family-gate (export-exclude.txt: both research paths kept) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:32:44 +00:00
igneum-labs
d87b8808f7 Merge ca3-coord-record 6821b686 into master (gate: green on 6821b686, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 10:31:47 +00:00
igneum-labs
697fdd23a1 Class v6 history lane, revision 2: the synthesis lane's reading of the six items folded in, lane B's hardware file cross-cited 
docs/analysis/class-v6/history.md: layer 2's open ceiling question replaced by the synthesis lane's resolution (the per-year ceiling as layer 2's first constant, the schedule's power-of-two step for the year; the state brings a step forward and never adds one), with the Ethereum-state figure kept as the reason the ceiling exists; the read-width rank reworded on the measured warrant (w16 latency-bound within 2.7 percent on the 5090 and the 9070 XT, within 1 percent on the M5 Max; the band is {4 B, 16 B}, nothing wider); the Jasminer X4 finding cross-cited to lane B's hybrid-bonded DRAM row (hardware-future.md 4.4, 13x to 17x modelled) as that row's shipped precedent at 5x on a planar node; the header records the 11:26 UK landing (eb71eaf3). No number changes.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:29:17 +00:00
igneum-labs
eb71eaf399 Merge class-v6-history 2b76937c into master (gate: green on 2b76937c, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 10:26:13 +00:00
igneum-labs
1dcb3882e1 Class v6 family gate (lane D), first cut: the parameter table with bands and margins, the sampling bound (rule of three, the union bound over the per-era tests' measured miss rates, the stratified corners), the three rings of per-era tests with known-failed shapes and clean-seed costs, the board over the testnet period and the proof-of-testing record format, the honest line; the harness running on the boxes and its first 16-era reading (the era-stride class at 130 to 511 sigma on one address bit in 7 of 16 drawn eras); docs/analysis/class-v6 excluded from the public export 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:25:17 +00:00
igneum-labs
fde5957287 Merge class-v6-hardware 93e55f9d into master (gate: green on 93e55f9d, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 10:24:52 +00:00
igneum-labs
6821b6862e Counter ASIC 3.0 status: main's word on the two reds (the detach in 0.3.25 if green by 12:15), the day-key scan to 2^28 PASS, the sweep reruns read as none, the attack-pass branch merged and pushed, the family gate's first coverage (16 eras; the index-bit bias firing at address bit R on 7 of 16 drawn eras, a class v6 design row: load_index's form, not a floor; the bucket bound in sigma), the ota test literal fixed (f1a8102a, the detach rides 0.3.25) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:24:10 +00:00
igneum-labs
2b76937caf Class v6 history lane, first cut: every ASIC-resistant proof of work and its chips by mechanism, the four-layer mapping with a number per chip class, and the three lessons that bind on v6 
docs/analysis/class-v6/history.md: 21 chip rows by mechanism (what each chip specialised, what the design missed, the timeline, the v6 layer, closed or not, the per-joule number); in-depth sections for Ethash (the E3's DDR3, Linzhi's 4.4 GB beside 64 compute units, the Jasminer X4's DRAM hybrid-bonded onto a 40/45 nm die, the E9), ProgPoW (the Least Authority and Rao audits read from the PDFs, Kik, Linzhi's claim, the adopters), RandomX (the X5's RISC-V board at 1.46x, the X9 announced December 2025 and withdrawn May 2026 with zero units, RandomX v2 released 25 March 2026 with activation pending, the Qubic episode as the detector's lesson), Cuckoo (the GRN1's 512 MiB SRAM die, the G32, the iPollo G1, the 2025 bounty), Equihash (the Z9's single die, the Fudan parameter-following design), Scrypt and Argon2 (the BM1485's on-die scratchpads, Percival's lookup gap, MTP), the no-chip hashes, kHeavyHash, CryptoNight, X16R, Lyra2REv2, the compute rows. The four layers against the history layer by layer, with the E3's death dates, Autolykos's growth rule, the design-cycle and FPGA-compile clocks, and the honest verdict that the stored-dataset chip (class C) is not closed by any layer: 5.1x per joule at zero premium, 2.1x with the shadow at k = 1. Two corrections to the 5 October file (the X9, RandomX v2) and one claim marked unverified (the 5x fork-surviving chip). First cut for 15:00 UK; the full report by 09:00 UK on 9 October.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:19:10 +00:00
igneum-labs
93e55f9d43 Class v6 research lane B: the hardware future, five years out (first cut and the full report in one file) 
docs/analysis/class-v6/hardware-future.md: one table over PIM and PNM (HBM-PIM, AiM, LPDDR5X-PIM, UPMEM), HBM3E, HBM4 and the custom HBM4E base die, fine-grained DRAM on logic, LPDDR6, 3D DRAM, RLDRAM 3 and Folded Banks, FPGA with HBM2e, wafer-scale, CXL, optical I/O, chiplets and UCIe, and SRAM at N2: energy per dependent read, latency, cost per GB, availability to a non-hyperscaler, the k_read and shadow k bands, the edge per joule at zero shadow against the 5090 and the M5 Max, and the one layer of the four that blunts each with a number. The three findings: a 2 GiB SRAM full store on one N2 reticle is the strongest five-year chip (13x to 17x per joule, about USD 0.3 per MH/s) and no layer reaches it (layer 2 moves its capex, not its joules; the shadow at k = 0.5 holds 4.8x); per-bank PIM is blind (1.6 percent of reads in-bank at 2 GiB) and the custom HBM4E base die is the f = 1 chip with its controller in the stack (6.5x to 14x), untouched by layers 1 to 4; the denominator is the wrong card (the M5 Max at 0.78 microjoules halves to thirds every chip edge). Section 5 carries the k bands for the research lane's chip rows; section 7 the four decisions with defaults and deadlines; section 9 the sources with URLs and dates. tools/ci/export-exclude.txt: docs/analysis/class-v6 is research, not public export.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:17:50 +00:00
igneum-labs
0d7ecc6432 Counter ASIC 3.0 status: the founder's load order on the four boxes and its placement (lane D's family sampling, the attack families at scale, lane C's packs, the pin matrix, the cross builds), the drift class settled by a fresh-walk node, the pin candidate e0644958 confirmed, the Windows installer class and the detach fix, the tiers' class-flip pair gated (081b3ba7), the rpc up, two reds on the release line from the first ten minutes of the load order (the missing 60x field; the detach's test literal) with their fixes and defaults 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:14:50 +00:00
igneum-labs
b86e4845b5 DEX: the AMM live on Devnet 3 (factory 0x09FF42db, router 0x9a6fA842, WIGN 0x47447783, TTA, TTB, three seeded pools; docs/contracts/devnet-3.json), the faucet's first drip, the Seed script with the node's own gas estimates (Devnet 3 charges proving gas inside execution gas) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:14:48 +00:00
igneum-labs
04074f5bdc Merge ship-docs-0321 dea360cc into master (gate: green on dea360cc, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-08 10:12:42 +00:00
igneum-labs
dea360cc65 release record section 24: the first lock on cc902690 (checkpoint 1931, 10:06:32 BST), the move's count and the three puller faults closed, 0.3.24 Windows take 2 (Inno stopped the app and copied nothing; the /IGNOTA=1 rule), 0.3.25 opened (tip 78dfe65e, the ceiling cut e0644958, digest 1b37cb9d, the DMG 501ba293 staged, the clock), the tiers at the class flip, the signed apps pipeline (Igneum Labs LLC) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:03:40 +00:00
igneum-labs
fe940213a6 Counter ASIC 3.0 status: the 0.3.25 pairs and app tip (78dfe65e on the ceiling cut e0644958, its fast-time PASS at 10:54), the tiers' class-flip UI half (d949e274), the four builder lanes and the class v6 declaration with its four research lanes spawned and the outline on the mirror, the Arc re-read and v5lock jobs live, the held-push cause (the branch's own hook predating the per-process fix) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:01:24 +00:00
igneum-labs
d96faddae4 Counter ASIC 3.0 status: the 0.3.25 pairs on 7bd2940f and the re-pointed app tip 9b1ec8dc (every input green at 10:33 bar the pin's gates and the crossing), main's sweep finding (class v5 17 percent under v4 on a power-capped A4000; a knee-locked card may lose a few percent at the crossing until Ember re-tunes) and its two orders with their defaults 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 09:48:45 +00:00
igneum-labs
25c0d75bab Counter ASIC 3.0 status: the 10:05 move's read-back (36 of 36 on the pin by 10:12, the first lock 10:06:32, carrying resumed; three fault classes named), the tiers gated (d3d0704a), the knob's tip e2962b89, the 0.3.25 app line assembled at 10:29 (e0d4425f), the node line's tip 7bd2940f with the one-shot gossip fix and the drift item reclassified 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 09:31:37 +00:00
igneum-labs
de551552dd Counter ASIC 3.0 status: the 0.3.25 plan (the shipper's), main's word (the tiers both halves, gated) and the founder's word (0.3.25 today: the app line by 12:30, the pin by 13:00, the move after the 68,400 crossing reads clean, about 13:30), card-in ready, the tiers' UI half merged, the second deploy (d12e0684), the node line placeable ahead of its minute (c6629572), the knob's tip e2962b89, the Hetzner boxes on the founder's word 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 09:20:01 +00:00
igneum-labs
01d2e123c0 Counter ASIC 3.0 status: the site deployed (1e21bbac at 10:00 BST), row 17's floor sentence and the Arc row restored (96c7c7db), the 0.3.25 node build's shape and main's word on the fee ceiling (no second object cut today), class-v5 8f481459 gated with the Intel fix, the per-process gh fix on master (12f6f9a8), the AMD knob for tonight's cut, the 0.3.24 move FIRED at 10:05:00 BST (the Mac entry and the hive live 10:08:35, the three nodes on the pin, class v5 at 68,400 about 12:54) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 09:11:58 +00:00
igneum-labs
8b0a5a8a40 release rules 11 extended (never a kill pattern the shell carries; a kept datadir's locks); release 0.3.22 section 23: the move executed, 0.3.24 Mac and HiveOS LIVE 10:08:35 BST, the Windows chain on PC 2 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 09:11:06 +00:00
igneum-labs
d12e0684c6 Merge ca3-coord-record 5ebeff23 into master (gate: green on 5ebeff23, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 09:07:55 +00:00
igneum-labs
5ebeff2342 Counter ASIC 3.0 status: the gh switch owned by the attack-pass lane and the rule to every lane, the Intel fix on master (7616ccd4), the pairs on the pin, class-v5 a55fcc10 and the rebuilt kit (65b47211), the AMD grid prepared, the AP-F8-1 record line (4026be32) and the card-in job, the in-house pass's last landing (1bf68cdf), the attack-pass tail (8a2fc793), the signal-15 hook note 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 09:01:49 +00:00
igneum-labs
96c7c7db7e Merge spec-accept-23 1ac664e3 into master (gate: green on 1ac664e3, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 08:59:34 +00:00
igneum-labs
1e21bbacea Merge ca3-coord-record d0ea857d into master (gate: green on d0ea857d, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 08:58:40 +00:00
igneum-labs
8a2fc79398 Merge attack-pass 29239a22 into master (gate: green on 29239a22, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-08 08:55:29 +00:00
igneum-labs
1bf68cdf29 Merge crypto-engage f1c86098 into master (gate: green on f1c86098, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 08:54:42 +00:00
igneum-labs
4026be326d Merge ca3-v4-amend 8a63248c into master (gate: green on 8a63248c, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 08:54:04 +00:00
igneum-labs
1ac664e3b6 Merge build/master 7616ccd4 into spec-accept-23 (the Intel rotr worker fix taken; /miners rebuilt from the merged bench data) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 08:52:59 +00:00
igneum-labs
d0ea857d77 Counter ASIC 3.0 status: the move's readings and the pin line on 5b673577, the founder's standing rule (defaults and deadlines; the shipper's clocks mirrored) and its distribution, the Arc self-test read (the shipped workers right, the kit lacking the Intel rotate fix), the AMD knob opened (a002732a), the F8 tail attributed on the Mac (a per-site bucket concentration), the fast-time PASS and the minute 10:05:00 BST, the gh exception on the Mac, adv-accept closed (BOUND, no BREAK) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 08:51:32 +00:00
igneum-labs
9b057c02ed release 0.3.22: THE MINUTE 10:05 BST set in m5b67-1, the pairs and the hive on the pin, what moves at the minute 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 08:49:41 +00:00
igneum-labs
29239a2296 attack-pass: the status board, F8 row, gate line and re-gate paragraph read the tail as attributed 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 08:49:21 +00:00
igneum-labs
f1c860983e in-house-pass.md: adv-accept closed (15.1 box-hours, 796,042 accepted programs, BOUND, no BREAK); the pass's totals final 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 08:48:22 +00:00
igneum-labs
7ac25503ed attack-pass: AP-F8-1 tail attributed (p4, p8, p10, p34 as per-site bucket concentration at a narrow-window site; the largest-bucket bound named for a next class) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 08:48:03 +00:00
igneum-labs
8a63248c68 ledger AP-F8-1: the four-seed tail attributed (8 October 2026 Mac read at 2^24): one narrow-window site per seed, a quarter-bit bucket concentration from a mad, xor or sub writer, no lossy source, no chip consequence; the per-site bucket bound is a morning item 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 08:47:41 +00:00
igneum-labs
33addc3f94 release 0.3.22 section 22: the morning (main's word, the founder's rule, the fifth cut 5b673577, the move staged, the fleet's reading, the Arc answer) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 08:46:22 +00:00
igneum-labs
645ddb2014 Counter ASIC 3.0 status: main's morning words (the look landed, the floor sentence to row 17, CA4 parked, the Mac rule lifted for the F8 tail, route (A) at 10:45 BST), the build-server lane's honest state and the deploy and pairs plan, the fourth cut 5b673577 (floor 68,400), the Arc B580's self-test fault on both classes and the Intel kit held out of 0.3.24, the design pass on master (d8459e79) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 08:40:46 +00:00
igneum-labs
ca5151eef5 Evidence row 17: the in-house pass's floor reading beside its sentence (nine of nine hot sets refused; the diffuse era-stride excess, bounded under 0.1 percent of a hash's reads per site, is not caught by the floor and is the next class's test; measured 8 October 2026, ledger AP-F8-1 and AP-F8-6); /evidence rebuilt 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 08:33:21 +00:00
igneum-labs
54adb48ce0 Counter ASIC 3.0 status: the 9070 XT bench row on master (the AMD watts no longer owed), the hot-table ldcs rows (a dead lever; the hot family latency-bound), the PC 1 list main set closed on measured rows 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 07:13:01 +00:00
igneum-labs
cf4d5c143c Merge ca3-v4-amend 780b608d into master (gate: green on 780b608d, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 07:11:38 +00:00
igneum-labs
780b608d4d bench-log: the hot-table packs on the RTX 5090, ldcs against base, unlocked and at the 1,300 MHz lock (36 rows, all PASS; ldcs dead, the hot packs lose 2 percent to the lock where mx8 loses 7.5) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 07:05:19 +00:00
igneum-labs
575c07c721 Merge ca3-coord-record 0cc932f3 into master (gate: green on 0cc932f3, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 06:27:36 +00:00