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igneum-labs
4e6c6fc87c Counter ASIC 3.0 status: the blocker closed (G4 re-run with the id assertion green), every gate green, the line for the project lead confirmed 2026-10-06 16:45:52 +00:00
igneum-labs
365e927200 Merge branch 'ca3-v4-node' into ca3-coord 2026-10-06 16:44:27 +00:00
igneum-labs
ffe335d768 Counter ASIC 3.0 gates (node): the program id carries the class: G4 re-run GREEN with the id assertion (every v4 epoch's id = the CLI's class v4 id, differs from the same-seed v3 id; the assertion's failed case fails on that one check), the seven re-exported packs' Metal fingerprints equal the hash lane's table, G5 workers rebuilt from the fix 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 16:43:46 +00:00
igneum-labs
52aa917089 Counter ASIC 3.0 status: the hash lane green on the id fix (c17e6b6 merged) 2026-10-06 16:40:09 +00:00
igneum-labs
f21598563f Merge branch 'ca3-v4-hash' into ca3-coord 2026-10-06 16:39:24 +00:00
igneum-labs
c17e6b668c Counter ASIC 3.0 gates (hash): follow-up 1 on the program-id fix (49884b9 merged): crate suite 97 of 97, the seven v4 packs re-exported byte-identical (generator 4, id c120d7963abdcd96), fingerprints unchanged on Metal and Apple OpenCL, Mac G2 16 x 1,024 of 1,024 through the v4 class token, the harness 4 of 4 on the class and on the era with the id assert_ne holding; the job scripts take the class token from the pack 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 16:38:48 +00:00
igneum-labs
ee76f6ca70 Counter ASIC 3.0 status: the program-id fix merged (49884b9), the re-runs open 2026-10-06 16:26:11 +00:00
igneum-labs
60414c6498 Counter ASIC 3.0 status: AMD G2 job ready (chain-seed packs, own kit) 2026-10-06 16:22:31 +00:00
igneum-labs
e0ac1ccde0 Counter ASIC 3.0 status: every gate green on the hash, the program-id blocker on the cut, the one line for the project lead 2026-10-06 16:18:08 +00:00
igneum-labs
a1fa94e9b8 Merge branch 'ca3-v4-node' into ca3-coord 2026-10-06 16:16:21 +00:00
igneum-labs
7380469f43 Merge branch 'ca3-v4-hash' into ca3-coord 2026-10-06 16:16:21 +00:00
igneum-labs
40f7b77821 Counter ASIC 3.0 gates (hash): the RTX 5090 G1 and G2 JSON summaries 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 16:15:17 +00:00
igneum-labs
c44281cfac Counter ASIC 3.0 gates (hash): the RTX 5090 G1 and G2 evidence from the collected job.log (eight fingerprints equal to the Mac's, 8 x 1,024 of 1,024); hash-gates.md and the bench-log entry closed 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 16:14:08 +00:00
igneum-labs
38b5a0e241 Counter ASIC 3.0 gates (node): G6 row, the two crates whose lines the relay upload does not carry 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 16:10:30 +00:00
igneum-labs
a32925abbc Counter ASIC 3.0 gates (node): G4, G4b, G5 and G6 GREEN for class v4 (the three fast-time summaries incl. the known-failed case, node-gates.md, counter-asic-3-node.md) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 16:10:00 +00:00
igneum-labs
880b359d42 Counter ASIC 3.0 gates (hash): the gate directory (hash-gates.md, G1 Mac, G2 Mac, G3 and verifier JSON) and the bench-log entry; the RTX 5090 G1 rows pending the collected job.log 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 16:07:55 +00:00
igneum-labs
526000a614 Counter ASIC 3.0 status: job 1 closed (G1 AMD green, the 9070 XT ladder flat to 330,700 ops, watts owed) 2026-10-06 15:58:03 +00:00
igneum-labs
03f55677f6 Counter ASIC 3.0 status: G1 AMD green on the candidate pack (interim, job 1 running) 2026-10-06 15:52:47 +00:00
igneum-labs
1960bbb262 Counter ASIC 3.0 status: the Ember run 5 rows for the 5090 (the cap never binds, 0.41 MH per W flat) 2026-10-06 15:45:39 +00:00
igneum-labs
1552536365 Counter ASIC 3.0 status: the PC 1 AMD scripts ready (checks pass, kit verified) 2026-10-06 15:40:42 +00:00
igneum-labs
76c19c9516 Counter ASIC 3.0 status: the gate run opened on mx8+sh256x27 (the project lead 16:50 UTC), the gate table 2026-10-06 15:38:44 +00:00
igneum-labs
651b0315e4 Counter ASIC 3.0 status: the PC 1 AMD job queue (prepared, not published) 2026-10-06 15:13:22 +00:00
igneum-labs
4ae285f25e Counter ASIC 3.0 status: the close (items 6, 7 and 8 closed; the chip model before and after; the class v4 candidate mx8+sh256x27 ready for the gate run; nine decisions for the project lead; the owed list) 2026-10-06 08:48:18 +00:00
igneum-labs
ca40decd9e Merge branch 'ca3-reserve' into ca3-coord 2026-10-06 08:45:48 +00:00
igneum-labs
40444c3b4c Merge branch 'ca3-shadow' into ca3-coord 
# Conflicts:
#	docs/bench-log.md
 2026-10-06 08:45:48 +00:00
igneum-labs
0d47586d8f Counter ASIC 3.0 items 6 and 7: the RTX 5090 step-cost rows (PC 2 job run-ca3-family-pc2-20261006, every family bit-exact, mm8 included) in the bench-log and the reserve document 2026-10-06 08:45:02 +00:00
igneum-labs
ed5e4c19ae Counter ASIC 3.0 item 8: the RTX 5090 rows, the chip side on the measured 11 pJ per op, the verdict 
PC 2 job run-ca3-shadow-pc2-20261006 (card empty, every pack bit-exact against the Mac): the 5090 holds its rate to
150,800 ops per hash and loses 2.7 percent at 199,600 under the app's 431 W cap, which binds from 102,100 ops up and
takes the clock from 3,037 to 1,834 MHz (86 MH/s at 330,700 ops); 350 W at the control, 2.65 to 3.27 microjoules per
hash; marginal ALU energy 10 to 13 pJ per counted op. Clock rows OWED (nvidia-smi refused -lgc without rights). Chip
side at N = 100,000 and k = 1: 2.1x over the 5090 on GDDR7, 0.9x over the M5 Max. GO at mx8+sh256x27.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 08:44:57 +00:00
igneum-labs
94cb5993d3 Merge branch 'ca3-derive' into ca3-coord 
# Conflicts:
#	docs/bench-log.md
 2026-10-06 08:31:10 +00:00
igneum-labs
ee5afcfe03 Counter ASIC 3.0 item 2: the RTX 5090 rows from PC 2 (bit-exact on CUDA, +1.1 s NVRTC per pack, the card-off key finding) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 08:30:15 +00:00
igneum-labs
13013a3abd Counter ASIC 3.0 status: the detector's two calibration findings answered (8bbc524 merged; max r 0.10) 2026-10-06 08:29:28 +00:00
igneum-labs
340096939e Counter ASIC 3.0 status: PC 2 clear, the detector and vendor-share dry rows on the live tables, the restart constraint 2026-10-06 08:26:52 +00:00
igneum-labs
55f3c5a158 Counter ASIC 3.0 status: the marker guard exists in CI already 2026-10-06 08:25:02 +00:00
igneum-labs
1c9ae00189 Counter ASIC 3.0 status: items 6 and 7 merged (5090 rows queued), the marker slip recorded 2026-10-06 08:24:50 +00:00
igneum-labs
c692253ea1 Merge branch 'ca3-reserve' into ca3-coord 
# Conflicts:
#	docs/bench-log.md
#	tools/observer/observer.mjs
 2026-10-06 08:24:29 +00:00
igneum-labs
236a588c67 Merge ca3-shadow (item 8's Mac rows) into ca3-coord: LoadClass carries derive_len and shadow; igneum-pow suite 96 passed 2026-10-06 08:11:03 +00:00
igneum-labs
1bc5da3d03 Counter ASIC 3.0 item 8: the CUDA text checked in the clang emulation and the OpenCL text on Apple OpenCL (gate G1 row) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 08:10:25 +00:00
igneum-labs
43e767e964 Counter ASIC 3.0 item 8: the Mac rows 
The M5 Max ladder (Metal, packbench, IOReport GPU and DRAM watts without root): latency-bound to about 100,000 ops per
hash, the 5 percent point about 130,000, 11 to 27 W GPU at 100,000 ops, 0.78 to 1.40 microjoules per hash; the
verifier's law 2.06 ms + 3.2 us per 1,000 shadow instructions per warp on one core; every pack bit-exact. The
analysis file with the knob, the chip side (k = 1, 1.5, 0.3), the gates and the consequences; the bench-log entry;
the 5090 rows pending the PC 2 job (the playbook now carries the core-clock rows and the sh256x40 rung).

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 08:08:26 +00:00
igneum-labs
e9463b504a Counter ASIC 3.0 status: the 5090 draws about 290 W at the hash, cap floor 400 W, clocks are the lever (item 8's job) 2026-10-06 07:59:42 +00:00
igneum-labs
162121de7b Counter ASIC 3.0 status: item 2's verifier headroom table and the crate suite 2026-10-06 07:51:42 +00:00
igneum-labs
e99322690f Merge branch 'ca3-derive' into ca3-coord 2026-10-06 07:51:42 +00:00
igneum-labs
3aaa0c837c Counter ASIC 3.0 status: PC 2 clear about 08:35Z, the job order 2026-10-06 07:51:36 +00:00
igneum-labs
35ab9e4a29 Counter ASIC 3.0 status: item 2 interim (GO as reserve, NO-GO genesis-live at dr736), PC 2 clear about 08:35Z 2026-10-06 07:51:15 +00:00
igneum-labs
22134b3846 Counter ASIC 3.0 item 2: the verifier headroom per class under the 10 ms gate (the budget item 8 shares) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 07:51:13 +00:00
igneum-labs
399f974b95 Merge branch 'ca3-derive' into ca3-coord 
# Conflicts:
#	docs/analysis/chip-model-v3.md
 2026-10-06 07:51:00 +00:00
igneum-labs
b4b3f0d39a Counter ASIC 3.0 item 2: the design, the Mac measurements, the chip-model row and the PC 2 job 
docs/plans/counter-asic-3-derivation.md (the design, the acceptance test, the interpreter, the allowance argument,
the measurements, the PROPOSED reserve entry R0 for 1.13.2, what is owed), docs/analysis/chip-model-v3.md section 6
(the per-day derivation rows at 1.0x to 3x allowances), the bench-log entry, relay/playbooks/ca3-derive-pc2.ps1
(one PC 2 job: self-fetched packs zip, the installed worker through NVRTC, the card off only under test with its
key from settings.json). Verifier 4.875 / 4.944 ms per unit on one M5 Max core under the measure lock against
x8's 2.061 / 2.063; Metal build 29 ms against 22; hash rate equal; bit-exact on Metal and Apple OpenCL.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 07:50:01 +00:00
igneum-labs
9e3461251a Counter ASIC 3.0 status: items 4 and 5 closed, the owed list opened 2026-10-06 07:48:56 +00:00
igneum-labs
53b7de9e74 Merge branch 'ca3-detector' into ca3-coord 
# Conflicts:
#	docs/plans/funding.md
 2026-10-06 07:48:42 +00:00
igneum-labs
230e95566b Counter ASIC 3.0 items 4 and 5: the issuance trigger, the signal trigger, the FPGA lane and the layer 9 against layer 7 ranking 
docs/plans/funding.md rule 5: the bounty is escrowed and the benchmark live before daily
issuance crosses USD 20,000 a day, with the price-per-IGN table per halving period.
docs/plans/epoch-length.md section 11: the detector alert held 6 net windows recommends
the next shorter ladder step, per-tier costs at 2,400 and 600, the adversary's share per
compile class. Section 12: HBM FPGA parts with sources, reads in flight per watt against
the RTX 5090 (0.3x to 0.4x at Shuhai's measured rate, up to 1.9x at the unmeasured bank
ceiling), the two FPGA lanes in one table, and the ranking: layer 9 above layer 7.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 07:47:21 +00:00
igneum-labs
1765e892eb Counter ASIC 3.0 items 6 and 7: proposed reserve order and spec text (docs/plans/counter-asic-3-reserve.md), the vendor-share section on the benchmark page, the observer README row 2026-10-06 07:40:41 +00:00
igneum-labs
a3ce00f206 Counter ASIC 3.0 status: item 6's Mac step costs (interim) 2026-10-06 07:36:58 +00:00