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igneum-labs
2da9902ff2 Merge branch 'amd-prove' into ca2-coord 
# Conflicts:
#	docs/bench-log.md
 2026-10-05 21:03:58 +00:00
igneum-labs
ffd6727d0d docs/analysis/amd-proving.md: no zkVM proves on AMD (SP1, RISC Zero, Jolt, OpenVM, ICICLE cited), the SP1 CPU prover measured on PC 1 beside the miners (282 s a shard at any size, 30 GB RSS: no CPU tier), the tier consequences and the public line; PC 1 job scripts with the bash -n gate; bench-log entry 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 21:02:59 +00:00
igneum-labs
8c7c04af6b Counter ASIC 2.0 status 21:02: the measure lock convoy, found by lsof 2026-10-05 21:02:13 +00:00
igneum-labs
82df544980 Counter ASIC 2.0 status 21:01: the 0.3.10 installer build takes PC 1 after the repro run 2026-10-05 21:01:20 +00:00
igneum-labs
a134206f10 Counter ASIC 2.0 status 21:00: PC 1 to the repro run, PC 2 to agg-cost, the CPU fallback numbers, the S_p shard dropped 2026-10-05 21:00:58 +00:00
igneum-labs
7abf162600 Counter ASIC 2.0 status 20:58: PC 1 and PC 2 occupancy 2026-10-05 20:58:57 +00:00
igneum-labs
17017f3bf7 Counter ASIC 2.0 status 20:57: the mixer construction committed, MX4 is V3_CLASS 2026-10-05 20:57:12 +00:00
igneum-labs
f69ae9ff03 Counter ASIC 2.0 status 20:56: PC 2 released, the proving fork tip, the S_p curve with the miner on 2026-10-05 20:56:23 +00:00
igneum-labs
edd0c57acd counter-asic-2.md: layer 9 row and the decisions table of 5 October 2026 (night) 2026-10-05 20:53:45 +00:00
igneum-labs
f2e3a57754 Spec 01 1.4.5 and 1.4.6: generator 3, the class and era seed in the pack and on the job line, the refusal rule 2026-10-05 20:53:26 +00:00
igneum-labs
a360410c0c Counter ASIC 2.0 status 20:53: spec text applied for layers 6, 7, 9; what still lands from the branches 2026-10-05 20:53:12 +00:00
igneum-labs
3fce116e0f Spec 01 and 04: layer 9 epoch_len (1.12, 1.13.1, 4.3), reserve family R1 and the emulation rule (1.13.2), the cache growth rule option C and the step mapping (1.13.3), the mixer_mult row 2026-10-05 20:52:58 +00:00
igneum-labs
d9c22dfc4d Counter ASIC 2.0 status 20:51: chain_dataset_day wired in the node, evidence row 22 2026-10-05 20:51:52 +00:00
igneum-labs
e8a24607c5 evidence.md: the card-lifetime claim as a designed row under the step schedule 2026-10-05 20:51:38 +00:00
igneum-labs
b1ee345af9 Litepaper hardware line on the step schedule; status 20:51: public copy applied, level 1 and the limits bullet wait for the chip row 2026-10-05 20:51:26 +00:00
igneum-labs
ed9409cc39 Site and litepaper: the level 2 chip-resistance copy (three ideas, the fourth paragraph), the latency correction, the card-lifetime lines under the step schedule 2026-10-05 20:51:13 +00:00
igneum-labs
1bbba75602 Counter ASIC 2.0 status: readwidth head hash corrected to 4301618 2026-10-05 20:50:30 +00:00
igneum-labs
97b7f762fa Counter ASIC 2.0 status 20:50: the measure lock holder, the with-lock status defect 2026-10-05 20:50:05 +00:00
igneum-labs
c220fc07a9 Counter ASIC 2.0 status 20:49: mixer construction, the lock cleared, PC 2 state, one merged-tree suite job 2026-10-05 20:49:39 +00:00
igneum-labs
878c358f93 Counter ASIC 2.0 status: heading times 20:42 to 20:47 corrected to the commit clock 2026-10-05 20:48:20 +00:00
igneum-labs
c2d468f524 Counter ASIC 2.0 status 21:15: the Sonnet box off the link, PC 1 facts corrected, the queue 2026-10-05 20:47:57 +00:00
igneum-labs
49a7a3bd53 Counter ASIC 2.0: the G1 ruling (gfx1036 as the AMD vendor tonight), hardware events section for the morning 2026-10-05 20:46:20 +00:00
igneum-labs
b7b2e4f9a6 Counter ASIC 2.0 status 21:05: the 9070 XT absent on PC 1, app restart facts, era package ETA 2026-10-05 20:45:35 +00:00
igneum-labs
14e37c6b5f Counter ASIC 2.0 status 21:00: the Metal pack path, the --prepare-packs app item, the seam signatures, the build queue 2026-10-05 20:44:16 +00:00
igneum-labs
1bf09044d5 Counter ASIC 2.0 rollout: the rig miners' exit-42 path on the next-cut list as a layer 9 precondition 2026-10-05 20:42:03 +00:00
igneum-labs
b2b6f80c43 Counter ASIC 2.0: C18 per-pound correction struck everywhere, C19 and C20 routed 2026-10-05 20:41:50 +00:00
igneum-labs
002ed3fcab Counter ASIC 2.0 status 20:45: the node switch written, the Metal worker gate item, PC 1 gaps 2026-10-05 20:41:37 +00:00
igneum-labs
e32443404d Counter ASIC 2.0 status: heading times corrected to the commit clock (UTC) 2026-10-05 20:41:03 +00:00
igneum-labs
524226ba66 Counter ASIC 2.0: rig-install follow-ups on the next-cut list, the CPU fixture in the PC 1 gap, no more agents 2026-10-05 20:39:44 +00:00
igneum-labs
bd643d3c0d Counter ASIC 2.0 status 23:20: the PC 1 queue 2026-10-05 20:39:03 +00:00
igneum-labs
f14a74fdd9 Counter ASIC 2.0 status 23:10: layer 7 PC rows, PC 1 free 2026-10-05 20:38:08 +00:00
igneum-labs
9ea226f9c9 Counter ASIC 2.0 status 23:00: layer 9 agent, PC queues 2026-10-05 20:32:53 +00:00
igneum-labs
669b54a0fd Counter ASIC 2.0: card lifetime merged, cache freed after the build, growth mapping (b) recommended, public lines listed 2026-10-05 20:31:48 +00:00
igneum-labs
b96193dd5b Merge branch 'card-lifetime' into ca2-coord 2026-10-05 20:31:25 +00:00
igneum-labs
70724b7258 docs/analysis/card-lifetime-2026-10-05.md: years each card tier keeps mining under the dataset schedule and the working-set rule, against the site and litepaper claims 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-05 20:30:46 +00:00
igneum-labs
b62e88cb66 Counter ASIC 2.0 rollout: ota-k2 commit on the next-cut list 2026-10-05 20:29:37 +00:00
igneum-labs
38c5a6b34b Counter ASIC 2.0 status 22:40: C1 decision and the 16:00Z check, one packfile.h fix 2026-10-05 20:29:09 +00:00
igneum-labs
95541c77a7 Counter ASIC 2.0: layer 9 row, C1 constraint, era mid-way and the attempt-aware packfile bug, C10 and C11 answers 2026-10-05 20:27:58 +00:00
igneum-labs
b0c4816a92 Counter ASIC 2.0: layers 1, 2, 3 decided from the readwidth table, layer 5 Mac rows and the added-form redesign, user tiers, public level 2 edit 2026-10-05 20:27:01 +00:00
igneum-labs
42904d11b6 Counter ASIC 2.0: the mixer x4 decision into v3, ca2-mixer agent, status 22:00 2026-10-05 20:27:01 +00:00
igneum-labs
b9bcc4bd8f Counter ASIC 2.0: layer 3 decided (scratch share 0, chip 2.4x at every share), the claim qualified, public level 3 headline 2026-10-05 20:27:01 +00:00
igneum-labs
789c10a353 Counter ASIC 2.0 status 21:35: the corrected SRAM mirror table 2026-10-05 20:27:01 +00:00
igneum-labs
8c191f2ef3 Counter ASIC 2.0 status 21:25: proving v1 state, PC 2 queue 2026-10-05 20:27:01 +00:00
igneum-labs
a42caa0035 Counter ASIC 2.0: the shipped-density correction to the SRAM mirror (130 to 165 mm^2), carried into the rollout and public docs 2026-10-05 20:27:01 +00:00
igneum-labs
544f898e15 Counter ASIC 2.0: layer 6 option C and layer 7 R1 decided (delegated), the chip headline rule for the scratch share 2026-10-05 20:27:01 +00:00
igneum-labs
a8626e75e6 Counter ASIC 2.0 status 20:55: layers 6 and 7, node agent, 0.3.11 scope with proving v1 2026-10-05 20:27:01 +00:00
igneum-labs
fca5934213 Counter ASIC 2.0 status: the four-level public description deliverable 2026-10-05 20:27:01 +00:00
igneum-labs
7d29dc3029 Counter ASIC: the public description in four levels (levels 1 and 2 as copy, 3 and 4 with owed markers) 2026-10-05 20:27:01 +00:00
igneum-labs
f707d34198 Counter ASIC 2.0 status 20:35: readwidth round 2, probe ceilings, width arithmetic 2026-10-05 20:27:01 +00:00
igneum-labs
a02efe383b Counter ASIC 2.0 status 20:25: 0.3.10 blocked on GitHub, node fork convention, 0.3.11 inputs 2026-10-05 20:27:01 +00:00