igneum-labs
21a689c1fc
Counter ASIC 4.0 research: --bench honours --variant through the pinned race (the SM-sparse run of 00:22 to 00:41 UTC served base on all 48 rows); RESULT carries variant, sparse_blocks and block_warps, variant_not_installed is the known-failed line; 20.3a records the run and its knee rows (v4 309.9 W, v3 219.4 W, premium 90.5 W at 1,300 MHz)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 98974a8ec
2026-10-08 12:28:17 +00:00
igneum-labs
838946e9ca
Counter ASIC 4.0 research: 20.2a-close, the per-load 16 x 27 construction dead as a chain class (1.4 percent acceptance, 42 of 64 seeds without a program), the sound form named, rank 4 marked
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 413d19686
2026-10-08 12:28:17 +00:00
igneum-labs
bca81a905c
Counter ASIC 4.0 research: 20.2a the per-load fault fixed with clock readings, the drawn-era census (0 pairs across 16 eras), the Metal fingerprints (the tile reference bit-exact; the Apple emulation costs 35 and 78 percent of rate at 1,024 and 4,096 tiles per hash); 20.2b the biased-product-bits requirement from adv-cache-2
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of a84c19649
2026-10-08 12:28:16 +00:00
igneum-labs
9c25ba8bf5
Counter ASIC 4.0 research: 20.2 the verifier rows (AVX2 tile path 0.047 us per tile per unit, mm1430 10.14 ms loaded; the per-load placement derives 11 percent fewer distinct items per warp: a uniformity fault as drawn, with its fix)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of f3885df2e
2026-10-08 12:28:16 +00:00
igneum-labs
c1849034e5
Counter ASIC 4.0 research: section 20, the two prototypes built (what, where, gates; the verifier and card rows pending)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of a9c16353a
2026-10-08 12:28:16 +00:00
igneum-labs
dba2c3f57e
Counter ASIC 4.0 research, second pass: the k-above-1 hunt, the capex lever and the re-ranked list
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Sections 15 to 19: every GPU block gaming and AI paid for, priced against the best public 4 to 5 nm chip figure with its k band, verifier cost and the edge at the measured premium (the one-sentence answer: nothing reads k above 1 with certainty; the int8 tensor tile is the only block near or above 1, so the tensor shadow with a SIMD byte-dot verifier is the new rank 3); the capex column added to the chip model (both sides capex-dominated at 7x to 10x their electricity; the per-unit capex wall unreachable by 3x to 7x; the project wall doubled from USD 100 M to about USD 200 M of break-even cap by the shadow-per-load design, the mission lane's method); the microbench of 20 probes documented as built (section 18); the owed list.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of ed83ae162
2026-10-08 12:28:16 +00:00
igneum-labs
94f6bc6eb4
Counter ASIC 4.0 research: clock stamps in UTC (the box compile at 20:48 UTC, the knee reading at 20:5x UTC)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 5fd67c216
2026-10-08 12:28:16 +00:00
igneum-labs
e239f05d19
Counter ASIC 4.0 research: the identity that forbids a zero-premium chip lever, the ranked designs, and the SM-sparse worker variant
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docs/analysis/counter-asic-4-research.md (excluded from the public export): edge = (E_card + F) / (E_mem + k F); at zero premium the stored-dataset chip keeps E_card / E_mem, 3.6x on a 5090 locked at 1,400 MHz (measured card, modelled chip), about 2x at that card's idle-plus-memory bound, 1.7x on the M5 Max; class v5 at zero shadow leaves it at 5.1x to 9.1x; the shadow buys 2.1x at k = 1 for the measured 88 W (81.8 W at the knee) and turns against us below 1.8 pJ per op; per-card classes, the refresh as a cost, proof of useful work, memory shaping and the tensor block priced out with their arithmetic; ten designs ranked with the chip edge, the 5090 and 4070 premiums, the verifier cost, agent hours and what breaks each; the recommendation in five sentences; consequences per tier.
proto-cuda/nvrtc/worker.cpp: opt-in SM-sparse variants sp<N> and sp<N>-w<W> (a persistent grid of N blocks of W warps over the dispatch's nonces; the bound kernel rewritten at compile time with exact anchors into a unit function plus a wrapper of the kernel's name; made on demand by name, never in the default race; refused on variant-5 packs and with minBlocks). Gate: mingw cross-compile on igneum-build-1 under lease pool (class measure, label "ca4 research"), exit 0 with -Wall -Wextra, 22:48 UTC; exe sha256 ee8d0e70dd101f125f42c0c7cf07481a794ee18a1317acf68561b37ea18d72be; unrun on a card (the hash lane's PC 1 job run-ca4-pc1-ca4sparse-5090-20261007 is its first run).
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of b18684240
2026-10-08 12:28:16 +00:00
igneum-labs
02bc398552
Merge ca3-coord-record e159dd28 into master (gate: green on e159dd28, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 12:13:44 +00:00
igneum-labs
72b33aaf84
Merge class-v6-family-gate bb52ac64 into master (gate: green on bb52ac64, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 12:12:39 +00:00
igneum-labs
e159dd28cc
Counter ASIC 3.0 status: Devnet 3 stalled at the class v5 floor at 12:48 BST (the fleet's workers without the kit's generator-5 worker; --exec-rpc) and crossed clean at 12:57:40, the pairing checked three ways, the worker-smoke gate rule; the pin's node sha 5f316c21 (the chain-id answer) every gate green; the research lane's section 10 and the two floor rows; kit b's 5090 rows (the x16 draw free on the GPU, the size term real at the knee); the 9070 XT row served ( 5fd703f6); the attack pass's census split; the deploys 9100269f, 5fd703f6
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 12:06:07 +00:00
igneum-labs
40be3175af
Merge master 5fd703f6 into wallet-bridge (master moved 24 commits during the landing's gate)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 11:59:16 +00:00
igneum-labs
6ca6bc657d
Merge ca3-coord-record 92b42379 into master (gate: green on 92b42379, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 11:53:54 +00:00
igneum-labs
92b42379dd
Standing rule (main's word, 8 October 2026, 12:5x UK): no kill by name on the Mac, pid file only, ad-hoc shell lines included; Counter ASIC 3.0 status: the node lane's named commit 42ce0f07 (four node fixes incl. the proof-map window, the OOM class behind the seed outage), the fleet census (36 on population A, 21 stale re-walking), the research lane's 2ae69eb4 (chip-model 5.12, the class v6 document through section 9), lane D's move to build-3 and its lossy-share curve, the F8-256 PASS, the hash lane's v6 packs rows and the byte-seed export lesson, the shipper's 12:33 line, the pkill class
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 11:46:11 +00:00
igneum-labs
ec10c06368
Merge remote-tracking branch 'build/master' into class-v6-invention
2026-10-08 11:46:02 +00:00
igneum-labs
680abc5cdb
Class v6 invention: the 5090 rows for the two per-load packs (the sound form costs the card 15 to 20 percent more per shadow instruction than the whole block, +19 W unlocked and +6.6 W at the knee at class v4's count; rank 1's GPU column corrected, the verdict restated with the honest sign)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 11:45:37 +00:00
igneum-labs
26053c9cd2
Merge ca3-coord-record bebb9670 into master (gate: green on bebb9670, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 11:45:12 +00:00
igneum-labs
c31df5f69b
Merge class-v6-invention da2a06e4 into master (gate: green on da2a06e4, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 11:44:26 +00:00
igneum-labs
16cf71cd41
Merge dex-devnet3 8ae41821 into master (gate: green on 8ae41821, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 11:43:52 +00:00
igneum-labs
112c16fccc
The wallet line's text under master's founder scrub: the name replaced in the README, updater.rs's comment, the three wallet plan documents and the capture script (the files predate the scrub; the facts stay)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 11:36:47 +00:00
igneum-labs
8ae4182101
Bridge: one Devnet 3 account balance proven on the Sepolia verifier (547.8077 IGN under the state root of Devnet 3 block 28,462, three-node eth_getProof from the reader node; eth_call true on the live contract, the suite 10 of 10 green on build-3); the vector committed
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 11:35:41 +00:00
igneum-labs
bb52ac640f
Class v6 family gate, the 17:00 cut: the harness as a plain diff at 3dc3117c (the founder-strings check refuses the patch form's author lines)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 11:35:25 +00:00
igneum-labs
da2a06e4b6
Merge remote-tracking branch 'build/master' into class-v6-invention
2026-10-08 11:35:21 +00:00
igneum-labs
958d49f498
Class v6 invention: the uniformity read at 2^20 on 64 seeds (the sound per-load forms clean, 0 over 1.2x and 0 sites under 0.995; the raw class v4 shape through the v2/v3 rule 41 of 64 hot at 7x to 36x, AP-F8-1's class as the harness's known-failed firing), the harness crate, the box OOM record, the offered window-bits test
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 11:35:11 +00:00
igneum-labs
7a1fb95cb5
Merge master into wallet-bridge (the wallet's line meets master for the landing of the page bridge)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
# Conflicts:
# packaging/ota/publish-manifest.sh
# site/index.html
# site/wallet.html
2026-10-08 11:33:30 +00:00
igneum-labs
bebb967029
Counter ASIC 3.0 status: the 3bb57640 deploy read back, the 0.3.25 pre-pin matrix green on four boxes, the 9070 XT grid on the AMD knob (run-ca3-pc1-amd-grid-9070-20261008-b: 149 W at 18.96 MH/s, both floors, the knob a watts lever only, the two 5090 denominators), the Arc default at 12:30 (pairing dba17a0a, kit 65b47211, Intel held out), the explorer deploys 43547048, 7dddf190 and af873d4b, the /build lane's close, lane D's 24,000-era coverage (61 of 5,000 at the lossy corner against 0 of 19,000), the node lane's missed 12:30 clock and the gate-priority lesson, main's census correction
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 11:30:51 +00:00
igneum-labs
a421b896f5
Class v6 family gate, the 17:00 cut: the last-resort rows corrected for class v5's verified scan (the finding at the corner is the correlation of one era's attempts, 1,000x the independent estimate, not an unchecked program); the harness patch series at 236ef3a5 (the lossy-share curve and the scan's verdict column)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 11:27:11 +00:00
igneum-labs
17a9bf682d
Class v6 family gate, the 17:00 cut: the measured coverage (24,000 drawn eras through the ring-B tests on build-1 and build-3, 54 core-hours), per stratum and per axis, with the bound arithmetic on the counts; four measured rows (the lossy corner of B = 4 exhausts the 256 cap in 1.2 percent of eras, the band capped at the lossy families; the (c''') floor's per-width calibration; the shape axis's draw cost; the era-stride bias at bit R in half the eras of every stratum); the census rows, logs, scripts and the harness patch series under logs/
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 11:25:26 +00:00
igneum-labs
af873d4bcb
Merge dex-devnet3 ac793c9e into master (gate: green on ac793c9e, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 11:17:02 +00:00
igneum-labs
ac793c9e43
Bridge: the first Devnet 3 checkpoint (index 2127) verified and recorded on the Sepolia verifier (tx 0x569a62c1, block 11869773); docs/contracts/sepolia.json
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 11:10:43 +00:00
igneum-labs
f839b75bd0
Merge dex-devnet3 096f5415 into master (gate: green on 096f5415, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 11:09:11 +00:00
igneum-labs
43547048be
Merge explorer-dn3 91b64b80 into master (gate: green on 91b64b80, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 11:05:43 +00:00
igneum-labs
096f54156b
Bridge: the verifier live on Sepolia at 0xAf74f3F512081291D663Bb1d6b6d37E99e37D744 with the Devnet 3 voter table (29 keys, 7,164 weight at index 2127; docs/contracts/sepolia.json), the Osaka test EVM, the account vector mode and the Devnet 3 account test (skips until the eth_getProof node serves)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 11:02:40 +00:00
igneum-labs
91b64b809a
Merge remote-tracking branch 'build/master' into explorer-dn3
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# Conflicts:
# site/build.mjs
2026-10-08 10:58:52 +00:00
igneum-labs
af22135f6e
Counter ASIC 3.0 status: the new gate on the pin (the reorg unwind), lane D's 12:00 coverage (the exhaustion break at the lossy corner; the bit-level era-stride class at half the family's epochs), the v6 cost rows, the drift class read from node1's log and its fix, main's words (the band, the fold, the served sentence corrected today, Apple split by size), the genesis gate answered on build-1 with the re-execution measured at 7 min 30 s, lane A's schedule flag and lane C's instrument finding (the per-load class reopened), the served corrections ( 0defaba7, 3bb57640), the 11:53 deploy, the four-box load line at 11:55
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 10:56:33 +00:00
igneum-labs
3bb57640e5
Merge spec-accept-23 6d0a52ea into master (gate: green on 6d0a52ea, recorded by tools/ci/pre-push.sh; landed on the box mirror)
2026-10-08 10:54:20 +00:00
igneum-labs
6d0a52ea03
Litepaper and evidence: the hash's reads stated as measured (8 October 2026, lane D's family harness at 2^20 over 4,900 drawn eras and adv-cache-2's reading): "dependent reads spread over a multi-gigabyte dataset" in the lead, the measured clause after the chain-of-random-reads sentence (the 0.995 floor on every accepted program; about half of epochs with one biased address bit at the era's stride rotation; about 1.6 percent of a hash's reads to a chip storing half the dataset, nothing to a full store; the fold in the next class), evidence row 18 with its sources; ledger AP-F8-7 (Open, priced), the public ledger and the ledger page regenerated. Bench table: class v4 watts rows 7 to 10 (RTX 3070 196.4 W under a 193 W cap, +28 percent; RTX 3070 Ti 267.6 W uncapped, +48 percent; RTX 4060 no watts on any rented host; the 3080 Ti's deep-capped pair in its note, the first cap that costs rate, the uncapped rate standing)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 10:48:11 +00:00
igneum-labs
68b624b82e
Merge class-v6-invention 5abdf181 into master (gate: green on 5abdf181, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 10:47:37 +00:00
igneum-labs
c49358ed94
Merge build-programme 8472843f into master (gate: green on 8472843f, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 10:46:53 +00:00
igneum-labs
59f82c6dbd
Bridge: docs/bridge/light-client-bridge.md (what the Sepolia verifier proves, the six things it does not, the path from here), the Devnet 3 table mode of the vector generator, the certificate-optional deploy script
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 10:45:56 +00:00
igneum-labs
0defaba741
Merge spec-accept-23 ba08d6b8 into master (gate: green on ba08d6b8, recorded by tools/ci/pre-push.sh; landed on the box mirror)
2026-10-08 10:45:43 +00:00
igneum-labs
1c02320532
Merge class-v6-history fd32fdc5 into master (gate: green on fd32fdc5, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 10:45:04 +00:00
igneum-labs
28effe9e2c
Merge class-v6-family-gate 8551379f into master (gate: green on 8551379f, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 10:40:09 +00:00
igneum-labs
5abdf18115
Merge build/master into class-v6-invention (the export-exclude line for docs/analysis/class-v6 kept once, the history lane's wording)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 10:40:05 +00:00
igneum-labs
e08b5d70a6
Merge ca3-coord-record cf521c46 into master (gate: green on cf521c46, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 10:39:26 +00:00
igneum-labs
8472843f8b
Merge build/master into build-programme: the swap page (dex-devnet3) joins the Build group in the nav, the footer, the sitemap and the nav check; /build links /swap
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 10:39:07 +00:00
igneum-labs
fd32fdc5ce
Class v6 history lane, revision 3: the dataset-floor schedule priced per tier and against the chips (section 4.2a, main's ask of 11:2x UK)
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docs/analysis/class-v6/history.md 4.2a: main's 6, 10 and 14 GiB steps checked against every tier's room under the standing 75 percent budget rule (the card-lifetime method, the bench table's 32 measured consumer cards as the population): 6 GiB does not fit the 8 GB tier under the rule (78 to 82 percent of the card; it fits only at a headless-rig reading of about 85 percent), 10 GiB retires the 10, 11 and 12 GB tiers and the Apple 16 GB laptop at year 2, 14 GiB retires the 16 GB tier at year 4, leaving 24 GB and above; beside it the schedule that drops the tiers in the order main named (5.5 GiB at the v6 epoch, 8 GiB at two years, 11 GiB at four) with the year each tier falls and its share of the measured cards (6 GB 3 percent at day one; 8 GB plus the 10 GB RTX 3080 plus Apple 16 GB 25 percent at year 2; 12 GB 22 percent at year 4; 16 GB 28 percent at the 16 GiB step; 24 GB and above hold). Against the chips: the hybrid-bonded or soldered chip sized at launch dies at the first step it cannot carry (the E3's shape, 20 to 27 months) but a maker reading a public consensus field sizes to the step it wants (USD 160 more of GDDR7 on a USD 470 part; about 3x the memory die area for the Jasminer shape); the f = 1 GDDR7 chip's 32 GB board pays USD 0 through 16 GiB and keeps 5.1x; the SRAM store pays capex only at the cache doubling (USD 46 to 111 per die) and keeps 0.92x and 1.86x. The fleet's hashrate-weighted card census is owed. The arithmetic is checked by script against the card-lifetime working sets.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 10:38:53 +00:00
igneum-labs
d5c4b90d23
Merge class-v6-history 697fdd23 into master (gate: green on 697fdd23, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 10:35:30 +00:00
igneum-labs
cb70a8fa60
Merge remote-tracking branch 'build/master' into explorer-dn3
2026-10-08 10:34:09 +00:00
igneum-labs
cf521c467d
Counter ASIC 3.0 status: the whole 60x file (six keys) landed on both lines, the index fold as a class v6 design row, class v5 level with v4 at the 5090's knee (the knee stands, the note off, the A4000's loss a cap effect), lane B's SRAM-store and HBM4E readings and main's three orders on them, the shipper's three readings and the cut tip edf77203, lane A's cut and verdict (the stored-dataset chip closed by no layer; the floor and a per-tier ceiling the numbers) with main's schedule to price, the snapshot digest stamp and the genesis difference as a gate on the pin, main's words
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 10:32:55 +00:00
