Merge box/master 19c945915 into amd-intel-energy-registry-docs (rule 26: master's map, page and registry taken; the lane's cells bench:amd-intel-energy re-added; batches re-recorded)
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igneum-labs
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3 changed files with 59 additions and 16 deletions
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@ -334,6 +334,14 @@ Rule: a case maps to a cell only where the cell's tests visibly answer it; cover
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- ROT-07 Ablate redundant rotation layers: partial: the acceptance-side ablation rows (layer 8 off against the same-crate windowed control: the draw cost, the floors' costs, the hot-set and 1.2x ceiling, the bit-R read; the mixer and shape axes' per-era invisibility and verifier rows), docs/analysis/class-v6/family-gate.md sections 6.4 to 6.12; the adversarial cost and the GPU setup rows per layer are the hash lane's and the adversary lane's
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- ROT-08 Pass the no-new-rules counterfactual: partial: the no-rescue control document (38,000 drawn eras of the parameter family through the acceptance, the bound arithmetic on the counts, the honest line of what the gate cannot see), family-gate.md sections 1 to 6; the competitiveness envelope and the economic half are ECO's
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### bench:amd-intel-energy
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- Command: `the AMD-and-Intel energy lane jobs on the signed-jobs channel: run-ae-pc2-b580-energy-20261008 (PC 2, Arc B580, the class v6 kit worker --memprobe and --bench-pack on hl-v6-foldrw and hl-v6-all, Level Zero energy counter) and run-ae-pc1-7600-energy-20261008 (PC 1, RX 7600, the same with ADLX watts at stock, plimit -30, gmax -500 + plimit -30); scripts in docs/analysis/class-v6/amd-intel-energy/`
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- Box class: PC 1 and PC 2 bench (OpenCL)
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- Fixtures: F0, F1
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- Cases:
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- GPU-03 Measure the real 64-register GPU cost: partial: the 64-register window on AMD and Intel, rate per unit of work (RX 7600 0 percent, Arc B580 -0.3 percent, kernel throughput, quiet) with the B580 fingerprints equal on both packs and the offline RDNA allocation (160 VGPRs, no spill); energy owed (the 7600 job queued, the B580 counter unsupported unelevated); team-run, not under the standard's paired protocol or a wall meter
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## Automated cases with no harness in the matrix (NOT RUN, the reason)
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- GOV-02 Approve thresholds before results: the approval is recorded in the registry's approval field; the automated half (thresholds frozen before any run_status) is the gate rule landing by 21:00
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@ -823,31 +823,30 @@
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"manual_page": 21,
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"owner_lane": "hash lane (a690540514aa453d7)",
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"run_status": "NOT RUN",
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"evidence_path": "docs/analysis/class-v6/rows/fleet-f05-20261008.md",
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"run_id": "hash-lane-20261008-batch2",
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"updated": "2026-10-08T19:59:34.316Z",
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"evidence_path": "docs/analysis/class-v6/rows/fleet-f05-20261008.md; docs/analysis/class-v6/amd-intel-energy.md",
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"run_id": "amd-intel-energy-20261008-01",
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"updated": "2026-10-08T20:12:15.165Z",
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"evidence_record": {
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"cell": "bench:fleet-pods",
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"manifest_sha": "b24dfc162",
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"coverage": {
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"GPU-01": "partial: the NVIDIA cells of P02 that RunPod carries",
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"GPU-03": "partial: the 4090 cell",
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"POW-08": "partial: W = 16 on four cards"
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},
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"at": "2026-10-08T19:59:34.316Z",
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"method": "GPU",
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"requirement_id": "GPU-03",
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"decision": "NOT RUN",
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"reviewer": "",
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"claim_impact": "",
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"method": "GPU",
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"cell": "bench:amd-intel-energy",
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"manifest_sha": "c245d50b9",
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"run_id": "amd-intel-energy-20261008-01",
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"evidence": "docs/analysis/class-v6/amd-intel-energy.md",
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"in_progress": false,
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"coverage": "partial: the 64-register window on AMD and Intel, rate per unit of work (RX 7600 0 percent, Arc B580 -0.3 percent, kernel throughput, quiet) with the B580 fingerprints equal on both packs and the offline RDNA allocation (160 VGPRs, no spill); energy owed (the 7600 job queued, the B580 counter unsupported unelevated); team-run, not under the standard's paired protocol or a wall meter",
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"release_identity": {
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"commit": "b24dfc162",
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"commit": "c245d50b9",
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"lockfile": "",
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"binary": "",
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"network_object": "",
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"activation": "",
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"profile_hashes": ""
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}
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},
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"claim_impact": "",
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"reviewer": "",
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"at": "2026-10-08T20:12:15.165Z"
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},
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"in_progress_since": "2026-10-08T19:59:34.316Z",
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"approvals": {
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@ -882,6 +881,28 @@
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"run_id": "hash-lane-20261008-batch2",
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"evidence": "docs/analysis/class-v6/rows/fleet-f05-20261008.md",
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"in_progress": true
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},
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"bench:amd-intel-energy": {
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"requirement_id": "GPU-03",
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"decision": "NOT RUN",
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"method": "GPU",
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"cell": "bench:amd-intel-energy",
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"manifest_sha": "c245d50b9",
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"run_id": "amd-intel-energy-20261008-01",
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"evidence": "docs/analysis/class-v6/amd-intel-energy.md",
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"in_progress": false,
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"coverage": "partial: the 64-register window on AMD and Intel, rate per unit of work (RX 7600 0 percent, Arc B580 -0.3 percent, kernel throughput, quiet) with the B580 fingerprints equal on both packs and the offline RDNA allocation (160 VGPRs, no spill); energy owed (the 7600 job queued, the B580 counter unsupported unelevated); team-run, not under the standard's paired protocol or a wall meter",
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"release_identity": {
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"commit": "c245d50b9",
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"lockfile": "",
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"binary": "",
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"network_object": "",
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"activation": "",
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"profile_hashes": ""
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},
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"claim_impact": "",
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"reviewer": "",
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"at": "2026-10-08T20:12:15.165Z"
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}
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}
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},
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@ -574,6 +574,20 @@
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"ROT-07": "partial: the acceptance-side ablation rows (layer 8 off against the same-crate windowed control: the draw cost, the floors' costs, the hot-set and 1.2x ceiling, the bit-R read; the mixer and shape axes' per-era invisibility and verifier rows), docs/analysis/class-v6/family-gate.md sections 6.4 to 6.12; the adversarial cost and the GPU setup rows per layer are the hash lane's and the adversary lane's",
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"ROT-08": "partial: the no-rescue control document (38,000 drawn eras of the parameter family through the acceptance, the bound arithmetic on the counts, the honest line of what the gate cannot see), family-gate.md sections 1 to 6; the competitiveness envelope and the economic half are ECO's"
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}
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},
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"bench:amd-intel-energy": {
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"command": "the AMD-and-Intel energy lane jobs on the signed-jobs channel: run-ae-pc2-b580-energy-20261008 (PC 2, Arc B580, the class v6 kit worker --memprobe and --bench-pack on hl-v6-foldrw and hl-v6-all, Level Zero energy counter) and run-ae-pc1-7600-energy-20261008 (PC 1, RX 7600, the same with ADLX watts at stock, plimit -30, gmax -500 + plimit -30); scripts in docs/analysis/class-v6/amd-intel-energy/",
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"box_class": "PC 1 and PC 2 bench (OpenCL)",
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"fixtures": [
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"F0",
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"F1"
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],
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"cases": [
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"GPU-03"
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],
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"coverage": {
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"GPU-03": "partial: the 64-register window on AMD and Intel, rate per unit of work (RX 7600 0 percent, Arc B580 -0.3 percent, kernel throughput, quiet) with the B580 fingerprints equal on both packs and the offline RDNA allocation (160 VGPRs, no spill); energy owed (the 7600 job queued, the B580 counter unsupported unelevated); team-run, not under the standard's paired protocol or a wall meter"
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}
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}
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},
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"not_run": {
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