From 8651f9bf23f2a663abc0b63f6fab2713476bdc32 Mon Sep 17 00:00:00 2001 From: igneum-labs <337424239+igneum-labs@users.noreply.github.com> Date: Thu, 8 Oct 2026 20:12:15 +0000 Subject: [PATCH] Merge box/master 19c945915 into amd-intel-energy-registry-docs (rule 26: master's map, page and registry taken; the lane's cells bench:amd-intel-energy re-added; batches re-recorded) --- docs/plans/igneum-2.0-test-harness-map.md | 8 ++++ docs/plans/igneum-2.0-test-registry.json | 53 ++++++++++++++++------- tools/ci/test-map.json | 14 ++++++ 3 files changed, 59 insertions(+), 16 deletions(-) diff --git a/docs/plans/igneum-2.0-test-harness-map.md b/docs/plans/igneum-2.0-test-harness-map.md index 9d458437d..6bacb2699 100644 --- a/docs/plans/igneum-2.0-test-harness-map.md +++ b/docs/plans/igneum-2.0-test-harness-map.md @@ -334,6 +334,14 @@ Rule: a case maps to a cell only where the cell's tests visibly answer it; cover - ROT-07 Ablate redundant rotation layers: partial: the acceptance-side ablation rows (layer 8 off against the same-crate windowed control: the draw cost, the floors' costs, the hot-set and 1.2x ceiling, the bit-R read; the mixer and shape axes' per-era invisibility and verifier rows), docs/analysis/class-v6/family-gate.md sections 6.4 to 6.12; the adversarial cost and the GPU setup rows per layer are the hash lane's and the adversary lane's - ROT-08 Pass the no-new-rules counterfactual: partial: the no-rescue control document (38,000 drawn eras of the parameter family through the acceptance, the bound arithmetic on the counts, the honest line of what the gate cannot see), family-gate.md sections 1 to 6; the competitiveness envelope and the economic half are ECO's +### bench:amd-intel-energy + +- Command: `the AMD-and-Intel energy lane jobs on the signed-jobs channel: run-ae-pc2-b580-energy-20261008 (PC 2, Arc B580, the class v6 kit worker --memprobe and --bench-pack on hl-v6-foldrw and hl-v6-all, Level Zero energy counter) and run-ae-pc1-7600-energy-20261008 (PC 1, RX 7600, the same with ADLX watts at stock, plimit -30, gmax -500 + plimit -30); scripts in docs/analysis/class-v6/amd-intel-energy/` +- Box class: PC 1 and PC 2 bench (OpenCL) +- Fixtures: F0, F1 +- Cases: + - GPU-03 Measure the real 64-register GPU cost: partial: the 64-register window on AMD and Intel, rate per unit of work (RX 7600 0 percent, Arc B580 -0.3 percent, kernel throughput, quiet) with the B580 fingerprints equal on both packs and the offline RDNA allocation (160 VGPRs, no spill); energy owed (the 7600 job queued, the B580 counter unsupported unelevated); team-run, not under the standard's paired protocol or a wall meter + ## Automated cases with no harness in the matrix (NOT RUN, the reason) - GOV-02 Approve thresholds before results: the approval is recorded in the registry's approval field; the automated half (thresholds frozen before any run_status) is the gate rule landing by 21:00 diff --git a/docs/plans/igneum-2.0-test-registry.json b/docs/plans/igneum-2.0-test-registry.json index 1b8c5c561..5114d40c4 100644 --- a/docs/plans/igneum-2.0-test-registry.json +++ b/docs/plans/igneum-2.0-test-registry.json @@ -823,31 +823,30 @@ "manual_page": 21, "owner_lane": "hash lane (a690540514aa453d7)", "run_status": "NOT RUN", - "evidence_path": "docs/analysis/class-v6/rows/fleet-f05-20261008.md", - "run_id": "hash-lane-20261008-batch2", - "updated": "2026-10-08T19:59:34.316Z", + "evidence_path": "docs/analysis/class-v6/rows/fleet-f05-20261008.md; docs/analysis/class-v6/amd-intel-energy.md", + "run_id": "amd-intel-energy-20261008-01", + "updated": "2026-10-08T20:12:15.165Z", "evidence_record": { - "cell": "bench:fleet-pods", - "manifest_sha": "b24dfc162", - "coverage": { - "GPU-01": "partial: the NVIDIA cells of P02 that RunPod carries", - "GPU-03": "partial: the 4090 cell", - "POW-08": "partial: W = 16 on four cards" - }, - "at": "2026-10-08T19:59:34.316Z", - "method": "GPU", "requirement_id": "GPU-03", "decision": "NOT RUN", - "reviewer": "", - "claim_impact": "", + "method": "GPU", + "cell": "bench:amd-intel-energy", + "manifest_sha": "c245d50b9", + "run_id": "amd-intel-energy-20261008-01", + "evidence": "docs/analysis/class-v6/amd-intel-energy.md", + "in_progress": false, + "coverage": "partial: the 64-register window on AMD and Intel, rate per unit of work (RX 7600 0 percent, Arc B580 -0.3 percent, kernel throughput, quiet) with the B580 fingerprints equal on both packs and the offline RDNA allocation (160 VGPRs, no spill); energy owed (the 7600 job queued, the B580 counter unsupported unelevated); team-run, not under the standard's paired protocol or a wall meter", "release_identity": { - "commit": "b24dfc162", + "commit": "c245d50b9", "lockfile": "", "binary": "", "network_object": "", "activation": "", "profile_hashes": "" - } + }, + "claim_impact": "", + "reviewer": "", + "at": "2026-10-08T20:12:15.165Z" }, "in_progress_since": "2026-10-08T19:59:34.316Z", "approvals": { @@ -882,6 +881,28 @@ "run_id": "hash-lane-20261008-batch2", "evidence": "docs/analysis/class-v6/rows/fleet-f05-20261008.md", "in_progress": true + }, + "bench:amd-intel-energy": { + "requirement_id": "GPU-03", + "decision": "NOT RUN", + "method": "GPU", + "cell": "bench:amd-intel-energy", + "manifest_sha": "c245d50b9", + "run_id": "amd-intel-energy-20261008-01", + "evidence": "docs/analysis/class-v6/amd-intel-energy.md", + "in_progress": false, + "coverage": "partial: the 64-register window on AMD and Intel, rate per unit of work (RX 7600 0 percent, Arc B580 -0.3 percent, kernel throughput, quiet) with the B580 fingerprints equal on both packs and the offline RDNA allocation (160 VGPRs, no spill); energy owed (the 7600 job queued, the B580 counter unsupported unelevated); team-run, not under the standard's paired protocol or a wall meter", + "release_identity": { + "commit": "c245d50b9", + "lockfile": "", + "binary": "", + "network_object": "", + "activation": "", + "profile_hashes": "" + }, + "claim_impact": "", + "reviewer": "", + "at": "2026-10-08T20:12:15.165Z" } } }, diff --git a/tools/ci/test-map.json b/tools/ci/test-map.json index 12aa26ce5..ef7fa6c3c 100644 --- a/tools/ci/test-map.json +++ b/tools/ci/test-map.json @@ -574,6 +574,20 @@ "ROT-07": "partial: the acceptance-side ablation rows (layer 8 off against the same-crate windowed control: the draw cost, the floors' costs, the hot-set and 1.2x ceiling, the bit-R read; the mixer and shape axes' per-era invisibility and verifier rows), docs/analysis/class-v6/family-gate.md sections 6.4 to 6.12; the adversarial cost and the GPU setup rows per layer are the hash lane's and the adversary lane's", "ROT-08": "partial: the no-rescue control document (38,000 drawn eras of the parameter family through the acceptance, the bound arithmetic on the counts, the honest line of what the gate cannot see), family-gate.md sections 1 to 6; the competitiveness envelope and the economic half are ECO's" } + }, + "bench:amd-intel-energy": { + "command": "the AMD-and-Intel energy lane jobs on the signed-jobs channel: run-ae-pc2-b580-energy-20261008 (PC 2, Arc B580, the class v6 kit worker --memprobe and --bench-pack on hl-v6-foldrw and hl-v6-all, Level Zero energy counter) and run-ae-pc1-7600-energy-20261008 (PC 1, RX 7600, the same with ADLX watts at stock, plimit -30, gmax -500 + plimit -30); scripts in docs/analysis/class-v6/amd-intel-energy/", + "box_class": "PC 1 and PC 2 bench (OpenCL)", + "fixtures": [ + "F0", + "F1" + ], + "cases": [ + "GPU-03" + ], + "coverage": { + "GPU-03": "partial: the 64-register window on AMD and Intel, rate per unit of work (RX 7600 0 percent, Arc B580 -0.3 percent, kernel throughput, quiet) with the B580 fingerprints equal on both packs and the offline RDNA allocation (160 VGPRs, no spill); energy owed (the 7600 job queued, the B580 counter unsupported unelevated); team-run, not under the standard's paired protocol or a wall meter" + } } }, "not_run": {