diff --git a/docs/evidence.md b/docs/evidence.md index 87fd81eda..9a3cdd4c2 100644 --- a/docs/evidence.md +++ b/docs/evidence.md @@ -41,7 +41,7 @@ Versions in the table: `igneum-pow` is the Rust crate at `igneum-pow/Cargo.toml` | 14 | Ethereum bytecode runs unchanged, with the documented differences of spec 7.1 | Homepage Build card; litepaper Building | tested by the team | as row 13; fixes `F-exec-A`, `F-exec-B` (spec 7.5) | `tools/evm-smoke/smoke.mjs`: deploy via viem, `increment`, `hashLoop`, `eth_estimateGas`, `eth_getLogs`; `tools/exec-attacks` scenarios 1 and 3; bench-log "execution layer attack fixes" | Deployment, calls, reverts, logs and gas estimates behave as viem expects; chain id 4463; the prototype pgas table gives 0.0095 to 0.028 pgas per gas, below the design's band before calibration, 3 October 2026. 4 October 2026: a transaction that would cross the block's proving budget is refused by the mempool and, if forced in, aborted and charged with its nonce advanced (25 of 25 checks; 30 of 30 malformed cases). Apple M5 Max. The `Prover` precompile, proof records and the shard planner are not in the node | none yet | | 15 | Every block is proven, with the proof landing within about a minute at launch | Homepage stats ("~60 s to a proof"); litepaper Proving; roadmap phase 3 gate | implemented | repo `d7e1f89` (GPU proof), `e01a3cc`, `292e800`, `eedd136` (`proving/igneum-prove`: shard cutter, MPT witnesses, shard and aggregator guests); SP1 6.8.1; spec 7.2, 7.6 | `proving/windows-wsl2` (SETUP-PROVER, PROVE-BLOCK) on the RTX 5090; `igneum-prove-host --mode block` on `proving/fixtures/`; bench-log "proving v0 on the RTX 5090" and "proving: devnet v4 shards" | First GPU proof of an Igneum block, 4 October 2026, RTX 5090 (WSL2, SP1 cuda, mining paused): fixture `block-78-increment` (2 transactions), core proof 1.4 s (7.3 MB, verify 0.221 s), compressed proof 2.7 s (1.27 MB, verify 0.038 s), post-state and receipts roots identical to the node's; 15.7x and 20.6x faster than a loaded M5 Max CPU. The same day on that CPU (load 38 to 47): a three-shard block proved shard by shard and aggregated by recursion, 19 min (1,139 s) end to end, 245 to 337 s per compressed shard proof, every proof verified. What is not there: no proof is produced, carried or checked on the chain (the devnet prover is a stub that signs claims), the proving pool pays nobody (row 21), the block proven is far below one shard, and the 60-second figure remains a design target; the pass mark is the standard in `docs/benchmarks/proving-e2e.md`. Second RTX 5090 run, 4 October 2026 evening (job run-20261004-173115): a full shard at the provisional S_p (6.75 M pgas, 60.8 M cycles) executed in 1.63 s, core proof 8.3 s (18.1 MB), compressed proof 10.9 s (1.27 MB, verify 0.040 s); a two-shard block (13.5 M pgas) proved shard by shard (11.7 s and 10.0 s) and aggregated in 2.2 s, 24 s of GPU stages end to end, every proof verified, six tampered witnesses rejected. The two host defects (an abort after the upload, an idle wait that turned out to be an unbuffered 18 MB proof save through the WSL2 file bridge, 24 minutes) are fixed (ledger P20) 5 October 2026, live devnet with real transactions (bench-log "real transactions, the first non-empty shard proven and paid"): block 72704 shard 0, 29 transfers, 5,800 pgas, proven on PC 2 in 34 s, verified on the Mac in 0.297 s and paid 1.7623 IGN, 53 s after the chain block executed; of about 1,400 blocks in the 20-minute window 36 were proven (the one prover takes the newest shard assigned to it), so "every block" is not yet true; a second content shard (72803, all copies skipped) failed the native-execution veto on the exporter's block structure, fixed with fixtures the same day, the node side pending the 0.3.9 rollout 5 October 2026, evening (bench-log "proving v1"): the aggregated segment record, the chain rule and the unproven rule are implemented behind `proving_v1_activation_daa` (branch proving-v1, not on the devnet before 0.3.11); on the RTX 5090 a chain of 8 consecutive live blocks proved and aggregated by recursion in 135.6 s with the miner on the card (17 s a block, one proof of 1,272,909 bytes attesting all 8, verified in 0.04 s); the 3-node fast-time harness paid a segment record 1.0 s after submission and refused a late one after its deadline (21 checks); the devnet itself, with one prover, carried proofs for 2.4% of blocks over 30 minutes at a block-to-record latency p50 44 s, p99 52 s. The "within about a minute" holds per proven block; "every block" needs 18 mining 5090s or 6 proving-only cards at empty blocks on the measured rates, and the mandatory rule stays off until the share is one | none yet | | 16 | A 12 GB card proves one shard in about 20 s (WITHDRAWN 5 October 2026: a 24 GB card proves a full shard at the adopted size in 4.3 s; 32 GB mines and proves) | Litepaper Proving ("The proving budget"); roadmap gate 2 | designed | spec 5.1 (Target), 7.6 (`S_p` provisional, 7,500,000 pgas = `B_p` / 4) | `PROVE-SHARD.bat` on the RTX 5090 (pending); the end-to-end standard in `docs/benchmarks/proving-e2e.md`; bench-log "proving: devnet v4 shards" | Measured on a 32 GB card, not yet on a 12 GB card. A shard at the provisional `S_p` is 60.8 M SP1 cycles on the prototype pgas table (9 cycles per pgas, 44 per EVM gas; the modexp entry about 100x its SP1 cost); on an RTX 5090 (4 October 2026 evening, job run-20261004-173115) it executed in 1.63 s and its compressed proof took 10.9 s, verified in 0.040 s, so the 32 GB card is inside the 20 s target with margin. Whether a 12 GB card proves it at all, and in what time, is the next measurement (an RTX 3060 and an RTX 5060 Ti 16 GB are on order). A per-shard time can be met by shrinking the shard, so the project does not use it as a pass mark 5 October 2026, evening (bench-log "proving v1", the S_p curve): measured on the RTX 5090 with SP1 6.8.1's GPU prover, the card to itself, 1-s nvidia-smi samples: an empty shard 13,874 MiB and 2.2 s; a full shard at the ADOPTED v1 budget (30,000 pgas, 4.7 M cycles) 20,434 MiB and 4.3 s; the full prototype shard (6.75 M pgas, 60 M cycles) 28,307 MiB and 10.8 s; beside the miner 15,670 and 30,039 MiB. No environment knob of SP1 moves the 13.9 GB floor and the GPU server has no options of its own, so on this build a 12 GB card proves nothing, a 16 GB card only empty shards, a 24 GB card the adopted full shard alone and beside the miner (22,210 MiB and 13.2 s, measured on the 32 GB card: the 5090's allocation pattern, not yet a run on a 24 GB card) and a 32 GB card the prototype shard beside the miner with 2.5 GB spare. The litepaper line now says so; the 12 GB gate returns when a prover build with a smaller floor is measured on a 12 GB card | none yet | -| 17 | The chip resistance claim, served as the class v6 close words it: Class v6 retains the 64-register window. Current modelling estimates a 2.2x to 2.4x energy-efficiency advantage for the strongest specialised designs assessed against the GPU tier (2.0x on the GPU's own node). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment. Beside it: class v4 is live from the first block on the testnet and the mainnet; class v5 makes the dataset the chain's state so a stateless or stale chip is wrong on every item; the hot-set cache is bounded at 1.067x at the ceiling and the weak-day FPGA at 12 percent on 15 days a century, both routed to the next class; datacentre silicon does not change the question; the three statements (energy resistance, economic resistance, response capability) are served separate, with the harness and the scoring rule linked | the home page's chip line, the litepaper's chip section (/litepaper#chip-model), the miner page's line | the GPU side tested by the team (the RTX 5080 and RTX 5090 clock-lock passes under class v4, every card, the verifier, the two attack-pass bounds, the H100); the chip core synthesised on ASAP7 and scaled to N3, claimed; the chip's memory modelled; the node column claimed scaling; the economic surface modelled, first cut, conditional; the rotation schedule measured per boundary; class v5 designed; the Antminer X5 an observed comparison, not a ceiling; the X9 a withdrawn pre-order, never benchmarked | `docs/design/class-v6-rotating-family.md` section 10 (10.0 to 10.0h, the close and its two accepted external reviews, 8 October 2026); `docs/design/class-v5-stored-state.md` sections 0, 13 and 14 and `docs/design/class-v5-harness/` (branch class-v5); `docs/design/class-rotation-four-layers.md`; `docs/analysis/chip-model-v3.md` 5 and 6; `docs/analysis/latency-shadow-2026-10-06.md`; `docs/analysis/attack-pass/f8-uniform.md`, `f4-weakday.md`, `docs/analysis/ca3-v4-uniform.md`; the H100 row of 7 October; `docs/plans/cryptanalysis/in-house-pass.md` (the internal adversarial pass) | the scoring rule in the close (the minimum over workloads of the maximum over free adversarial designs of the GPU's joules per hash over the adversary's, under the 10 percent GPU-cost budget at the lock, the verifier limit, cross-vendor correctness and hardware accessibility); the card rows by the benchmark package; the class v5 harness and the family harness; the attack-pass harnesses `tools/attack/f8-uniform` and the F4 census; the verifier by `igneum-pow bench` | 136 MH/s at 350 W (5090, bench) and 290 W (app); the class v4 efficiency passes (bench log "7 to 8 October 2026, the class v4 efficiency passes: the core clock lock on the RTX 5090 and the RTX 5080", measured): the 5090 at 136.84 MH/s and 475.5 W unlocked, 134.98 at 316.3 W at a 1,400 MHz core lock, the best points class v4 at 1,200 MHz (133.80 MH/s, 305.1 W, 0.439 MH/W) and class v3 at 1,300 MHz (134.62, 223.3 W, 0.603), the premium 145 W unlocked and 82 W at the best points, the knee 1,300 MHz; the RTX 5080 (8 October 2026, the dock card of the three-card Windows rig) at 71.41 MH/s and 253.1 W unlocked under class v4 against 71.28 at 169.7 W under class v3, the best points class v4 at 1,100 MHz (71.20 MH/s, 146.6 W, 0.486 MH/W) and class v3 at 1,000 MHz (71.11, 103.7 W, 0.686), the premium 83.4 W unlocked and 41 W at the best points, the knee between 1,000 and 900 MHz; per tier: a 5080 owner on class v4 locked near 1,100 MHz pays 147 W instead of 253 for 0.3 percent less rate, MH per watt up 72 percent, the lever Ember Tune's core-clock knob in 0.3.24; 27 MH/s at 21 W (M5 Max); 249 MH/s (H100 SXM) at 98 percent of its read ceiling, 1.78x hash, 1.15x MH/W, a third per rented dollar; 2.33 ms per warp; the GPU side of the close: the RTX 5080 at its 1,100 MHz lock 2.06 microjoules per hash and the RTX 5090 at its 1,300 MHz lock 2.33 (class v4, 8 October 2026); the modelled edge 2.2x to 2.4x a node ahead, 2.0x node for node (k 1.09), 2.8x two nodes ahead on the synthesised 8-lane core; the 32-lane rows pending (about 2.4x to 2.6x a node ahead, 2.0x to 2.2x node for node); the shadow's premium on a 5090 81.8 W at its knee (class v4 at the 1,200 MHz lock 133.80 MH/s at 305.1 W; class v3 at 1,300 MHz 134.62 at 223.3 W; 7 October 2026); 1.067x at the ceiling; 12 percent on 15 days a century; 10.85 ms at rung 3; 6 to 8 October 2026, the M5 Max, the desk rigs' RTX 5090, RTX 5080, RX 9070 XT and RTX 4070, rented pods, a rented H100 SXM, igneum-build-1 Bitmain's Antminer X9 (RandomX; 1,000 KH/s, 2,472 W, 2.47 J per KH, USD 5,600; pre-orders 26 December 2025) was withdrawn in mid-May 2026 with buyers refunded before any unit shipped, no independent benchmark, commodity Sophgo SG2044 server SoCs with an AES accelerator, no tapeout: it is a precedent on the served pages, not a chip core against the model (attack pass AP-F5-1, 7 October 2026; the close's 10.0f, 8 October 2026). Withdrawn from the served pages on 8 October 2026 and not restated: the 2.1x and 3.4x launch line, the 5x to 9x class v3 baseline, the ladder's 2.8x row, the USD 100 M pay-back row, any chip-arrival probability, the lifetime claim and the USD 300 M and 340 M lines. | none yet; the next test is the internal adversarial pass (three lanes new to the hash code, outsider inputs only, reports published whole), whose floor reading is in (measured, 8 October 2026; ledger AP-F8-1 and AP-F8-6): nine of nine hot sets refused; the diffuse era-stride excess, bounded under 0.1 percent of a hash's reads per site, is not caught by the floor and is the next class's test, and no outside review has run yet | +| 17 | The chip resistance claim, served as the class v6 close words it: Class v6 adopts the 64-register window and retains it across every rotation. Current modelling estimates a 2.2x to 2.4x energy-efficiency advantage for the strongest specialised designs assessed against the GPU tier (2.0x on the GPU's own node). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment. Beside it: class v4 is live from the first block on the testnet and the mainnet; class v5 makes the dataset the chain's state so a stateless or stale chip is wrong on every item; the hot-set cache is bounded at 1.067x at the ceiling and the weak-day FPGA at 12 percent on 15 days a century, both routed to the next class; datacentre silicon does not change the question; the three statements (energy resistance, economic resistance, response capability) are served separate, with the harness and the scoring rule linked | the home page's chip line, the litepaper's chip section (/litepaper#chip-model), the miner page's line | the GPU side tested by the team (the RTX 5080 and RTX 5090 clock-lock passes under class v4, every card, the verifier, the two attack-pass bounds, the H100); the chip core synthesised on ASAP7 and scaled to N3, claimed; the chip's memory modelled; the node column claimed scaling; the economic surface modelled, first cut, conditional; the rotation schedule measured per boundary; class v5 designed; the Antminer X5 an observed comparison, not a ceiling; the X9 a withdrawn pre-order, never benchmarked | `docs/design/class-v6-rotating-family.md` section 10 (10.0 to 10.0h, the close and its two accepted external reviews, 8 October 2026); `docs/design/class-v5-stored-state.md` sections 0, 13 and 14 and `docs/design/class-v5-harness/` (branch class-v5); `docs/design/class-rotation-four-layers.md`; `docs/analysis/chip-model-v3.md` 5 and 6; `docs/analysis/latency-shadow-2026-10-06.md`; `docs/analysis/attack-pass/f8-uniform.md`, `f4-weakday.md`, `docs/analysis/ca3-v4-uniform.md`; the H100 row of 7 October; `docs/plans/cryptanalysis/in-house-pass.md` (the internal adversarial pass) | the scoring rule in the close (the minimum over workloads of the maximum over free adversarial designs of the GPU's joules per hash over the adversary's, under the 10 percent GPU-cost budget at the lock, the verifier limit, cross-vendor correctness and hardware accessibility); the card rows by the benchmark package; the class v5 harness and the family harness; the attack-pass harnesses `tools/attack/f8-uniform` and the F4 census; the verifier by `igneum-pow bench` | 136 MH/s at 350 W (5090, bench) and 290 W (app); the class v4 efficiency passes (bench log "7 to 8 October 2026, the class v4 efficiency passes: the core clock lock on the RTX 5090 and the RTX 5080", measured): the 5090 at 136.84 MH/s and 475.5 W unlocked, 134.98 at 316.3 W at a 1,400 MHz core lock, the best points class v4 at 1,200 MHz (133.80 MH/s, 305.1 W, 0.439 MH/W) and class v3 at 1,300 MHz (134.62, 223.3 W, 0.603), the premium 145 W unlocked and 82 W at the best points, the knee 1,300 MHz; the RTX 5080 (8 October 2026, the dock card of the three-card Windows rig) at 71.41 MH/s and 253.1 W unlocked under class v4 against 71.28 at 169.7 W under class v3, the best points class v4 at 1,100 MHz (71.20 MH/s, 146.6 W, 0.486 MH/W) and class v3 at 1,000 MHz (71.11, 103.7 W, 0.686), the premium 83.4 W unlocked and 41 W at the best points, the knee between 1,000 and 900 MHz; per tier: a 5080 owner on class v4 locked near 1,100 MHz pays 147 W instead of 253 for 0.3 percent less rate, MH per watt up 72 percent, the lever Ember Tune's core-clock knob in 0.3.24; 27 MH/s at 21 W (M5 Max); 249 MH/s (H100 SXM) at 98 percent of its read ceiling, 1.78x hash, 1.15x MH/W, a third per rented dollar; 2.33 ms per warp; the GPU side of the close: the RTX 5080 at its 1,100 MHz lock 2.06 microjoules per hash and the RTX 5090 at its 1,300 MHz lock 2.33 (class v4, 8 October 2026); the modelled edge 2.2x to 2.4x a node ahead, 2.0x node for node (k 1.09), 2.8x two nodes ahead on the synthesised 8-lane core; the 32-lane rows pending (about 2.4x to 2.6x a node ahead, 2.0x to 2.2x node for node); the shadow's premium on a 5090 81.8 W at its knee (class v4 at the 1,200 MHz lock 133.80 MH/s at 305.1 W; class v3 at 1,300 MHz 134.62 at 223.3 W; 7 October 2026); 1.067x at the ceiling; 12 percent on 15 days a century; 10.85 ms at rung 3; 6 to 8 October 2026, the M5 Max, the desk rigs' RTX 5090, RTX 5080, RX 9070 XT and RTX 4070, rented pods, a rented H100 SXM, igneum-build-1 Bitmain's Antminer X9 (RandomX; 1,000 KH/s, 2,472 W, 2.47 J per KH, USD 5,600; pre-orders 26 December 2025) was withdrawn in mid-May 2026 with buyers refunded before any unit shipped, no independent benchmark, commodity Sophgo SG2044 server SoCs with an AES accelerator, no tapeout: it is a precedent on the served pages, not a chip core against the model (attack pass AP-F5-1, 7 October 2026; the close's 10.0f, 8 October 2026). Withdrawn from the served pages on 8 October 2026 and not restated: the 2.1x and 3.4x launch line, the 5x to 9x class v3 baseline, the ladder's 2.8x row, the USD 100 M pay-back row, any chip-arrival probability, the lifetime claim and the USD 300 M and 340 M lines. | none yet; the next test is the internal adversarial pass (three lanes new to the hash code, outsider inputs only, reports published whole), whose floor reading is in (measured, 8 October 2026; ledger AP-F8-1 and AP-F8-6): nine of nine hot sets refused; the diffuse era-stride excess, bounded under 0.1 percent of a hash's reads per site, is not caught by the floor and is the next class's test, and no outside review has run yet | | 18 | The chip resistance measurements: the program is latency-bound (dependent reads spread over the whole dataset), not bandwidth-bound, on every card we own, and sits beyond a card's on-chip cache; measured 8 October 2026: the distinct-index floor holds at 0.995 on every accepted program, about half of epochs carry one load site with a biased address bit at the era's stride rotation, priced at about 1.6 percent of a hash's reads to a chip storing half the dataset and nothing to one storing all of it (`docs/analysis/class-v6/family-gate.md`, lane D; adv-cache-2's `report-chained-cache-2.md` section 2.3 on its branch; ledger AP-F8-7) | Litepaper Mining ("waits on memory latency, not on maths or bandwidth"), vs RandomX; the numbers page | tested by the team | readwidth e752fc7 (`docs/plans/read-width.md`), ca2-era 78c0ee4, ca2-cache 2de19e5 (`docs/plans/hot-table.md`) | The dependent-read probes at 32 to 1,024 MiB and the hash rate per class on the three cards; the latency-bound share = rate over the probe ceiling per load | Latency-bound share at the 1 GiB dataset: RTX 5090 0.96 (v2) and 1.01 (v3), RX 9070 XT 0.87 and 0.95, M5 Max 1.01 and 1.06; wider reads do not close the AMD gap (the 9070 XT does 2.4 G dependent reads per second at every width; the 5090 goes bandwidth-bound at 64 B, share 0.58); a 32 to 96 MiB hot table is not kept resident by any card while the dataset streams (g 0.80 to 0.87 in the added form). 5 October 2026 | none yet | | 19 | The lottery hash is sound as a hash: uniform output, deterministic, no out-of-bounds read, fuzzed; class v3 bit-exact on the three vendors | Litepaper vs RandomX ("Every number above is measured and logged"), the numbers page | tested by the team | ca2-mixer 1ab8b21 (`tests/mixer.rs`, `tests/scratch.rs`), ca2-era 78c0ee4, ca2-soundness a465881 (`docs/analysis/scratch-soundness.md`), `igneum-pow/tests/packs.rs` | The crate suite (53 + 4 + 19 + 7), the Metal fuzz, edge, stats and determinism runs on the v3 construction, the pack vectors and 2^24 fingerprints on Metal, Apple OpenCL, the RTX 5090 and the RX 9070 XT, the 1,024-hash CPU re-check per card | Class v3 (mixer x8 + era): 200-program fuzz 200 of 200 on Metal, every tenth on Apple OpenCL; the pinned v3 packs 3/3 + 3/3 and 96 of 96 lanes on Metal and Apple OpenCL; the six era packs' fingerprints equal on the three vendors (PC 1 job run-ca2-era-pc1-20261005, 5 October 2026); the v2 exports byte-identical on the v3 crate; the final-class PC rows and the G2 re-check: job run-ca2-era-pc1b-20261005 (pending at the time of writing) | none yet | | 20 | No premine, no pre-sale, no allocation: every coin is minted by the schedule and every coin goes to the block producer (80%) and the proving pool (20%) | Homepage stats and Economics tiles; litepaper Supply, Economics | implemented | repo `6ac80a3`; fork "igneum-node devnet v0"; `consensus/core/src/igneum.rs`, `coinbase.rs` | `cargo test -p kaspa-consensus-core igneum` (8 pass: subsidy table, ramp, split, cap) and `cargo test -p kaspa-consensus coinbase` (8 pass); `igneum-miner inspect 40`; bench-log "igneum-node devnet v0" | Coinbases on the devnet: 80/20 exact on 39 of 39 single-payee blocks, the 20% to the `igneum-proving-pool-v0` output; the per-second schedule sums to under the 4,000,000,000 cap by less than 100 coins; 3,168,808,781 units per DAA second in years 0 to 2, halving at 63,115,200 DAA s. 3 October 2026, Apple M5 Max. The devnet genesis carries no allocation; the mainnet genesis does not exist yet, so the claim is about the code and the stated rule, not a launch that has happened | none yet | diff --git a/docs/fud-ledger.md b/docs/fud-ledger.md index 69a430a0f..a57e4aac3 100644 --- a/docs/fud-ledger.md +++ b/docs/fud-ledger.md @@ -2335,7 +2335,7 @@ Evidence: `docs/design/latency-ladder.md` (the k column, the rung table at k = 0 Status: Fixed, stated; restated (7 October 2026, evening, by order of the coordinator; the chip-text rewrite e57da45a, on master at 25f38035): the served texts give the floor and the premium at the 5090's measured knee: 2.1x per joule with a core as good as a GPU lane (k = 1), 3.4x with one three times better (k about 0.33), no core below about 1.8 pJ per op in the model's range, the premium 81.8 W at the best points, Ember Tune named as how a user gets there; the ledger pin for X35 moved to the new sentence; `site/litepaper.html#chip-model` and the home line. -Status: Fixed, stated; restated (8 October 2026, afternoon, by order of main after two accepted external reviews of the class v6 close; `docs/design/class-v6-rotating-family.md` 10.0f to 10.0h): the served chip text is the review's sentence, verbatim on the home line, the litepaper's abstract, chip section and limits item, and the miner page: "Class v6 retains the 64-register window. Current modelling estimates a 2.2x to 2.4x energy-efficiency advantage for the strongest specialised designs assessed against the GPU tier (2.0x on the GPU's own node). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment." Every number carries its label (2.2x to 2.4x modelled on the measured RTX 5080 and RTX 5090 lock rows of 8 October 2026, the chip core synthesised on ASAP7 and scaled to N3, claimed, its memory modelled; 2.0x node for node modelled, k 1.09; the node column claimed scaling; the 32-lane rows pending beside it). The three statements (energy resistance, economic resistance, response capability) are served separate; the harness and the scoring rule are linked beside the sentence. Struck from every served page: the 2.1x and 3.4x launch line, the 5x to 9x baseline, the ladder's 2.8x row, the USD 100 M pay-back row and the k about 0.33 column; never served and not to be: the lifetime claim, the USD 300 M and 340 M lines, any chip-arrival probability, the 725d2945 sentence. The pins for X35 moved to the new sentence (`tools/ci/ledger-text-check.mjs`). Was: the 2.1x to 3.4x range at the 5090's knee, below. +Status: Fixed, stated; restated (8 October 2026, afternoon, by order of main after two accepted external reviews of the class v6 close; `docs/design/class-v6-rotating-family.md` 10.0f to 10.0h): the served chip text is the review's sentence, verbatim on the home line, the litepaper's abstract, chip section and limits item, and the miner page: "Class v6 adopts the 64-register window and retains it across every rotation. Current modelling estimates a 2.2x to 2.4x energy-efficiency advantage for the strongest specialised designs assessed against the GPU tier (2.0x on the GPU's own node). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment." Every number carries its label (2.2x to 2.4x modelled on the measured RTX 5080 and RTX 5090 lock rows of 8 October 2026 and the card's measured cost of the window (a rented 5090 and 4090 at stock, within 5 percent per load), the chip core synthesised on ASAP7 and scaled to N3, claimed, its memory modelled; 2.0x node for node modelled, k 1.09; the node column claimed scaling; the 32-lane rows pending beside it). The three statements (energy resistance, economic resistance, response capability) are served separate; the harness and the scoring rule are linked beside the sentence. Struck from every served page: the 2.1x and 3.4x launch line, the 5x to 9x baseline, the ladder's 2.8x row, the USD 100 M pay-back row and the k about 0.33 column; never served and not to be: the lifetime claim, the USD 300 M and 340 M lines, any chip-arrival probability, the 725d2945 sentence. The pins for X35 moved to the new sentence (`tools/ci/ledger-text-check.mjs`). Was: the 2.1x to 3.4x range at the 5090's knee, below. ### X36. The X9 described as a shipping chip "X34 and X35 said Bitmain's Antminer X9 'ships from July 2026' and called it 'the shipping RandomX chip'. It never shipped: Bitmain opened pre-orders on 26 December 2025 for July 2026 delivery, resellers told buyers in mid-May 2026 that Bitmain had discontinued it and refunded them, no unit was delivered and none was independently benchmarked." diff --git a/docs/ledger-public.md b/docs/ledger-public.md index 37411702c..2ea231bc9 100644 --- a/docs/ledger-public.md +++ b/docs/ledger-public.md @@ -186,7 +186,7 @@ Generated by `tools/ledger/export-public.mjs` from `docs/fud-ledger.md`; a gate | X32 | The roadmap carried calendar months beside a testnet that is weeks away | Fixed, stated | Every calendar month is out of the roadmap. | [site/litepaper.html](../site/litepaper.html) | | X33 | The public benchmark dated "January 2027" | Fixed, stated | Both sentences read "The public benchmark with a leaderboard ships with the public testnet." (`site/litepaper.html`, For miners and Questions miners ask). | [site/litepaper.html](../site/litepaper.html) | | X34 | RandomX described as chip-free | Fixed, stated | Four sentences corrected, each with the X9 as the stated fact and its date; every sentence that only names the technique stands. | [site/index.html](../site/index.html) | -| X35 | The class v4 chip headline stated as one number, 2.1x | Fixed, stated; restated | The served chip text is the review's sentence, verbatim on the home line, the litepaper's abstract, chip section and limits item, and the miner page: "Class v6 retains the 64-register window. | [docs/design/latency-ladder.md](../docs/design/latency-ladder.md) | +| X35 | The class v4 chip headline stated as one number, 2.1x | Fixed, stated; restated | The served chip text is the review's sentence, verbatim on the home line, the litepaper's abstract, chip section and limits item, and the miner page: "Class v6 adopts the 64-register window and retains it across every… | [docs/design/latency-ladder.md](../docs/design/latency-ladder.md) | | X36 | The X9 described as a shipping chip | Fixed, stated; restated | The X9 appears on the served pages only as a precedent (the pre-order, the withdrawal, no benchmark) and no served sentence uses its claimed core as a chip core against the model; the Antminer X5 is served as an… | [site/index.html](../site/index.html) | | X37 | The class v4 energy premium is a cost the user pays, not a line in a model | Answered with evidence | Measured on the RTX 5090, 145 W of premium unlocked and 82 W at the knee; the RTX 5080 at stock 84 W, its grid running; the team identity says the premium needed for 2x at k = 1 is 103 W at the lock and a premium of… | [docs/plans/counter-asic-3-status.md](../docs/plans/counter-asic-3-status.md) | | N1 | A 0.3.15 node on the live file wrote blocks every 0.3.14 node rejected | Fixed | The class v4 signal (PROPOSED, `docs/plans/counter-asic-3-node.md` section 6) is the producer's object version in the high byte of the header version; the first 0.3.15 build stamped it from the binary alone, so on the… | [infra/fast-time/node-compat.mjs](../infra/fast-time/node-compat.mjs) | diff --git a/site/claims.html b/site/claims.html index 0cf6979ff..af5a03ddb 100644 --- a/site/claims.html +++ b/site/claims.html @@ -243,7 +243,7 @@

Here are the limits, stated before anyone else states them.

diff --git a/site/ledger.html b/site/ledger.html index 42daf2520..f417f8585 100644 --- a/site/ledger.html +++ b/site/ledger.html @@ -1377,7 +1377,7 @@ blockquote{margin:10px 0;padding:10px 14px;border-left:3px solid var(--line-2);c
X35

The class v4 chip headline stated as one number, 2.1x

8 October 2026
The home page said the strongest chip reaches 'about 2x once the lever now in its gates ships' and the litepaper said the latency-shadow work 'brings the chip to about 2x' and that its edge 'falls from 5.6x to 2.1x ... at a chip core equal to the GPU's'. That 2.1x assumes the chip's core costs what the GPU's does per operation (k = 1). Bitmain's Antminer X9 reached about a third of its honest device's energy on a latency-bound random program, so k about 0.33 is a shipped product class, and at that k the same model gives 3.9x.
-
Fixed, stated; restated 8 October 2026, afternoon, by order of main after two accepted external reviews of the class v6 close; a repository file 10.0f to 10.0h): the served chip text is the review's sentence, verbatim on the home line, the litepaper's abstract, chip section and limits item, and the miner page: "Class v6 retains the 64-register window. Current modelling estimates a 2.2x to 2.4x energy-efficiency advantage for the strongest specialised designs assessed against the GPU tier (2.0x on the GPU's own node). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment." Every number carries its label (2.2x to 2.4x modelled on the measured RTX 5080 and RTX 5090 lock rows of 8 October 2026, the chip core synthesised on ASAP7 and scaled to N3, claimed, its memory modelled; 2.0x node for node modelled, k 1.09; the node column claimed scaling; the 32-lane rows pending beside it). The three statements (energy resistance, economic resistance, response capability) are served separate; the harness and the scoring rule are linked beside the sentence. Struck from every served page: the 2.1x and 3.4x launch line, the 5x to 9x baseline, the ladder's 2.8x row, the USD 100 M pay-back row and the k about 0.33 column; never served and not to be: the lifetime claim, the USD 300 M and 340 M lines, any chip-arrival probability, the 725d2945 sentence. The pins for X35 moved to the new sentence (a repository file). Was: the 2.1x to 3.4x range at the 5090's knee, below.
+
Fixed, stated; restated 8 October 2026, afternoon, by order of main after two accepted external reviews of the class v6 close; a repository file 10.0f to 10.0h): the served chip text is the review's sentence, verbatim on the home line, the litepaper's abstract, chip section and limits item, and the miner page: "Class v6 adopts the 64-register window and retains it across every rotation. Current modelling estimates a 2.2x to 2.4x energy-efficiency advantage for the strongest specialised designs assessed against the GPU tier (2.0x on the GPU's own node). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment." Every number carries its label (2.2x to 2.4x modelled on the measured RTX 5080 and RTX 5090 lock rows of 8 October 2026 and the card's measured cost of the window (a rented 5090 and 4090 at stock, within 5 percent per load), the chip core synthesised on ASAP7 and scaled to N3, claimed, its memory modelled; 2.0x node for node modelled, k 1.09; the node column claimed scaling; the 32-lane rows pending beside it). The three statements (energy resistance, economic resistance, response capability) are served separate; the harness and the scoring rule are linked beside the sentence. Struck from every served page: the 2.1x and 3.4x launch line, the 5x to 9x baseline, the ladder's 2.8x row, the USD 100 M pay-back row and the k about 0.33 column; never served and not to be: the lifetime claim, the USD 300 M and 340 M lines, any chip-arrival probability, the 725d2945 sentence. The pins for X35 moved to the new sentence (a repository file). Was: the 2.1x to 3.4x range at the 5090's knee, below.
The answer as first written

One number was the model's k = 1 column; the X9 made the k = 0.33 column a product rather than a claim, so the public figure is the range. Rung 2 of the ladder (the top admissible rung on 6 October 2026) takes the X9 bracket from about 3.9x to about 2.8x and does not close it; the ladder moves at the pace of the cards that pay for it (M34).

diff --git a/site/litepaper.html b/site/litepaper.html index d786f7e62..b24646cda 100644 --- a/site/litepaper.html +++ b/site/litepaper.html @@ -335,7 +335,7 @@ body.all .pager{display:none}

Abstract

-

Igneum is a proof-of-work blockchain built for graphics cards, where NVIDIA cards also prove every block with zero-knowledge proofs and sell proving to other chains. Class v6 retains the 64-register window. Current modelling estimates a 2.2x to 2.4x energy-efficiency advantage for the strongest specialised designs assessed against the GPU tier (2.0x on the GPU's own node). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment. The chip model: every number labelled measured, modelled or claimed, the harness and the scoring rules beside it.

+

Igneum is a proof-of-work blockchain built for graphics cards, where NVIDIA cards also prove every block with zero-knowledge proofs and sell proving to other chains. Class v6 adopts the 64-register window and retains it across every rotation. Current modelling estimates a 2.2x to 2.4x energy-efficiency advantage for the strongest specialised designs assessed against the GPU tier (2.0x on the GPU's own node). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment. The chip model: every number labelled measured, modelled or claimed, the harness and the scoring rules beside it.

It runs the Ethereum virtual machine, so anything built for Ethereum runs on Igneum unchanged. Transactions are included in about one second, proven within about a minute at launch, and locked by miners within about two. There is no premine, no pre-sale, no treasury taken from emission, no stake anywhere in consensus, and no dependence on any other chain. Mining stays open to anyone with a GPU because the mining program changes every hour, so a chip built for one program is useless for the next, and a chip for the whole program space is a GPU without the graphics parts. No scheduled human release is needed to keep it that way. Writing new code, including an emergency fix to the proof system, is the one thing that takes a person, and it activates only on miner signalling.

1 / s
blocks, rising to 10
@@ -460,8 +460,8 @@ body.all .pager{display:none}

Three ideas carry the chip resistance. The hash rewrites itself. A new program every hour, drawn from the chain. Its memory pattern changes with it. The rules change on a schedule fixed at launch. No release, no vote. These are automatic schedule changes: they defeat a chip wired for one datapath and they need no human fork. Against a chip that stores the dataset every drawn parameter is firmware, and what meets that chip is the latency-shadow work (class v4) and the price per joule (the Horizon lane analysis, 6 October 2026, section 5.4; ledger M32). It waits on memory, not maths. Every hash is a chain of random reads into a table too big for a chip to carry. Measured (8 October 2026; lane D’s family harness at the acceptance rule’s own 2^20 sample over 4,900 drawn eras, and the chained-cache pass’s reading of the night before): every hash’s 128 dependent reads land across the whole dataset and the distinct-index floor holds at 0.995 on every accepted program; about half of epochs carry one load site whose address bit at the era’s stride rotation is biased, which prices about 1.6 percent of a hash’s reads to a chip storing half the dataset and nothing to a chip storing all of it; the next class folds the product’s low bits before the rotation, so no era lands a biased bit on an address bit. The wait is the same physics for everyone. Miners hold the switch. Spare defences are written into the rules, switched off. A miner signal turns one on, at the class-change threshold: miners signal three things at three thresholds, 60 percent of blue blocks over two weeks for a parameter genesis leaves open, 90 percent for an upgrade (new code), and 95 percent with a floor height for a class change. No fork.

The work that waits can grow. Class v4 adds a block of latency-shadow arithmetic to every hash, about 100,000 integer operations that run while the memory reads are in flight, so a chip that stores the whole dataset still has to pay for a core. That size sits on a ladder fixed at genesis, six rungs from about 100,000 to about 1,000,000 operations, and it moves one rung at a time only when 90 percent of blue blocks in each of seven consecutive days ask for it; it can never move two rungs inside a week and never past a rung the reference verifier cannot check under 10 ms with its sibling thread busy (measured on the build server, 6 October 2026: the first three rungs pass at 8.8, 8.9 and 9.2 ms, the fourth misses by 0.08 ms on a loaded box and stays out until a quiet re-measurement, the two doublings are out at 12.4 and 15.0 ms). What it buys against a chip is scored under the rule in the chip model below. What it costs, per rung, is measured too: the Apple tier gives up 3 points of rate at the first step and 6 more at the second, the RTX 5090 nothing until the second; so the miners who pay for a step are the ones who take it (ledger M34).

The chip model

-

Class v6 retains the 64-register window. Current modelling estimates a 2.2x to 2.4x energy-efficiency advantage for the strongest specialised designs assessed against the GPU tier (2.0x on the GPU's own node). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment.

-

The labels. 2.2x to 2.4x is modelled. The GPU side is measured: an RTX 5080 at its 1,100 MHz core lock, 2.06 microjoules per hash, and an RTX 5090 at its 1,300 MHz lock, 2.33 microjoules per hash, both under class v4, on the project’s own rigs and rented pods, 8 October 2026. The chip side is claimed: a synthesised 8-lane sequencer core with the 64-register window on ASAP7, scaled to N3 on the foundry’s headline factors; the window’s k is synthesis-derived and not a lower bound. The chip’s memory is modelled: the GDDR7 board of the chip model. 2.0x on the GPU’s own node is modelled: the same core node for node (k 1.09). Pending beside the sentence: against a 32-lane window core the same figures read about 2.4x to 2.6x a node ahead and 2.0x to 2.2x node for node (synthesised; the re-optimised row is due on the evening of 8 October 2026 and is served when it lands).

+

Class v6 adopts the 64-register window and retains it across every rotation. Current modelling estimates a 2.2x to 2.4x energy-efficiency advantage for the strongest specialised designs assessed against the GPU tier (2.0x on the GPU's own node). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment.

+

The labels. 2.2x to 2.4x is modelled. The GPU side is measured: an RTX 5080 at its 1,100 MHz core lock, 2.06 microjoules per hash, and an RTX 5090 at its 1,300 MHz lock, 2.33 microjoules per hash, both under class v4, on the project’s own rigs and rented pods, 8 October 2026; the card’s cost of the window is measured too (a rented RTX 5090 and RTX 4090 at stock, 8 October 2026: within 5 percent per load with the liveness chain, no register spill). The chip side is synthesised and claimed: a synthesised 8-lane sequencer core with the 64-register window on ASAP7, scaled to N3 on the foundry’s headline factors; the window’s k is synthesis-derived and not a lower bound. The chip’s memory is modelled: the GDDR7 board of the chip model. 2.0x on the GPU’s own node is modelled: the same core node for node (k 1.09). Pending beside the sentence: against a 32-lane window core the same figures read about 2.4x to 2.6x a node ahead and 2.0x to 2.2x node for node (synthesised; the re-optimised row is due on the evening of 8 October 2026 and is served when it lands).

Three statements, kept separate.

@@ -826,7 +826,7 @@ body.all .pager{display:none}

Here are the limits, stated before anyone else states them.

  • A proof in seconds. Not at launch. Proving a full block today needs a cluster of 100 to 200 consumer GPUs, approximate, so Igneum launches with proofs within about a minute and tightens as hardware improves. Users still see their transaction land in one second.
    • -
  • A chip is impossible. No. A chip wired for one program is a bad bet, because the program moves before it ships. A programmable chip is not stopped by the moving target: everything it needs is public at genesis and every drawn parameter is firmware to it (an address permute, a rotator, an immediate table), so the defence against it is the latency-shadow work (class v4) and the price per joule, not the schedule (the Horizon lane analysis, 6 October 2026, section 5.4; ledger M32). Class v6 retains the 64-register window. Current modelling estimates a 2.2x to 2.4x energy-efficiency advantage for the strongest specialised designs assessed against the GPU tier (2.0x on the GPU's own node). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment. The labels: 2.2x to 2.4x modelled (the GPU side measured on the RTX 5080 and RTX 5090 at their core locks under class v4, 8 October 2026; the chip core synthesised on ASAP7 and scaled to N3, claimed; its memory modelled); 2.0x on the GPU’s own node modelled. Class v5 makes the dataset the chain’s own state, so a chip that stores it or recomputes it is wrong on every item (designed, 7 October 2026). The strongest recompute chip we can price, holding the whole 256 MiB cache on-die, reaches under 1x per chip against an RTX 5090 (the published model, 5 October 2026: 0.92x per unit of silicon with a 3x fixed-function allowance, approximate). Sources: the class v6 close, section 10 (8 October 2026); the ASIC history’s Ethash rows; the chip model analysis (6 October 2026). No hash has stayed free of chips forever; Igneum does not claim to. Monero’s RandomX has held its miners on commodity hardware for about seven years: one chip shipped against it, Bitmain’s Antminer X5 (September 2023), an observed comparison, not a ceiling; the one announced beyond it, the Antminer X9, was withdrawn in mid-May 2026 before any unit shipped, its claimed core never measured; RandomX v2 was released on 25 March 2026 with its activation pending. That record says nothing about the price of a chip with the 256 MB cache on its die; that price is a cost model, not a measurement.
    • +
  • A chip is impossible. No. A chip wired for one program is a bad bet, because the program moves before it ships. A programmable chip is not stopped by the moving target: everything it needs is public at genesis and every drawn parameter is firmware to it (an address permute, a rotator, an immediate table), so the defence against it is the latency-shadow work (class v4) and the price per joule, not the schedule (the Horizon lane analysis, 6 October 2026, section 5.4; ledger M32). Class v6 adopts the 64-register window and retains it across every rotation. Current modelling estimates a 2.2x to 2.4x energy-efficiency advantage for the strongest specialised designs assessed against the GPU tier (2.0x on the GPU's own node). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment. The labels: 2.2x to 2.4x modelled (the GPU side measured on the RTX 5080 and RTX 5090 at their core locks under class v4, 8 October 2026; the chip core synthesised on ASAP7 and scaled to N3, claimed; its memory modelled); 2.0x on the GPU’s own node modelled. Class v5 makes the dataset the chain’s own state, so a chip that stores it or recomputes it is wrong on every item (designed, 7 October 2026). The strongest recompute chip we can price, holding the whole 256 MiB cache on-die, reaches under 1x per chip against an RTX 5090 (the published model, 5 October 2026: 0.92x per unit of silicon with a 3x fixed-function allowance, approximate). Sources: the class v6 close, section 10 (8 October 2026); the ASIC history’s Ethash rows; the chip model analysis (6 October 2026). No hash has stayed free of chips forever; Igneum does not claim to. Monero’s RandomX has held its miners on commodity hardware for about seven years: one chip shipped against it, Bitmain’s Antminer X5 (September 2023), an observed comparison, not a ceiling; the one announced beyond it, the Antminer X9, was withdrawn in mid-May 2026 before any unit shipped, its claimed core never measured; RandomX v2 was released on 25 March 2026 with its activation pending. That record says nothing about the price of a chip with the 256 MB cache on its die; that price is a cost model, not a measurement.
  • A guaranteed income floor. No. External proving is a small market today. Igneum's miners' electricity cost in it is close to power, but the price they must charge is the subsidy they forgo, which falls as one over network hash: an edge at scale and nothing more.
  • A memory-hard prototype on every vendor. Not yet. The 256 MB cache closed the shortcut on Apple silicon (computing items runs 4.8x slower than loading them, measured 3 October 2026). The same ratio on NVIDIA and on a discrete AMD card is Open.
  • Finality in the first month. No. No checkpoint locks until the 30-day window has 30 days of history. The first month of mainnet is proof of work with a 12-hour depth, and the text above says so wherever a day count appears.
    • diff --git a/site/miner.html b/site/miner.html index f6bc25895..7f3e5f1dc 100644 --- a/site/miner.html +++ b/site/miner.html @@ -327,7 +327,7 @@ pre b{color:var(--molten-text);font-weight:500}
StatementWhat it saysLabel and date
Energy resistanceThe figures above: 2.2x to 2.4x for the strongest specialised design a node ahead of the GPU tier; 2.0x on the GPU’s own node; 2.8x two nodes ahead, on the 8-lane core. The honest tier moves to the next node with every GPU generation; a chip must tape out again.modelled on measured cards, 8 October 2026; the node column is claimed scaling

Graphics cards only. A new mining program every hour, so no chip is built for it. 80% of every block to the card that finds it, 20% to the cards that prove it. No premine, no stake, no fee to any team. Every number above has a row in the bench table.

-

Your card against the strongest chip we can price. Class v6 retains the 64-register window. Current modelling estimates a 2.2x to 2.4x energy-efficiency advantage for the strongest specialised designs assessed against the GPU tier (2.0x on the GPU's own node). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment. The GPU side is measured: an RTX 5080 and an RTX 5090 at their core locks under class v4 (8 October 2026); the chip core is synthesised and claimed; its memory is modelled. Under class v5 the chip is wrong on every item because the dataset is the chain’s own state (designed). Every number with its label, the harness and the scoring rules.

+

Your card against the strongest chip we can price. Class v6 adopts the 64-register window and retains it across every rotation. Current modelling estimates a 2.2x to 2.4x energy-efficiency advantage for the strongest specialised designs assessed against the GPU tier (2.0x on the GPU's own node). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment. The GPU side is measured: an RTX 5080 and an RTX 5090 at their core locks under class v4 (8 October 2026); the chip core is synthesised and claimed; its memory is modelled. Under class v5 the chip is wrong on every item because the dataset is the chain’s own state (designed). Every number with its label, the harness and the scoring rules.

diff --git a/tools/ci/ledger-text-check.mjs b/tools/ci/ledger-text-check.mjs index 58ac942ba..da12aa42d 100644 --- a/tools/ci/ledger-text-check.mjs +++ b/tools/ci/ledger-text-check.mjs @@ -25,7 +25,7 @@ const REQUIRED = { ['C2', 'Monero has run on RandomX since November 2019'], ['X34', 'was withdrawn in mid-May 2026 before any unit shipped; RandomX 2.0 shipped on 25 March 2026'], ['X36', 'Bitmain opened Antminer X9 pre-orders on 26 December 2025 for July 2026 delivery, then withdrew the product in mid-May 2026 and refunded buyers before any unit shipped; none has been independently benchmarked.'], - ['X35', 'Class v6 retains the 64-register window.'], + ['X35', 'Class v6 adopts the 64-register window and retains it across every rotation.'], ['X35', 'The long-program and select-tree proposals were rejected.'], ['X36', 'an observed comparison, not a ceiling'], ['M34', 'The work that waits can grow.'],