Merge amd-intel-energy-registry-docs f1cbd84d into master (gate: green on 8651f9bf, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)

docs/plans/igneum-2.0-test-harness-map.md

@@ -334,6 +334,14 @@ Rule: a case maps to a cell only where the cell's tests visibly answer it; cover
   - ROT-07 Ablate redundant rotation layers: partial: the acceptance-side ablation rows (layer 8 off against the same-crate windowed control: the draw cost, the floors' costs, the hot-set and 1.2x ceiling, the bit-R read; the mixer and shape axes' per-era invisibility and verifier rows), docs/analysis/class-v6/family-gate.md sections 6.4 to 6.12; the adversarial cost and the GPU setup rows per layer are the hash lane's and the adversary lane's
   - ROT-08 Pass the no-new-rules counterfactual: partial: the no-rescue control document (38,000 drawn eras of the parameter family through the acceptance, the bound arithmetic on the counts, the honest line of what the gate cannot see), family-gate.md sections 1 to 6; the competitiveness envelope and the economic half are ECO's
 
+### bench:amd-intel-energy
+
+- Command: `the AMD-and-Intel energy lane jobs on the signed-jobs channel: run-ae-pc2-b580-energy-20261008 (PC 2, Arc B580, the class v6 kit worker --memprobe and --bench-pack on hl-v6-foldrw and hl-v6-all, Level Zero energy counter) and run-ae-pc1-7600-energy-20261008 (PC 1, RX 7600, the same with ADLX watts at stock, plimit -30, gmax -500 + plimit -30); scripts in docs/analysis/class-v6/amd-intel-energy/`
+- Box class: PC 1 and PC 2 bench (OpenCL)
+- Fixtures: F0, F1
+- Cases:
+  - GPU-03 Measure the real 64-register GPU cost: partial: the 64-register window on AMD and Intel, rate per unit of work (RX 7600 0 percent, Arc B580 -0.3 percent, kernel throughput, quiet) with the B580 fingerprints equal on both packs and the offline RDNA allocation (160 VGPRs, no spill); energy owed (the 7600 job queued, the B580 counter unsupported unelevated); team-run, not under the standard's paired protocol or a wall meter
+
 ## Automated cases with no harness in the matrix (NOT RUN, the reason)
 
 - GOV-02 Approve thresholds before results: the approval is recorded in the registry's approval field; the automated half (thresholds frozen before any run_status) is the gate rule landing by 21:00

tools/ci/batches/amd-intel-energy-20261008-01.json

@@ -0,0 +1,15 @@
+{
+ "run_id": "amd-intel-energy-20261008-01",
+ "manifest_sha": "c245d50b9",
+ "evidence_dir": "docs/analysis/class-v6/amd-intel-energy",
+ "cells": [
+  {
+   "cell": "bench:amd-intel-energy",
+   "status": "NOT RUN",
+   "evidence": "docs/analysis/class-v6/amd-intel-energy.md",
+   "note": "GPU-03 AMD and Intel cells: the window costs the RX 7600 0 percent and the Arc B580 -0.3 percent of rate per unit of work (measured, kernel throughput, quiet); B580 fingerprints equal on hl-v6-foldrw and hl-v6-all; energy owed (RX 7600 ADLX job queued behind a held PC 1 runner; the B580 Level Zero energy counter unsupported unelevated); RUNNING, not PASS: team-run, no paired 30-minute protocol, no wall meter",
+   "method": "GPU",
+   "in_progress": true
+  }
+ ]
+}

tools/ci/test-map.json

@@ -574,6 +574,20 @@
         "ROT-07": "partial: the acceptance-side ablation rows (layer 8 off against the same-crate windowed control: the draw cost, the floors' costs, the hot-set and 1.2x ceiling, the bit-R read; the mixer and shape axes' per-era invisibility and verifier rows), docs/analysis/class-v6/family-gate.md sections 6.4 to 6.12; the adversarial cost and the GPU setup rows per layer are the hash lane's and the adversary lane's",
         "ROT-08": "partial: the no-rescue control document (38,000 drawn eras of the parameter family through the acceptance, the bound arithmetic on the counts, the honest line of what the gate cannot see), family-gate.md sections 1 to 6; the competitiveness envelope and the economic half are ECO's"
       }
+    },
+    "bench:amd-intel-energy": {
+      "command": "the AMD-and-Intel energy lane jobs on the signed-jobs channel: run-ae-pc2-b580-energy-20261008 (PC 2, Arc B580, the class v6 kit worker --memprobe and --bench-pack on hl-v6-foldrw and hl-v6-all, Level Zero energy counter) and run-ae-pc1-7600-energy-20261008 (PC 1, RX 7600, the same with ADLX watts at stock, plimit -30, gmax -500 + plimit -30); scripts in docs/analysis/class-v6/amd-intel-energy/",
+      "box_class": "PC 1 and PC 2 bench (OpenCL)",
+      "fixtures": [
+        "F0",
+        "F1"
+      ],
+      "cases": [
+        "GPU-03"
+      ],
+      "coverage": {
+        "GPU-03": "partial: the 64-register window on AMD and Intel, rate per unit of work (RX 7600 0 percent, Arc B580 -0.3 percent, kernel throughput, quiet) with the B580 fingerprints equal on both packs and the offline RDNA allocation (160 VGPRs, no spill); energy owed (the 7600 job queued, the B580 counter unsupported unelevated); team-run, not under the standard's paired protocol or a wall meter"
+      }
     }
   },
   "not_run": {