Chip text: the whole-machine sentence stands (1.5x to 3.1x; 1.5x to 2.3x on the GPU's own node) with the core-only line beside it (2.8x and 2.4x, placed and routed, plus or minus 15 percent) and the standard's P04 target as approved; the two-source range withdrawn (the coordinator's word: the rows measure different things)

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

site/claims.html

@@ -249,7 +249,7 @@
 <div class="derived"><p>Here are the limits, stated before anyone else states them.</p>
         <ul>
           <li><strong>A proof in seconds.</strong> Not at launch. Proving a full block today needs a cluster of 100 to 200 consumer GPUs, approximate, so Igneum launches with proofs within about a minute and tightens as hardware improves. Users still see their transaction land in one second.</li>
-          <li><strong>A chip is impossible.</strong> No. Igneum assumes a chip exists. A programmable chip is not stopped by the moving target: everything it needs is public at genesis and every drawn parameter is firmware to it (an address permute, a rotator, an immediate table), so the defence against it is the latency-shadow work (class v4) and the price per joule, not the schedule (the chip and economy analysis of 6 October 2026, section 5.4; <a href="/ledger#D3">ledger D3</a>). Igneum remains competitive on accessible commodity GPUs even when specialised mining hardware is assumed to exist, remain compatible and seek profit; its security does not rely on identifying that hardware or retiring it through emergency changes. Class v6 adopts the 64-register window and retains it across every rotation. Against a locked RTX 5090 on the same node, two placed-and-routed chip models put a DRAM-board machine at 1.5x to 2.4x per joule, a node ahead 1.8x to 2.8x; the board with SRAM holding the hottest half of the dataset about 1.9x and 2.4x, the SRAM-store die 2.3x and 3.1x, as before (MODELLED, two sources named, no chip measured; the reconciliation is due at 21:00 UK). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment. The labels: the bracket modelled, approximate and provisional (the GPU side measured on the RTX 5080 and RTX 5090 at their core locks under class v4, 8 October 2026; the chip core synthesised on ASAP7 and scaled to N3, claimed, its placed gated row pending; its memory modelled). Class v5 makes the dataset the chain’s own state, so a chip that stores it or recomputes it is wrong on every item (designed, 7 October 2026; under evaluation (Deliverable 3), not counted as a defence until justified or dropped). The strongest recompute chip we can price, holding the whole 256 MiB cache on-die, reaches under 1x per chip against an RTX 5090 (the published model, 5 October 2026: 0.92x per unit of silicon with a 3x fixed-function allowance, approximate). Sources: the class v6 close, section 10 (8 October 2026); the ASIC history’s Ethash rows; the chip model analysis (6 October 2026). No hash has stayed free of chips forever; Igneum does not claim to. Monero’s RandomX has held its miners on commodity hardware for about seven years: one chip shipped against it, Bitmain’s Antminer X5 (September 2023), an observed comparison, not a ceiling; the one announced beyond it, the Antminer X9, was withdrawn in mid-May 2026 before any unit shipped, its claimed core never measured; RandomX v2 was released on 25 March 2026 with its activation pending. That record says nothing about the price of a chip with the 256 MB cache on its die; that price is a cost model, not a measurement.</li>
+          <li><strong>A chip is impossible.</strong> No. Igneum assumes a chip exists. A programmable chip is not stopped by the moving target: everything it needs is public at genesis and every drawn parameter is firmware to it (an address permute, a rotator, an immediate table), so the defence against it is the latency-shadow work (class v4) and the price per joule, not the schedule (the chip and economy analysis of 6 October 2026, section 5.4; <a href="/ledger#D3">ledger D3</a>). Igneum remains competitive on accessible commodity GPUs even when specialised mining hardware is assumed to exist, remain compatible and seek profit; its security does not rely on identifying that hardware or retiring it through emergency changes. Class v6 adopts the 64-register window and retains it across every rotation. Current modelling estimates a 1.5x to 3.1x energy-efficiency advantage for the specialised designs assessed as complete machines against the GPU tier, from a board on commodity DRAM at 1.5x to an SRAM-store die at 3.1x (1.5x to 2.3x on the GPU's own node). The specialised core alone, placed and routed on ASAP7 with claimed node scaling (plus or minus 15 percent until the two-length solve lands): a 2.8x energy-efficiency advantage a node ahead, 2.4x on the GPU’s own node. The standard’s P04 target as approved: R_E at most 1.5 on the same node and one node ahead; today’s placed bracket reads against it as a FAIL to work against. The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment. The labels: the bracket modelled, approximate and provisional (the GPU side measured on the RTX 5080 and RTX 5090 at their core locks under class v4, 8 October 2026; the chip core synthesised on ASAP7 and scaled to N3, claimed, its placed gated row pending; its memory modelled). Class v5 makes the dataset the chain’s own state, so a chip that stores it or recomputes it is wrong on every item (designed, 7 October 2026; under evaluation (Deliverable 3), not counted as a defence until justified or dropped). The strongest recompute chip we can price, holding the whole 256 MiB cache on-die, reaches under 1x per chip against an RTX 5090 (the published model, 5 October 2026: 0.92x per unit of silicon with a 3x fixed-function allowance, approximate). Sources: the class v6 close, section 10 (8 October 2026); the ASIC history’s Ethash rows; the chip model analysis (6 October 2026). No hash has stayed free of chips forever; Igneum does not claim to. Monero’s RandomX has held its miners on commodity hardware for about seven years: one chip shipped against it, Bitmain’s Antminer X5 (September 2023), an observed comparison, not a ceiling; the one announced beyond it, the Antminer X9, was withdrawn in mid-May 2026 before any unit shipped, its claimed core never measured; RandomX v2 was released on 25 March 2026 with its activation pending. That record says nothing about the price of a chip with the 256 MB cache on its die; that price is a cost model, not a measurement.</li>
           <li><strong>A guaranteed income floor.</strong> No. External proving is a small market today. Igneum's miners' electricity cost in it is close to power, but the price they must charge is the subsidy they forgo, which falls as one over network hash: an edge at scale and nothing more.</li>
           <li><strong>A memory-hard prototype on every vendor.</strong> Not yet. The 256 MB cache closed the shortcut on Apple silicon (computing items runs 4.8x slower than loading them, measured 3 October 2026). The same ratio on NVIDIA and on a discrete AMD card is Open.</li>
           <li><strong>Finality in the first month.</strong> No. No checkpoint locks until the 30-day window has 30 days of history. The first month of mainnet is proof of work with a 12-hour depth, and the text above says so wherever a day count appears.</li>

site/index.html

@@ -280,7 +280,7 @@
     <div class="home-three rows">
       <div class="home-row"><span class="n">01</span><div><b>The same card finds the block and proves it.</b><p>Both jobs are paid by the chain today (TEAM-REPORTED on the facts page); what a card earns depends on the network and the price, which this site never states. When you stop, the card still games.</p></div></div>
       <div class="home-row"><span class="n">02</span><div><b>A fair start.</b><p>Nobody holds a coin before block one. The protocol carries no fee. The one payment to the project is the Ember software’s optional 1% dev fee, like other GPU miners, off with one flag.</p></div></div>
-      <div class="home-row"><span class="n">03</span><div><b>Built for graphics cards.</b><p>Igneum remains competitive on accessible commodity GPUs even when specialised mining hardware is assumed to exist, remain compatible and seek profit; its security does not rely on identifying that hardware or retiring it through emergency changes. Class v6 adopts the 64-register window and retains it across every rotation. Against a locked RTX 5090 on the same node, two placed-and-routed chip models put a DRAM-board machine at 1.5x to 2.4x per joule, a node ahead 1.8x to 2.8x; the board with SRAM holding the hottest half of the dataset about 1.9x and 2.4x, the SRAM-store die 2.3x and 3.1x, as before (MODELLED, two sources named, no chip measured; the reconciliation is due at 21:00 UK). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment. MODELLED: the GPU side measured (the RTX 5090 at its lock, 8 October 2026), the chip’s core placed and routed, the rest of the machine modelled, no chip measured, hardware cost approximate within 2x; the coexistence model finds the DRAM board passes six of seven conditions, the hybrid coexists only in a growing chain at cheap GPU electricity, and the SRAM die fails four conditions at its reconciled machine cost; a 5090 locked at its knee pays 82 W for the class v4 shadow work (measured, 7 October 2026). <a href="/litepaper#chip-model">Every number with its label, the harness and the scoring rules.</a></p></div></div>
+      <div class="home-row"><span class="n">03</span><div><b>Built for graphics cards.</b><p>Igneum remains competitive on accessible commodity GPUs even when specialised mining hardware is assumed to exist, remain compatible and seek profit; its security does not rely on identifying that hardware or retiring it through emergency changes. Class v6 adopts the 64-register window and retains it across every rotation. Current modelling estimates a 1.5x to 3.1x energy-efficiency advantage for the specialised designs assessed as complete machines against the GPU tier, from a board on commodity DRAM at 1.5x to an SRAM-store die at 3.1x (1.5x to 2.3x on the GPU's own node). The specialised core alone, placed and routed on ASAP7 with claimed node scaling (plus or minus 15 percent until the two-length solve lands): a 2.8x energy-efficiency advantage a node ahead, 2.4x on the GPU’s own node. The standard’s P04 target as approved: R_E at most 1.5 on the same node and one node ahead; today’s placed bracket reads against it as a FAIL to work against. The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment. MODELLED: the GPU side measured (the RTX 5090 at its lock, 8 October 2026), the chip’s core placed and routed, the rest of the machine modelled, no chip measured, hardware cost approximate within 2x; the coexistence model finds the DRAM board passes six of seven conditions, the hybrid coexists only in a growing chain at cheap GPU electricity, and the SRAM die fails four conditions at its reconciled machine cost; a 5090 locked at its knee pays 82 W for the class v4 shadow work (measured, 7 October 2026). <a href="/litepaper#chip-model">Every number with its label, the harness and the scoring rules.</a></p></div></div>
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site/miner.html

@@ -335,7 +335,7 @@ pre b{color:var(--molten-text);font-weight:500}
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     </table></div>
     <p class="fair"><b>Graphics cards only.</b> A new mining program every hour, so no chip is built for it. 80% of every block to the card that finds it, 20% to the cards that prove it. No premine, no stake, no fee to any team. Every number above has a row in <a href="/miners">the bench table</a>.</p>
-    <p class="fair">Your card against the strongest chip we can price. Igneum remains competitive on accessible commodity GPUs even when specialised mining hardware is assumed to exist, remain compatible and seek profit; its security does not rely on identifying that hardware or retiring it through emergency changes. Class v6 adopts the 64-register window and retains it across every rotation. Against a locked RTX 5090 on the same node, two placed-and-routed chip models put a DRAM-board machine at 1.5x to 2.4x per joule, a node ahead 1.8x to 2.8x; the board with SRAM holding the hottest half of the dataset about 1.9x and 2.4x, the SRAM-store die 2.3x and 3.1x, as before (MODELLED, two sources named, no chip measured; the reconciliation is due at 21:00 UK). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment. The GPU side is measured: the RTX 5090 at its 1,300 MHz lock, 2.33 microjoules per hash on class v4, the window’s cost within 5 percent per load (8 October 2026); the chip’s core is placed and routed on ASAP7 with SRAM macros and scaled on claimed node factors; its memory and the rest of the machine (controller, host share, PSU, VRM, cooling) are modelled; no chip is measured and the chip’s hardware cost is approximate within 2x (MODELLED). Under class v5 the chip is wrong on every item because the dataset is the chain’s own state (designed). <a href="/litepaper#chip-model">Every number with its label, the harness and the scoring rules</a>.</p>
+    <p class="fair">Your card against the strongest chip we can price. Igneum remains competitive on accessible commodity GPUs even when specialised mining hardware is assumed to exist, remain compatible and seek profit; its security does not rely on identifying that hardware or retiring it through emergency changes. Class v6 adopts the 64-register window and retains it across every rotation. Current modelling estimates a 1.5x to 3.1x energy-efficiency advantage for the specialised designs assessed as complete machines against the GPU tier, from a board on commodity DRAM at 1.5x to an SRAM-store die at 3.1x (1.5x to 2.3x on the GPU's own node). The specialised core alone, placed and routed on ASAP7 with claimed node scaling (plus or minus 15 percent until the two-length solve lands): a 2.8x energy-efficiency advantage a node ahead, 2.4x on the GPU’s own node. The standard’s P04 target as approved: R_E at most 1.5 on the same node and one node ahead; today’s placed bracket reads against it as a FAIL to work against. The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment. The GPU side is measured: the RTX 5090 at its 1,300 MHz lock, 2.33 microjoules per hash on class v4, the window’s cost within 5 percent per load (8 October 2026); the chip’s core is placed and routed on ASAP7 with SRAM macros and scaled on claimed node factors; its memory and the rest of the machine (controller, host share, PSU, VRM, cooling) are modelled; no chip is measured and the chip’s hardware cost is approximate within 2x (MODELLED). Under class v5 the chip is wrong on every item because the dataset is the chain’s own state (designed). <a href="/litepaper#chip-model">Every number with its label, the harness and the scoring rules</a>.</p>
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