Abstract
-A GPU-secured network for Ethereum-compatible applications and verifiable computation. Igneum is a proof-of-work chain built for graphics cards. AMD, Apple and NVIDIA cards mine; NVIDIA cards also prove its blocks with zero-knowledge proofs. Igneum remains competitive on accessible commodity GPUs even when specialised mining hardware is assumed to exist, remain compatible and seek profit; its security does not rely on identifying that hardware or retiring it through emergency changes. Class v6 adopts the 64-register window and retains it across every rotation. Against a locked RTX 5090 on the same node, two placed-and-routed chip models put a DRAM-board machine at 1.5x to 2.4x per joule, a node ahead 1.8x to 2.8x; the board with SRAM holding the hottest half of the dataset about 1.9x and 2.4x, the SRAM-store die 2.3x and 3.1x, as before (MODELLED, two sources named, no chip measured; the reconciliation is due at 21:00 UK). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment. The chip model: every number labelled measured, modelled or claimed, the harness and the scoring rules beside it.
+A GPU-secured network for Ethereum-compatible applications and verifiable computation. Igneum is a proof-of-work chain built for graphics cards. AMD, Apple and NVIDIA cards mine; NVIDIA cards also prove its blocks with zero-knowledge proofs. Igneum remains competitive on accessible commodity GPUs even when specialised mining hardware is assumed to exist, remain compatible and seek profit; its security does not rely on identifying that hardware or retiring it through emergency changes. Class v6 adopts the 64-register window and retains it across every rotation. Current modelling estimates a 1.5x to 3.1x energy-efficiency advantage for the specialised designs assessed as complete machines against the GPU tier, from a board on commodity DRAM at 1.5x to an SRAM-store die at 3.1x (1.5x to 2.3x on the GPU's own node). The specialised core alone, placed and routed on ASAP7 with claimed node scaling (plus or minus 15 percent until the two-length solve lands): a 2.8x energy-efficiency advantage a node ahead, 2.4x on the GPU’s own node. The standard’s P04 target as approved: R_E at most 1.5 on the same node and one node ahead; today’s placed bracket reads against it as a FAIL to work against. The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment. The chip model: every number labelled measured, modelled or claimed, the harness and the scoring rules beside it.
It runs the Ethereum virtual machine through revm, so contracts built for Ethereum deploy with familiar tools; the differences (block context, randomness, two-dimensional fees) are documented. Transactions are included in about one second, proven within about a minute at launch, and locked by miners within about two (designed targets). There is no premine, no pre-sale, no treasury taken from emission, no stake anywhere in consensus, and no dependence on any other chain. Mining is built to stay open to anyone with a GPU. The argument rests on the scoring rule's result against placed adversary designs and on the economics, reported separately as energy advantage, economic advantage and response capability. The hourly program is an optional improvement, not the defence. Writing new code, including an emergency fix to the proof system, is the one thing that takes a person, and it activates only on miner signalling.
What carries the chip resistance is the scoring rule's result on the placed adversary rows, plus the economics, reported separately in the chip model below. Three properties feed it. Rotation is an option, not the defence. A new program every hour, drawn from the chain, its memory pattern with it, and rules that change on a schedule fixed at launch. These schedule changes defeat a chip wired for one datapath and need no human fork, but against a programmable chip that stores the dataset every drawn parameter is firmware, so the security argument does not rest on them. What meets that chip is the latency-shadow work (class v4) and the price per joule (the chip and economy analysis of 6 October 2026, section 5.4; ledger D3). It waits on memory, not maths. Every hash is a chain of random reads into a table too big for a chip to carry. Measured (8 October 2026; lane D’s family harness at the acceptance rule’s own 2^20 sample over 4,900 drawn eras, and the chained-cache pass’s reading of the night before): every hash’s 128 dependent reads land across the whole dataset and the distinct-index floor holds at 0.995 on every accepted program; about half of epochs carry one load site whose address bit at the era’s stride rotation is biased, which prices about 1.6 percent of a hash’s reads to a chip storing half the dataset and nothing to a chip storing all of it; the next class folds the product’s low bits before the rotation, so no era lands a biased bit on an address bit. The wait is the same physics for everyone. Miners hold the switch. Spare defences are written into the rules, switched off. A miner signal turns one on, at the class-change threshold: miners signal three things at three thresholds, 60 percent of blue blocks over two weeks for a parameter genesis leaves open, 90 percent for an upgrade (new code), and 95 percent with a floor height for a class change. No fork.
The work that waits can grow. Class v4 adds a block of latency-shadow arithmetic to every hash, about 100,000 integer operations that run while the memory reads are in flight, so a chip that stores the whole dataset still has to pay for a core. That size sits on a ladder fixed at genesis, six rungs from about 100,000 to about 1,000,000 operations, and it moves one rung at a time only when 90 percent of blue blocks in each of seven consecutive days ask for it; it can never move two rungs inside a week and never past a rung the reference verifier cannot check under 10 ms with its sibling thread busy (measured on the build server, 6 October 2026: the first three rungs pass at 8.8, 8.9 and 9.2 ms, the fourth misses by 0.08 ms on a loaded box and stays out until a quiet re-measurement, the two doublings are out at 12.4 and 15.0 ms). What it buys against a chip is scored under the rule in the chip model below. What it costs, per rung, is measured too: the Apple tier gives up 3 points of rate at the first step and 6 more at the second, the RTX 5090 nothing until the second; so the miners who pay for a step are the ones who take it.
The chip model
-Igneum remains competitive on accessible commodity GPUs even when specialised mining hardware is assumed to exist, remain compatible and seek profit; its security does not rely on identifying that hardware or retiring it through emergency changes. Class v6 adopts the 64-register window and retains it across every rotation. Against a locked RTX 5090 on the same node, two placed-and-routed chip models put a DRAM-board machine at 1.5x to 2.4x per joule, a node ahead 1.8x to 2.8x; the board with SRAM holding the hottest half of the dataset about 1.9x and 2.4x, the SRAM-store die 2.3x and 3.1x, as before (MODELLED, two sources named, no chip measured; the reconciliation is due at 21:00 UK). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment.
+Igneum remains competitive on accessible commodity GPUs even when specialised mining hardware is assumed to exist, remain compatible and seek profit; its security does not rely on identifying that hardware or retiring it through emergency changes. Class v6 adopts the 64-register window and retains it across every rotation. Current modelling estimates a 1.5x to 3.1x energy-efficiency advantage for the specialised designs assessed as complete machines against the GPU tier, from a board on commodity DRAM at 1.5x to an SRAM-store die at 3.1x (1.5x to 2.3x on the GPU's own node). The specialised core alone, placed and routed on ASAP7 with claimed node scaling (plus or minus 15 percent until the two-length solve lands): a 2.8x energy-efficiency advantage a node ahead, 2.4x on the GPU’s own node. The standard’s P04 target as approved: R_E at most 1.5 on the same node and one node ahead; today’s placed bracket reads against it as a FAIL to work against. The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment.
The labels. MODELLED. The GPU side is measured (the RTX 5090 at its 1,300 MHz lock on class v4, 8 October 2026). The chip’s core is placed and routed on ASAP7 with SRAM macros and scaled on claimed node factors; the chip’s memory and the rest of the machine (controller, host share, PSU, VRM, cooling) are modelled; no chip is measured, and the chip’s hardware cost is approximate within 2x. Beside it the coexistence verdict at these energies: the DRAM board passes six of the model’s seven conditions, the hybrid coexists only in a growing chain at cheap GPU electricity, the SRAM die fails the cost, hardware, fleet and margin conditions at its reconciled machine cost, and only private supply in a growing network coexists. The k lane’s own placed row amends the figures if it differs. The GPU side is measured: an RTX 5080 at its 1,100 MHz core lock, 2.06 microjoules per hash, and an RTX 5090 at its 1,300 MHz lock, 2.33 microjoules per hash, both under class v4, on the project’s own rigs and rented pods, 8 October 2026; the card’s cost of the window is measured too (a rented RTX 5090 and RTX 4090 at stock, 8 October 2026: within 5 percent per load with the liveness chain, no register spill). The chip side is synthesised and claimed: the clock-gated sequencer core with the 64-register window on ASAP7, scaled to N3 on the foundry’s headline factors (k about 0.37 at N3 and 0.51 node for node for the base core, the gated window adding about 0.13 of k against an adversary with a flop register file; the window’s liveness measured at 61 of 64 values necessary, its cost to the card measured under 5 percent); the window’s k is synthesis-derived and not a lower bound, and the multi-family adversary lane’s first core (its state in a macro) reads the window’s defence as close to nothing, a disagreement between two models that the placed rows settle. The chip’s memory is modelled: the GDDR7 board of the chip model. The placed gated figure is expected near 2.6x to 3.1x a node ahead and 2.3x to 2.7x node for node (approximate) and is served when its row lands.
The dataset policy (PROPOSED; the genesis size is the founder’s decision, pending). The dataset’s size is a one-off hardware ticket on specialised designs and a running energy tax on commodity cards: at 4 to 5.5 GiB a locked Blackwell card pays 12 to 14 percent more energy per hash than at 1 GiB (an 8 GB AMD card under 3 percent of rate), while the board on commodity DRAM pays nothing and the SRAM designs pay a hardware cost that does not change their outcome. So the genesis size is the founder’s decision on that scoring, pending (this lane’s recommendation 4 GiB, the largest size that keeps every entry card and a 12 GB card’s mining and proving together), and every later step is scored at 5 percent against it and taken only when the chain’s own state outgrows the dataset, not on a calendar. (the card rows measured: an RTX 5090 at its 1,300 MHz lock on the project’s own rig, one paired mapping job, 8 October 2026, the cost the size’s and not the mapping’s; the chip tickets modelled and approximate; later steps’ costs expected, not measured.)
| Dataset | Energy per hash against 1 GiB, at stock | At the 1,300 MHz lock | Cards excluded by memory | SRAM ticket on the hybrid board | SRAM ticket on the die | Labels |
|---|
| Statement | What it says | Label and date |
|---|---|---|
| Energy resistance | Per machine against a locked RTX 5090, node for node and a node ahead: the DRAM board 1.5x to 2.4x (the adversary lane’s placed full core 1.5x, 1.3x to 1.7x; the k lane’s placed base core 2.4x, plus or minus 15 percent) and 1.8x to 2.8x; the board with SRAM holding the hottest half of the dataset 1.9x to 2.1x and 2.4x to 2.6x; the SRAM-store die 2.3x and 3.1x; across the adversary’s lane-count choice the same-node bracket is 1.5x to 2.1x and a node ahead 1.8x to 2.6x, so about 2x on the same node stands at the bracket’s top; per dollar of hardware at list price 3x to 6x (modelled on the placed full 18-family core, routed 8 October 2026, and the 32-lane core’s synthesis). The honest tier moves to the next node with every GPU generation; a chip must tape out again. Whole machine per tier (synthesis with the SRAM band and node factors, claimed; placed rows to follow): the complete GDDR7 machine about 1.8x the RTX 5090 at its lock per joule node for node and 2.1x a node ahead; 1.6x and 1.9x the RTX 5080; 2.8x and 3.3x the Ada, Ampere and RX 9070 XT cohort; about 1.5x the Apple tier, reported, never headlined. | MODELLED: placed and routed core energies against the measured RTX 5090 lock row, 8 October 2026, no chip measured |
| Energy resistance | Per machine against a locked RTX 5090, node for node and a node ahead: the DRAM board 1.5x (1.3x to 1.7x) and 1.8x; the board with SRAM holding the hottest half of the dataset 1.9x to 2.1x and 2.4x to 2.6x; the SRAM-store die 2.3x and 3.1x; across the adversary’s lane-count choice the same-node bracket is 1.5x to 2.1x and a node ahead 1.8x to 2.6x, so about 2x on the same node stands at the bracket’s top; per dollar of hardware at list price 3x to 6x (modelled on the placed full 18-family core, routed 8 October 2026, and the 32-lane core’s synthesis). The honest tier moves to the next node with every GPU generation; a chip must tape out again. Whole machine per tier (synthesis with the SRAM band and node factors, claimed; placed rows to follow): the complete GDDR7 machine about 1.8x the RTX 5090 at its lock per joule node for node and 2.1x a node ahead; 1.6x and 1.9x the RTX 5080; 2.8x and 3.3x the Ada, Ampere and RX 9070 XT cohort; about 1.5x the Apple tier, reported, never headlined. | MODELLED: placed and routed core energies against the measured RTX 5090 lock row, 8 October 2026, no chip measured |
| Economic resistance | Whether a chip gets built depends on development cost, deployment economics and productive hardware lifetime. The first cut of the profitability surface: the price at which a project pays scales as the project cost over its share of the chain times its discounted life, and moves by under 5 percent with the per-joule edge; a fixed-lane chip under rotation needs 4x the price a programmable one needs. No threshold is the headline: the five-year coexistence model (Deliverable 4; its first run is docs/analysis/class-v6/coexistence-model.md, every row modelled) replaces any capex wall: the DRAM board passes six of its seven success conditions at a one to three year life; the SRAM die fails four conditions at its reconciled machine cost; the larger half of a chip's edge is capital cost per accepted hash, not joules. The result, as the model words it: A specialised supplier may earn a normal return; ordinary GPUs remain sufficiently close in total cost, widely obtainable and useful outside mining that new operators can still compete. On today's modelled rows that holds for the chip anyone can build, a stored-dataset board on commodity DRAM, at a productive life of one to three years: its cost per accepted unit of work sits within the range of the best GPU owner and entrant, it passes six of the seven conditions (a third of the network in boards now costs less than a year's revenue at the final hardware price), and a fleet of it holds a minority of the network with GPU entrants still setting the price. For the SRAM-store die the outcome turns on its hardware cost per unit of work, not its energy advantage: at the reconciled machine cost, set by the power train and the shadow core rather than the die, it fails the cost, hardware, fleet and margin conditions at every point of the band, a modest fleet holds about two fifths of a growing network and three fifths of a flat one on arrival and takes every flat or shrinking network within five years, and the only coexistence-shaped outcome is private supply in a growing network; what holds it is the investment decision, since its economics are project economics. A third design, a DRAM board with the hottest half of the dataset in on-board SRAM, sits between the two: it coexists only in a growing network at cheap GPU electricity and fails the cost conditions in a flat or shrinking one, and the dataset's size floor is a real lever on it where it was none on the SRAM die. What holds the die is the investment decision, not the hash; every chip figure here is modelled, not measured, and the chip's hardware cost per unit of work is approximate within 2x. The model holds under every market structure for the DRAM board (private supply, hardware sales, multiple suppliers, with no single supplier above a quarter of the network), and the SRAM die under none but private supply in a growing network; the thresholds live in the model's sensitivity workbook (docs/analysis/class-v6/coexistence-workbook.md), never on a page. A failure, reported as found: ECO-05, the standard’s coexistence sweep, was run on a register frozen before any result against a sourced revenue reference of USD 31.65 million a year of miner revenue (Ethereum Classic’s trailing year at its current era 6 reward) and FAILS the envelope as the chain stands. Of sixteen revenue and tariff worlds (a quarter, one, four and ten times the reference; electricity at 3, 10, 25 and 40 cents per kilowatt-hour) only one sustains new entry across two vendors, ten times the reference at 3 cents (about USD 316 million a year), because on this hash the measured AMD and Intel cards cost four to six times a Blackwell card per joule and never earn a new entrant’s purchase back at list price below that world; in that one world no specialised design sits inside the envelope against the whole cohort (the board on commodity DRAM is within the envelope only against the best Blackwell card, the die and the hybrid against no card of today’s), and the quarter-reference worlds at 25 and 40 cents are collapse worlds with no rational profitable operator. What moves the result is the specialist’s hardware cost per unit of work, the honest cards’ own efficiency on this hash, above all the AMD and Intel cards’ energy, and the dataset’s size floor; not a smaller network, a higher token price or any chip’s death. Reported as found; the register, the full result cube and the model are published for independent reproduction. (Labels: the register frozen at 18:37 UK on 8 October 2026, the reference corrected by a second public read and the run repeated with the verdict unchanged, the cube MODELLED on measured card rows, two cohort rows BLOCKED, the RX 7600’s knee and the Arc’s watts, their measurement running tonight; the registry row ECO-05 on /acceptance; the results file docs/analysis/class-v6/eco-05-results.md.) | MODELLED, the coexistence model's first run, 8 October 2026 |
| Response capability | Rotation is an optional improvement, not the mechanism. A passed rotation boundary proves the rotation works, not that hardware dies. The schedule: a new program every hour, a parameter era every week, a family epoch every 180 days, an emergency vote when miners call one. Rotation costs a chip versatility, not life: the family bank is firmware plus about 43 percent of core cells, and no transition carries an obsolescence credit (modelled). | measured per boundary, 8 October 2026; the family-bank cost modelled, 8 October 2026 |
Here are the limits, stated before anyone else states them.
- A proof in seconds. Not at launch. Proving a full block today needs a cluster of 100 to 200 consumer GPUs, approximate, so Igneum launches with proofs within about a minute and tightens as hardware improves. Users still see their transaction land in one second. -
- A chip is impossible. No. Igneum assumes a chip exists. A programmable chip is not stopped by the moving target: everything it needs is public at genesis and every drawn parameter is firmware to it (an address permute, a rotator, an immediate table), so the defence against it is the latency-shadow work (class v4) and the price per joule, not the schedule (the chip and economy analysis of 6 October 2026, section 5.4; ledger D3). Igneum remains competitive on accessible commodity GPUs even when specialised mining hardware is assumed to exist, remain compatible and seek profit; its security does not rely on identifying that hardware or retiring it through emergency changes. Class v6 adopts the 64-register window and retains it across every rotation. Against a locked RTX 5090 on the same node, two placed-and-routed chip models put a DRAM-board machine at 1.5x to 2.4x per joule, a node ahead 1.8x to 2.8x; the board with SRAM holding the hottest half of the dataset about 1.9x and 2.4x, the SRAM-store die 2.3x and 3.1x, as before (MODELLED, two sources named, no chip measured; the reconciliation is due at 21:00 UK). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment. The labels: the bracket modelled, approximate and provisional (the GPU side measured on the RTX 5080 and RTX 5090 at their core locks under class v4, 8 October 2026; the chip core synthesised on ASAP7 and scaled to N3, claimed, its placed gated row pending; its memory modelled). Class v5 makes the dataset the chain’s own state, so a chip that stores it or recomputes it is wrong on every item (designed, 7 October 2026; under evaluation (Deliverable 3), not counted as a defence until justified or dropped). The strongest recompute chip we can price, holding the whole 256 MiB cache on-die, reaches under 1x per chip against an RTX 5090 (the published model, 5 October 2026: 0.92x per unit of silicon with a 3x fixed-function allowance, approximate). Sources: the class v6 close, section 10 (8 October 2026); the ASIC history’s Ethash rows; the chip model analysis (6 October 2026). No hash has stayed free of chips forever; Igneum does not claim to. Monero’s RandomX has held its miners on commodity hardware for about seven years: one chip shipped against it, Bitmain’s Antminer X5 (September 2023), an observed comparison, not a ceiling; the one announced beyond it, the Antminer X9, was withdrawn in mid-May 2026 before any unit shipped, its claimed core never measured; RandomX v2 was released on 25 March 2026 with its activation pending. That record says nothing about the price of a chip with the 256 MB cache on its die; that price is a cost model, not a measurement. +
- A chip is impossible. No. Igneum assumes a chip exists. A programmable chip is not stopped by the moving target: everything it needs is public at genesis and every drawn parameter is firmware to it (an address permute, a rotator, an immediate table), so the defence against it is the latency-shadow work (class v4) and the price per joule, not the schedule (the chip and economy analysis of 6 October 2026, section 5.4; ledger D3). Igneum remains competitive on accessible commodity GPUs even when specialised mining hardware is assumed to exist, remain compatible and seek profit; its security does not rely on identifying that hardware or retiring it through emergency changes. Class v6 adopts the 64-register window and retains it across every rotation. Current modelling estimates a 1.5x to 3.1x energy-efficiency advantage for the specialised designs assessed as complete machines against the GPU tier, from a board on commodity DRAM at 1.5x to an SRAM-store die at 3.1x (1.5x to 2.3x on the GPU's own node). The specialised core alone, placed and routed on ASAP7 with claimed node scaling (plus or minus 15 percent until the two-length solve lands): a 2.8x energy-efficiency advantage a node ahead, 2.4x on the GPU’s own node. The standard’s P04 target as approved: R_E at most 1.5 on the same node and one node ahead; today’s placed bracket reads against it as a FAIL to work against. The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment. The labels: the bracket modelled, approximate and provisional (the GPU side measured on the RTX 5080 and RTX 5090 at their core locks under class v4, 8 October 2026; the chip core synthesised on ASAP7 and scaled to N3, claimed, its placed gated row pending; its memory modelled). Class v5 makes the dataset the chain’s own state, so a chip that stores it or recomputes it is wrong on every item (designed, 7 October 2026; under evaluation (Deliverable 3), not counted as a defence until justified or dropped). The strongest recompute chip we can price, holding the whole 256 MiB cache on-die, reaches under 1x per chip against an RTX 5090 (the published model, 5 October 2026: 0.92x per unit of silicon with a 3x fixed-function allowance, approximate). Sources: the class v6 close, section 10 (8 October 2026); the ASIC history’s Ethash rows; the chip model analysis (6 October 2026). No hash has stayed free of chips forever; Igneum does not claim to. Monero’s RandomX has held its miners on commodity hardware for about seven years: one chip shipped against it, Bitmain’s Antminer X5 (September 2023), an observed comparison, not a ceiling; the one announced beyond it, the Antminer X9, was withdrawn in mid-May 2026 before any unit shipped, its claimed core never measured; RandomX v2 was released on 25 March 2026 with its activation pending. That record says nothing about the price of a chip with the 256 MB cache on its die; that price is a cost model, not a measurement.
- A guaranteed income floor. No. External proving is a small market today. Igneum's miners' electricity cost in it is close to power, but the price they must charge is the subsidy they forgo, which falls as one over network hash: an edge at scale and nothing more.
- A memory-hard prototype on every vendor. Not yet. The 256 MB cache closed the shortcut on Apple silicon (computing items runs 4.8x slower than loading them, measured 3 October 2026). The same ratio on NVIDIA and on a discrete AMD card is Open.
- Finality in the first month. No. No checkpoint locks until the 30-day window has 30 days of history. The first month of mainnet is proof of work with a 12-hour depth, and the text above says so wherever a day count appears. diff --git a/site/miner.html b/site/miner.html index 5acc4ca17..3ed28db96 100644 --- a/site/miner.html +++ b/site/miner.html @@ -335,7 +335,7 @@ pre b{color:var(--molten-text);font-weight:500}
Graphics cards only. A new mining program every hour, so no chip is built for it. 80% of every block to the card that finds it, 20% to the cards that prove it. No premine, no stake, no fee to any team. Every number above has a row in the bench table.
-Your card against the strongest chip we can price. Igneum remains competitive on accessible commodity GPUs even when specialised mining hardware is assumed to exist, remain compatible and seek profit; its security does not rely on identifying that hardware or retiring it through emergency changes. Class v6 adopts the 64-register window and retains it across every rotation. Against a locked RTX 5090 on the same node, two placed-and-routed chip models put a DRAM-board machine at 1.5x to 2.4x per joule, a node ahead 1.8x to 2.8x; the board with SRAM holding the hottest half of the dataset about 1.9x and 2.4x, the SRAM-store die 2.3x and 3.1x, as before (MODELLED, two sources named, no chip measured; the reconciliation is due at 21:00 UK). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment. The GPU side is measured: the RTX 5090 at its 1,300 MHz lock, 2.33 microjoules per hash on class v4, the window’s cost within 5 percent per load (8 October 2026); the chip’s core is placed and routed on ASAP7 with SRAM macros and scaled on claimed node factors; its memory and the rest of the machine (controller, host share, PSU, VRM, cooling) are modelled; no chip is measured and the chip’s hardware cost is approximate within 2x (MODELLED). Under class v5 the chip is wrong on every item because the dataset is the chain’s own state (designed). Every number with its label, the harness and the scoring rules.
+Your card against the strongest chip we can price. Igneum remains competitive on accessible commodity GPUs even when specialised mining hardware is assumed to exist, remain compatible and seek profit; its security does not rely on identifying that hardware or retiring it through emergency changes. Class v6 adopts the 64-register window and retains it across every rotation. Current modelling estimates a 1.5x to 3.1x energy-efficiency advantage for the specialised designs assessed as complete machines against the GPU tier, from a board on commodity DRAM at 1.5x to an SRAM-store die at 3.1x (1.5x to 2.3x on the GPU's own node). The specialised core alone, placed and routed on ASAP7 with claimed node scaling (plus or minus 15 percent until the two-length solve lands): a 2.8x energy-efficiency advantage a node ahead, 2.4x on the GPU’s own node. The standard’s P04 target as approved: R_E at most 1.5 on the same node and one node ahead; today’s placed bracket reads against it as a FAIL to work against. The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment. The GPU side is measured: the RTX 5090 at its 1,300 MHz lock, 2.33 microjoules per hash on class v4, the window’s cost within 5 percent per load (8 October 2026); the chip’s core is placed and routed on ASAP7 with SRAM macros and scaled on claimed node factors; its memory and the rest of the machine (controller, host share, PSU, VRM, cooling) are modelled; no chip is measured and the chip’s hardware cost is approximate within 2x (MODELLED). Under class v5 the chip is wrong on every item because the dataset is the chain’s own state (designed). Every number with its label, the harness and the scoring rules.