The energy-against-size curve beside the pending dataset policy (1, 2, 4, 5.5 GiB at stock and at the lock, the exclusions by memory, the SRAM tickets; every cell labelled) on the litepaper, cited by the facts row

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

site/litepaper.html

@@ -469,6 +469,14 @@ body.all .pager{display:none}
         <p><b>Igneum remains competitive on accessible commodity GPUs even when specialised mining hardware is assumed to exist, remain compatible and seek profit; its security does not rely on identifying that hardware or retiring it through emergency changes.</b> Class v6 adopts the 64-register window and retains it across every rotation. Current modelling estimates a 1.5x to 3.1x energy-efficiency advantage for the specialised designs assessed as complete machines against the GPU tier, from a board on commodity DRAM at 1.5x to an SRAM-store die at 3.1x (1.5x to 2.3x on the GPU's own node). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment.</p>
         <p><b>The labels.</b> MODELLED. The GPU side is measured (the RTX 5090 at its 1,300 MHz lock on class v4, 8 October 2026). The chip’s core is placed and routed on ASAP7 with SRAM macros and scaled on claimed node factors; the chip’s memory and the rest of the machine (controller, host share, PSU, VRM, cooling) are modelled; no chip is measured, and the chip’s hardware cost is approximate within 2x. Beside it the coexistence verdict at these energies: the DRAM board passes six of the model’s seven conditions, the hybrid coexists only in a growing chain at cheap GPU electricity, the SRAM die fails the cost, hardware, fleet and margin conditions at its reconciled machine cost, and only private supply in a growing network coexists. The k lane’s own placed row amends the figures if it differs. The GPU side is measured: an RTX 5080 at its 1,100 MHz core lock, 2.06 microjoules per hash, and an RTX 5090 at its 1,300 MHz lock, 2.33 microjoules per hash, both under class v4, on the project’s own rigs and rented pods, 8 October 2026; the card’s cost of the window is measured too (a rented RTX 5090 and RTX 4090 at stock, 8 October 2026: within 5 percent per load with the liveness chain, no register spill). The chip side is synthesised and claimed: the clock-gated sequencer core with the 64-register window on ASAP7, scaled to N3 on the foundry’s headline factors (k about 0.37 at N3 and 0.51 node for node for the base core, the gated window adding about 0.13 of k against an adversary with a flop register file; the window’s liveness measured at 61 of 64 values necessary, its cost to the card measured under 5 percent); the window’s k is synthesis-derived and not a lower bound, and the multi-family adversary lane’s first core (its state in a macro) reads the window’s defence as close to nothing, a disagreement between two models that the placed rows settle. The chip’s memory is modelled: the GDDR7 board of the chip model. The placed gated figure is expected near 2.6x to 3.1x a node ahead and 2.3x to 2.7x node for node (approximate) and is served when its row lands.</p>
         <p><b>The dataset policy (PROPOSED; the genesis size is the founder’s decision, pending).</b> The dataset’s size is a one-off hardware ticket on specialised designs and a running energy tax on commodity cards: at 4 to 5.5 GiB a locked Blackwell card pays 12 to 14 percent more energy per hash than at 1 GiB (an 8 GB AMD card under 3 percent of rate), while the board on commodity DRAM pays nothing and the SRAM designs pay a hardware cost that does not change their outcome. The genesis size is scored by adversary burden against commodity burden and is the founder’s decision, pending; no size is served as decided here. Every later step is scored under the standard’s 5 percent GPU-cost rule and taken only when the chain’s own state outgrows the dataset, not on a calendar. (the card rows measured: an RTX 5090 at its 1,300 MHz lock on the project’s own rig, one paired mapping job, 8 October 2026, the cost the size’s and not the mapping’s; the chip tickets modelled and approximate; later steps’ costs expected, not measured.)</p>
+        <div class="tbl"><table><thead><tr><th>Dataset</th><th>Energy per hash against 1 GiB, at stock</th><th>At the 1,300 MHz lock</th><th>Cards excluded by memory</th><th>SRAM ticket on the hybrid board</th><th>SRAM ticket on the die</th><th>Labels</th></tr></thead><tbody>
+          <tr><td>1 GiB (class v4 today)</td><td>the control</td><td>the control</td><td>none</td><td>USD 125</td><td>one reticle, USD 500</td><td>measured; modelled</td></tr>
+          <tr><td>2 GiB (class v5’s designed size)</td><td>about +1 percent</td><td>about +4 percent (the morning’s run; a paired read in flight)</td><td>none (an 8 GB card holds it)</td><td>USD 250</td><td>one reticle, USD 500</td><td>measured; modelled</td></tr>
+          <tr><td>4 GiB</td><td>+0.7 percent</td><td>+11.7 percent</td><td>none by memory (an 8 GB AMD card measured -2.6 percent of rate; a 12 GB card loses mine-and-prove co-residence)</td><td>USD 500</td><td>two reticles, USD 1,000</td><td>measured (paired, 8 October 2026, 18:2x UK); modelled</td></tr>
+          <tr><td>5.5 GiB</td><td>+4.3 percent</td><td>+13.4 percent</td><td>none by memory (an 8 GB card holds it with 1.8 GB spare, measured -2.5 percent of rate; a 12 GB card loses mine-and-prove co-residence)</td><td>USD 690</td><td>three reticles, USD 1,500</td><td>measured (paired, 8 October 2026, 18:2x UK); modelled</td></tr>
+        </tbody></table></div>
+        <p class="src">The energy columns are measured on an RTX 5090 on the project’s own rig, 8 October 2026, against its own 1 GiB control at stock and at the 1,300 MHz lock (250 batches of 2^24, fingerprints equal across sizes); the exclusions are by memory on the reference population, measured where a card ran the size; the SRAM tickets are modelled (the hybrid’s hot-half store at about USD 250 per GiB of N2 SRAM; the die’s reticle count at USD 500 a reticle, claimed). A locked card pays the size as energy, a specialised design as a one-off ticket; on the measured rows the knee cost saturates above a few gigabytes (about 12 to 14 percent at 4 to 5.5 GiB) and no size moves a specialised design’s economic outcome. The board on commodity DRAM pays nothing at any size (modelled).</p>
+
         <p>Three statements, kept separate. The baseline is the hash as it stands under the scoring rule; rotation is an optional improvement to that baseline, not the mechanism the claim rests on.</p>
         <div class="tbl"><table><thead><tr><th>Statement</th><th>What it says</th><th>Label and date</th></tr></thead><tbody>
           <tr><td>Energy resistance</td><td>Per machine against a locked RTX 5090, node for node and a node ahead: the DRAM board 1.5x to 1.6x (1.3x to 1.7x) and 1.8x; the board with SRAM holding the hottest half of the dataset 1.9x to 2.1x and 2.4x to 2.6x; the SRAM-store die 2.3x and 3.1x; across the adversary’s lane-count choice the same-node bracket is 1.5x to 2.1x and a node ahead 1.8x to 2.6x, so about 2x on the same node stands at the bracket’s top; per dollar of hardware at list price 3x to 6x (modelled on the placed full 18-family core, routed 8 October 2026, and the 32-lane core’s synthesis). The honest tier moves to the next node with every GPU generation; a chip must tape out again. Whole machine per tier (synthesis with the SRAM band and node factors, claimed; placed rows to follow): the complete GDDR7 machine about 1.8x the RTX 5090 at its lock per joule node for node and 2.1x a node ahead; 1.6x and 1.9x the RTX 5080; 2.8x and 3.3x the Ada, Ampere and RX 9070 XT cohort; about 1.5x the Apple tier, reported, never headlined.</td><td>MODELLED: placed and routed core energies against the measured RTX 5090 lock row, 8 October 2026, no chip measured</td></tr>