diff --git a/docs/evidence.md b/docs/evidence.md index 3b1ac8331..c20e5dff7 100644 --- a/docs/evidence.md +++ b/docs/evidence.md @@ -38,7 +38,7 @@ Every row carries its release evidence packet at the end of its Result cell: par | 3 | The 64-register window per lane costs a GPU under 1 percent of rate at stock, and at most 5 percent per load with the liveness chain | The litepaper (class v6); `docs/plans/igneum-2.0.md` D1 (the placed 64-register rows) | TEAM-REPORTED; tested by the team | `docs/analysis/class-v6/connected-state.md` section 4; `docs/design/class-v6-rotating-family.md` section 10.0e | The class v5 nvcc harness and the kit worker, both packs on the same card minutes apart, 250 batches of 2^24, nvidia-smi at 1 Hz, vectors PASS on every row (`connected-state.md` section 4); the per-load rows of the full chain against the base (`class-v6-rotating-family.md` 10.0e) | 8 October 2026, rented RTX 5090 (575 W cap) and RTX 4090 (450 W cap) at stock: energy per hash +0.6 percent on the RTX 5090 and -0.9 percent on the RTX 4090, inside the run-to-run noise; under 1 percent of rate; 80 to 87 registers per thread, no spill (all measured). Per load: RTX 5090 16.7 nJ base, 17.6 nJ full chain; RTX 4090 26.0 nJ, 27.0 nJ (measured). The lock row on the project's own rigs is owed | none yet. Packet: parameters a rented RTX 5090 and RTX 4090 at stock, the liveness chain, class v4; procedure the hash lane's harness rows in connected-state.md section 4; raw result energy per hash +0.6 percent and -0.9 percent, at most 5 percent per load; reproduction none yet; review scope none; unresolved two cards, one day, no AMD or Apple row | | 4 | Reorganising the same work around live state (the connected-state variant, experiment D2(a)) does not reduce a specialised chip's edge: KILL as a class | `docs/plans/igneum-2.0.md` D2(a); this page | TEAM-REPORTED; tested by the team (a published failure) | `docs/analysis/class-v6/connected-state.md` (the verdict, section 6) | The census, liveness and GPU rows in `connected-state.md` sections 2 to 4; the chip side priced on the drawn program by synthesis (a model, never a lower bound) | 8 October 2026, verdict 17:25 UK: the window is necessary (63 of 64 registers live at every address, measured) but only its width reaches the chip, +1.2 pJ per lane-op at N5 (synthesised); the window moves the chip's edge 1.10x node for node against a 1.25x gate (modelled); the GPU side +0.6 percent energy per hash on the RTX 5090, -0.9 percent on the RTX 4090 at stock (measured). Rearranging the dependency graph of the same operations moves neither side | none yet. Packet: parameters the connected-state generator variant behind a flag, the census TSVs; procedure connected-state.md; raw result +1.2 pJ per lane-op at N5 on the chip side, the GPU side unmoved; reproduction none yet; review scope none; unresolved the chip side is modelled, not measured | | 5 | "A GPU-secured network for Ethereum-compatible applications and verifiable computation." served on every page | Every page | PROPOSED; designed (served) | `docs/plans/igneum-2.0.md` (the objective: the positioning line) | `node tools/ci/ledger-text-check.mjs`: the sentence pinned (R0) on the home page, the litepaper and this page | 8 October 2026: on this page; the home page and the litepaper carry it as their 2.0 text lands (designed) | none yet. Packet: parameters none (a served sentence); procedure the ledger-text check pins it on every page; raw result the check's count; reproduction not applicable; review scope the three external reviews the founder accepted; unresolved none | -| 6 | The chip claim as served: "Igneum remains competitive on accessible commodity GPUs even when specialised mining hardware is assumed to exist, remain compatible and seek profit; its security does not rely on identifying that hardware or retiring it through emergency changes." Under it the three statements, separate: energy ("Current modelling estimates a 1.5x to 3.1x energy-efficiency advantage for the specialised designs assessed as complete machines against the GPU tier, from a board on commodity DRAM at 1.5x to an SRAM-store die at 3.1x (1.5x to 2.3x on the GPU's own node)." Per machine on the same node and a node ahead: the DRAM board 1.5x to 1.6x and 1.8x, the hybrid 1.9x to 2.1x and 2.4x to 2.6x, the die 2.3x and 3.1x; across the adversary's lane-count choice the same-node bracket is 1.5x to 2.1x and a node ahead 1.8x to 2.6x; 3x to 6x per dollar of hardware at list price. MODELLED: the GPU side measured, the chip's core placed and routed, the rest of the machine modelled, no chip measured, hardware cost approximate within 2x), economic and response capability, rotation an optional improvement. Class v5 derives the dataset from chain state; whether that excludes a specialised design is under evaluation (Deliverable 3), since a design that tracks state is not excluded by staleness. The dataset policy (PROPOSED; the genesis size is the founder's decision, pending; no size served as decided): "The dataset’s size is a one-off hardware ticket on specialised designs and a running energy tax on commodity cards: at 4 to 5.5 GiB a locked Blackwell card pays 12 to 14 percent more energy per hash than at 1 GiB (an 8 GB AMD card under 3 percent of rate), while the board on commodity DRAM pays nothing and the SRAM designs pay a hardware cost that does not change their outcome. The genesis size is scored by adversary burden against commodity burden and is the founder’s decision, pending; no size is served as decided here. Every later step is scored under the standard’s 5 percent GPU-cost rule and taken only when the chain’s own state outgrows the dataset, not on a calendar." (PROPOSED; the card rows measured, the tickets modelled and approximate). The energy ratio is not the pass criterion: the coexistence model ([docs/analysis/class-v6/coexistence-model.md](https://git.igneum.network/igneum-network/igneum/src/branch/master/docs/analysis/class-v6/coexistence-model.md)) is, and its first run's result is served with its conditions: A specialised supplier may earn a normal return; ordinary GPUs remain sufficiently close in total cost, widely obtainable and useful outside mining that new operators can still compete. On today's modelled rows that holds for the chip anyone can build, a stored-dataset board on commodity DRAM, at a productive life of one to three years: its cost per accepted unit of work sits within the range of the best GPU owner and entrant, it passes six of the seven conditions (a third of the network in boards now costs less than a year's revenue at the final hardware price), and a fleet of it holds a minority of the network with GPU entrants still setting the price. For the SRAM-store die the outcome turns on its hardware cost per unit of work, not its energy advantage: at the reconciled machine cost, set by the power train and the shadow core rather than the die, it fails the cost, hardware, fleet and margin conditions at every point of the band, a modest fleet holds about two fifths of a growing network and three fifths of a flat one on arrival and takes every flat or shrinking network within five years, and the only coexistence-shaped outcome is private supply in a growing network; what holds it is the investment decision, since its economics are project economics. A third design, a DRAM board with the hottest half of the dataset in on-board SRAM, sits between the two: it coexists only in a growing network at cheap GPU electricity and fails the cost conditions in a flat or shrinking one, and the dataset's size floor is a real lever on it where it was none on the SRAM die. What holds the die is the investment decision, not the hash; every chip figure here is modelled, not measured, and the chip's hardware cost per unit of work is approximate within 2x. | The litepaper (the chip model) | MODELLED; designed (the bracket modelled; the GPU side tested by the team) | `docs/design/class-v6-rotating-family.md` section 10 (10.0h to 10.0n, 8 October 2026); `docs/plans/igneum-2.0.md` D3 and D4 | the scoring rule in the close (the minimum over workloads of the maximum over free adversarial designs of the GPU's joules per hash over the adversary's, under the 10 percent GPU-cost budget at the lock, the verifier limit, cross-vendor correctness and hardware accessibility); the placed rows are D3's | the GPU side measured: the RTX 5080 at its 1,100 MHz lock 2.06 microjoules per hash and the RTX 5090 at its 1,300 MHz lock 2.33 (8 October 2026, the project's own rigs and rented pods); the chip side synthesised and claimed, its placed gated row pending | none yet. Packet: parameters the placed full 18-family core on ASAP7, claimed node scaling, the GDDR7 board, the RTX 5090 at its 1,300 MHz lock on class v4; procedure class-v6-rotating-family.md section 10 and coexistence-model.md; raw result the energies and verdicts as served; reproduction none yet; review scope three external reviews of the close, findings taken; unresolved no chip measured, hardware cost approximate within 2x, the k lane's 32-lane placed row pending | +| 6 | The chip claim as served: "Igneum remains competitive on accessible commodity GPUs even when specialised mining hardware is assumed to exist, remain compatible and seek profit; its security does not rely on identifying that hardware or retiring it through emergency changes." Under it the three statements, separate: energy ("Current modelling estimates a 1.5x to 3.1x energy-efficiency advantage for the specialised designs assessed as complete machines against the GPU tier, from a board on commodity DRAM at 1.5x to an SRAM-store die at 3.1x (1.5x to 2.3x on the GPU's own node)." Per machine on the same node and a node ahead: the DRAM board 1.5x to 1.6x and 1.8x, the hybrid 1.9x to 2.1x and 2.4x to 2.6x, the die 2.3x and 3.1x; across the adversary's lane-count choice the same-node bracket is 1.5x to 2.1x and a node ahead 1.8x to 2.6x; 3x to 6x per dollar of hardware at list price. MODELLED: the GPU side measured, the chip's core placed and routed, the rest of the machine modelled, no chip measured, hardware cost approximate within 2x), economic and response capability, rotation an optional improvement. Class v5 derives the dataset from chain state; whether that excludes a specialised design is under evaluation (Deliverable 3), since a design that tracks state is not excluded by staleness. The dataset policy (PROPOSED; the genesis size is the founder's decision, pending; no size served as decided): "The dataset’s size is a one-off hardware ticket on specialised designs and a running energy tax on commodity cards: at 4 to 5.5 GiB a locked Blackwell card pays 12 to 14 percent more energy per hash than at 1 GiB (an 8 GB AMD card under 3 percent of rate), while the board on commodity DRAM pays nothing and the SRAM designs pay a hardware cost that does not change their outcome. The genesis size is scored by adversary burden against commodity burden and is the founder’s decision, pending; no size is served as decided here. Every later step is scored under the standard’s 5 percent GPU-cost rule and taken only when the chain’s own state outgrows the dataset, not on a calendar." (PROPOSED; the energy-against-size curve on the litepaper: 1, 2, 4 and 5.5 GiB at stock and at the lock measured on an RTX 5090 against its own 1 GiB control, +0.7 and +4.3 percent at stock, +11.7 and +13.4 at the lock for 4 and 5.5 GiB, the 2 GiB knee cell a paired read in flight; the exclusions by memory; the SRAM tickets modelled). The energy ratio is not the pass criterion: the coexistence model ([docs/analysis/class-v6/coexistence-model.md](https://git.igneum.network/igneum-network/igneum/src/branch/master/docs/analysis/class-v6/coexistence-model.md)) is, and its first run's result is served with its conditions: A specialised supplier may earn a normal return; ordinary GPUs remain sufficiently close in total cost, widely obtainable and useful outside mining that new operators can still compete. On today's modelled rows that holds for the chip anyone can build, a stored-dataset board on commodity DRAM, at a productive life of one to three years: its cost per accepted unit of work sits within the range of the best GPU owner and entrant, it passes six of the seven conditions (a third of the network in boards now costs less than a year's revenue at the final hardware price), and a fleet of it holds a minority of the network with GPU entrants still setting the price. For the SRAM-store die the outcome turns on its hardware cost per unit of work, not its energy advantage: at the reconciled machine cost, set by the power train and the shadow core rather than the die, it fails the cost, hardware, fleet and margin conditions at every point of the band, a modest fleet holds about two fifths of a growing network and three fifths of a flat one on arrival and takes every flat or shrinking network within five years, and the only coexistence-shaped outcome is private supply in a growing network; what holds it is the investment decision, since its economics are project economics. A third design, a DRAM board with the hottest half of the dataset in on-board SRAM, sits between the two: it coexists only in a growing network at cheap GPU electricity and fails the cost conditions in a flat or shrinking one, and the dataset's size floor is a real lever on it where it was none on the SRAM die. What holds the die is the investment decision, not the hash; every chip figure here is modelled, not measured, and the chip's hardware cost per unit of work is approximate within 2x. | The litepaper (the chip model) | MODELLED; designed (the bracket modelled; the GPU side tested by the team) | `docs/design/class-v6-rotating-family.md` section 10 (10.0h to 10.0n, 8 October 2026); `docs/plans/igneum-2.0.md` D3 and D4 | the scoring rule in the close (the minimum over workloads of the maximum over free adversarial designs of the GPU's joules per hash over the adversary's, under the 10 percent GPU-cost budget at the lock, the verifier limit, cross-vendor correctness and hardware accessibility); the placed rows are D3's | the GPU side measured: the RTX 5080 at its 1,100 MHz lock 2.06 microjoules per hash and the RTX 5090 at its 1,300 MHz lock 2.33 (8 October 2026, the project's own rigs and rented pods); the chip side synthesised and claimed, its placed gated row pending | none yet. Packet: parameters the placed full 18-family core on ASAP7, claimed node scaling, the GDDR7 board, the RTX 5090 at its 1,300 MHz lock on class v4; procedure class-v6-rotating-family.md section 10 and coexistence-model.md; raw result the energies and verdicts as served; reproduction none yet; review scope three external reviews of the close, findings taken; unresolved no chip measured, hardware cost approximate within 2x, the k lane's 32-lane placed row pending | | 7 | Mining and proving together on one card needs a 16 GB card at the proposed 5.5 GiB dataset (the genesis size is pending the founder’s decision; at a smaller dataset the miner holds less and the rule is not yet measured): the miner holds about 6.1 GiB and a compressed shard proof peaks at about 7.5 GiB, so 8 GB and 12 GB cards time-share (the app pauses the miner for the proof). NVIDIA proves; AMD and Apple mine | The litepaper (Proving, vs RandomX); the miner page | TEAM-REPORTED; tested by the team | `docs/analysis/class-v6/coexist-rows.md` (the 5.5 GiB ds55 miner beside igneum-prove-host-0317, compressed at threshold 2^26, the served sm_86 and sm_89 floors) | the RESULT rows in that file, verbatim from the runs | rented RTX 3060 12 GB: 26.82 MH/s at 117.4 W with 6,129 MiB resident; the compressed shard 13.2 s, peak 7,525 MiB (6,129 + 7,525 = 13,654 MiB against 12,288); rented RTX 4060 8 GB: 18.84 MH/s, 6,116 MiB resident; the shard 8.2 s, peak 7,532 MiB; 8 October 2026 | none yet. Packet: parameters the 5.5 GiB ds55 miner, igneum-prove-host-0317 compressed at threshold 2^26, sm_86 and sm_89; procedure coexist-rows.md; raw result the RESULT rows verbatim; reproduction none yet; review scope none; unresolved two cards on one day, the 6 October rows stand as 1 GiB-dataset rows | ## Count by status diff --git a/site/evidence.html b/site/evidence.html index 5a3f96003..ec3efaf61 100644 --- a/site/evidence.html +++ b/site/evidence.html @@ -272,7 +272,7 @@ td.mono{font-family:var(--f-mono);font-size:12.5px;min-width:180px}td.iv{color:v 3The 64-register window per lane costs a GPU under 1 percent of rate at stock, and at most 5 percent per load with the liveness chain
The litepaper (class v6); docs/plans/igneum-2.0.md D1 (the placed 64-register rows)
TEAM-REPORTED; tested by the teamdocs/analysis/class-v6/connected-state.md section 4; docs/design/class-v6-rotating-family.md section 10.0eThe class v5 nvcc harness and the kit worker, both packs on the same card minutes apart, 250 batches of 2^24, nvidia-smi at 1 Hz, vectors PASS on every row (connected-state.md section 4); the per-load rows of the full chain against the base (class-v6-rotating-family.md 10.0e)8 October 2026, rented RTX 5090 (575 W cap) and RTX 4090 (450 W cap) at stock: energy per hash +0.6 percent on the RTX 5090 and -0.9 percent on the RTX 4090, inside the run-to-run noise; under 1 percent of rate; 80 to 87 registers per thread, no spill (all measured). Per load: RTX 5090 16.7 nJ base, 17.6 nJ full chain; RTX 4090 26.0 nJ, 27.0 nJ (measured). The lock row on the project's own rigs is owednone yet. Packet: parameters a rented RTX 5090 and RTX 4090 at stock, the liveness chain, class v4; procedure the hash lane's harness rows in connected-state.md section 4; raw result energy per hash +0.6 percent and -0.9 percent, at most 5 percent per load; reproduction none yet; review scope none; unresolved two cards, one day, no AMD or Apple row 4Reorganising the same work around live state (the connected-state variant, experiment D2(a)) does not reduce a specialised chip's edge: KILL as a class
docs/plans/igneum-2.0.md D2(a); this page
TEAM-REPORTED; tested by the team (a published failure)docs/analysis/class-v6/connected-state.md (the verdict, section 6)The census, liveness and GPU rows in connected-state.md sections 2 to 4; the chip side priced on the drawn program by synthesis (a model, never a lower bound)8 October 2026, verdict 17:25 UK: the window is necessary (63 of 64 registers live at every address, measured) but only its width reaches the chip, +1.2 pJ per lane-op at N5 (synthesised); the window moves the chip's edge 1.10x node for node against a 1.25x gate (modelled); the GPU side +0.6 percent energy per hash on the RTX 5090, -0.9 percent on the RTX 4090 at stock (measured). Rearranging the dependency graph of the same operations moves neither sidenone yet. Packet: parameters the connected-state generator variant behind a flag, the census TSVs; procedure connected-state.md; raw result +1.2 pJ per lane-op at N5 on the chip side, the GPU side unmoved; reproduction none yet; review scope none; unresolved the chip side is modelled, not measured 5"A GPU-secured network for Ethereum-compatible applications and verifiable computation." served on every page
Every page
PROPOSED; designed (served)docs/plans/igneum-2.0.md (the objective: the positioning line)node tools/ci/ledger-text-check.mjs: the sentence pinned (R0) on the home page, the litepaper and this page8 October 2026: on this page; the home page and the litepaper carry it as their 2.0 text lands (designed)none yet. Packet: parameters none (a served sentence); procedure the ledger-text check pins it on every page; raw result the check's count; reproduction not applicable; review scope the three external reviews the founder accepted; unresolved none -6The chip claim as served: "Igneum remains competitive on accessible commodity GPUs even when specialised mining hardware is assumed to exist, remain compatible and seek profit; its security does not rely on identifying that hardware or retiring it through emergency changes." Under it the three statements, separate: energy ("Current modelling estimates a 1.5x to 3.1x energy-efficiency advantage for the specialised designs assessed as complete machines against the GPU tier, from a board on commodity DRAM at 1.5x to an SRAM-store die at 3.1x (1.5x to 2.3x on the GPU's own node)." Per machine on the same node and a node ahead: the DRAM board 1.5x to 1.6x and 1.8x, the hybrid 1.9x to 2.1x and 2.4x to 2.6x, the die 2.3x and 3.1x; across the adversary's lane-count choice the same-node bracket is 1.5x to 2.1x and a node ahead 1.8x to 2.6x; 3x to 6x per dollar of hardware at list price. MODELLED: the GPU side measured, the chip's core placed and routed, the rest of the machine modelled, no chip measured, hardware cost approximate within 2x), economic and response capability, rotation an optional improvement. Class v5 derives the dataset from chain state; whether that excludes a specialised design is under evaluation (Deliverable 3), since a design that tracks state is not excluded by staleness. The dataset policy (PROPOSED; the genesis size is the founder's decision, pending; no size served as decided): "The dataset’s size is a one-off hardware ticket on specialised designs and a running energy tax on commodity cards: at 4 to 5.5 GiB a locked Blackwell card pays 12 to 14 percent more energy per hash than at 1 GiB (an 8 GB AMD card under 3 percent of rate), while the board on commodity DRAM pays nothing and the SRAM designs pay a hardware cost that does not change their outcome. The genesis size is scored by adversary burden against commodity burden and is the founder’s decision, pending; no size is served as decided here. Every later step is scored under the standard’s 5 percent GPU-cost rule and taken only when the chain’s own state outgrows the dataset, not on a calendar." (PROPOSED; the card rows measured, the tickets modelled and approximate). The energy ratio is not the pass criterion: the coexistence model ([docs/analysis/class-v6/coexistence-model.md](https://git.igneum.network/igneum-network/igneum/src/branch/master/docs/analysis/class-v6/coexistence-model.md)) is, and its first run's result is served with its conditions: A specialised supplier may earn a normal return; ordinary GPUs remain sufficiently close in total cost, widely obtainable and useful outside mining that new operators can still compete. On today's modelled rows that holds for the chip anyone can build, a stored-dataset board on commodity DRAM, at a productive life of one to three years: its cost per accepted unit of work sits within the range of the best GPU owner and entrant, it passes six of the seven conditions (a third of the network in boards now costs less than a year's revenue at the final hardware price), and a fleet of it holds a minority of the network with GPU entrants still setting the price. For the SRAM-store die the outcome turns on its hardware cost per unit of work, not its energy advantage: at the reconciled machine cost, set by the power train and the shadow core rather than the die, it fails the cost, hardware, fleet and margin conditions at every point of the band, a modest fleet holds about two fifths of a growing network and three fifths of a flat one on arrival and takes every flat or shrinking network within five years, and the only coexistence-shaped outcome is private supply in a growing network; what holds it is the investment decision, since its economics are project economics. A third design, a DRAM board with the hottest half of the dataset in on-board SRAM, sits between the two: it coexists only in a growing network at cheap GPU electricity and fails the cost conditions in a flat or shrinking one, and the dataset's size floor is a real lever on it where it was none on the SRAM die. What holds the die is the investment decision, not the hash; every chip figure here is modelled, not measured, and the chip's hardware cost per unit of work is approximate within 2x.
The litepaper (the chip model)
MODELLED; designed (the bracket modelled; the GPU side tested by the team)docs/design/class-v6-rotating-family.md section 10 (10.0h to 10.0n, 8 October 2026); docs/plans/igneum-2.0.md D3 and D4the scoring rule in the close (the minimum over workloads of the maximum over free adversarial designs of the GPU's joules per hash over the adversary's, under the 10 percent GPU-cost budget at the lock, the verifier limit, cross-vendor correctness and hardware accessibility); the placed rows are D3'sthe GPU side measured: the RTX 5080 at its 1,100 MHz lock 2.06 microjoules per hash and the RTX 5090 at its 1,300 MHz lock 2.33 (8 October 2026, the project's own rigs and rented pods); the chip side synthesised and claimed, its placed gated row pendingnone yet. Packet: parameters the placed full 18-family core on ASAP7, claimed node scaling, the GDDR7 board, the RTX 5090 at its 1,300 MHz lock on class v4; procedure class-v6-rotating-family.md section 10 and coexistence-model.md; raw result the energies and verdicts as served; reproduction none yet; review scope three external reviews of the close, findings taken; unresolved no chip measured, hardware cost approximate within 2x, the k lane's 32-lane placed row pending +6The chip claim as served: "Igneum remains competitive on accessible commodity GPUs even when specialised mining hardware is assumed to exist, remain compatible and seek profit; its security does not rely on identifying that hardware or retiring it through emergency changes." Under it the three statements, separate: energy ("Current modelling estimates a 1.5x to 3.1x energy-efficiency advantage for the specialised designs assessed as complete machines against the GPU tier, from a board on commodity DRAM at 1.5x to an SRAM-store die at 3.1x (1.5x to 2.3x on the GPU's own node)." Per machine on the same node and a node ahead: the DRAM board 1.5x to 1.6x and 1.8x, the hybrid 1.9x to 2.1x and 2.4x to 2.6x, the die 2.3x and 3.1x; across the adversary's lane-count choice the same-node bracket is 1.5x to 2.1x and a node ahead 1.8x to 2.6x; 3x to 6x per dollar of hardware at list price. MODELLED: the GPU side measured, the chip's core placed and routed, the rest of the machine modelled, no chip measured, hardware cost approximate within 2x), economic and response capability, rotation an optional improvement. Class v5 derives the dataset from chain state; whether that excludes a specialised design is under evaluation (Deliverable 3), since a design that tracks state is not excluded by staleness. The dataset policy (PROPOSED; the genesis size is the founder's decision, pending; no size served as decided): "The dataset’s size is a one-off hardware ticket on specialised designs and a running energy tax on commodity cards: at 4 to 5.5 GiB a locked Blackwell card pays 12 to 14 percent more energy per hash than at 1 GiB (an 8 GB AMD card under 3 percent of rate), while the board on commodity DRAM pays nothing and the SRAM designs pay a hardware cost that does not change their outcome. The genesis size is scored by adversary burden against commodity burden and is the founder’s decision, pending; no size is served as decided here. Every later step is scored under the standard’s 5 percent GPU-cost rule and taken only when the chain’s own state outgrows the dataset, not on a calendar." (PROPOSED; the energy-against-size curve on the litepaper: 1, 2, 4 and 5.5 GiB at stock and at the lock measured on an RTX 5090 against its own 1 GiB control, +0.7 and +4.3 percent at stock, +11.7 and +13.4 at the lock for 4 and 5.5 GiB, the 2 GiB knee cell a paired read in flight; the exclusions by memory; the SRAM tickets modelled). The energy ratio is not the pass criterion: the coexistence model ([docs/analysis/class-v6/coexistence-model.md](https://git.igneum.network/igneum-network/igneum/src/branch/master/docs/analysis/class-v6/coexistence-model.md)) is, and its first run's result is served with its conditions: A specialised supplier may earn a normal return; ordinary GPUs remain sufficiently close in total cost, widely obtainable and useful outside mining that new operators can still compete. On today's modelled rows that holds for the chip anyone can build, a stored-dataset board on commodity DRAM, at a productive life of one to three years: its cost per accepted unit of work sits within the range of the best GPU owner and entrant, it passes six of the seven conditions (a third of the network in boards now costs less than a year's revenue at the final hardware price), and a fleet of it holds a minority of the network with GPU entrants still setting the price. For the SRAM-store die the outcome turns on its hardware cost per unit of work, not its energy advantage: at the reconciled machine cost, set by the power train and the shadow core rather than the die, it fails the cost, hardware, fleet and margin conditions at every point of the band, a modest fleet holds about two fifths of a growing network and three fifths of a flat one on arrival and takes every flat or shrinking network within five years, and the only coexistence-shaped outcome is private supply in a growing network; what holds it is the investment decision, since its economics are project economics. A third design, a DRAM board with the hottest half of the dataset in on-board SRAM, sits between the two: it coexists only in a growing network at cheap GPU electricity and fails the cost conditions in a flat or shrinking one, and the dataset's size floor is a real lever on it where it was none on the SRAM die. What holds the die is the investment decision, not the hash; every chip figure here is modelled, not measured, and the chip's hardware cost per unit of work is approximate within 2x.
The litepaper (the chip model)
MODELLED; designed (the bracket modelled; the GPU side tested by the team)docs/design/class-v6-rotating-family.md section 10 (10.0h to 10.0n, 8 October 2026); docs/plans/igneum-2.0.md D3 and D4the scoring rule in the close (the minimum over workloads of the maximum over free adversarial designs of the GPU's joules per hash over the adversary's, under the 10 percent GPU-cost budget at the lock, the verifier limit, cross-vendor correctness and hardware accessibility); the placed rows are D3'sthe GPU side measured: the RTX 5080 at its 1,100 MHz lock 2.06 microjoules per hash and the RTX 5090 at its 1,300 MHz lock 2.33 (8 October 2026, the project's own rigs and rented pods); the chip side synthesised and claimed, its placed gated row pendingnone yet. Packet: parameters the placed full 18-family core on ASAP7, claimed node scaling, the GDDR7 board, the RTX 5090 at its 1,300 MHz lock on class v4; procedure class-v6-rotating-family.md section 10 and coexistence-model.md; raw result the energies and verdicts as served; reproduction none yet; review scope three external reviews of the close, findings taken; unresolved no chip measured, hardware cost approximate within 2x, the k lane's 32-lane placed row pending 7Mining and proving together on one card needs a 16 GB card at the proposed 5.5 GiB dataset (the genesis size is pending the founder’s decision; at a smaller dataset the miner holds less and the rule is not yet measured): the miner holds about 6.1 GiB and a compressed shard proof peaks at about 7.5 GiB, so 8 GB and 12 GB cards time-share (the app pauses the miner for the proof). NVIDIA proves; AMD and Apple mine
The litepaper (Proving, vs RandomX); the miner page
TEAM-REPORTED; tested by the teamdocs/analysis/class-v6/coexist-rows.md (the 5.5 GiB ds55 miner beside igneum-prove-host-0317, compressed at threshold 2^26, the served sm_86 and sm_89 floors)the RESULT rows in that file, verbatim from the runsrented RTX 3060 12 GB: 26.82 MH/s at 117.4 W with 6,129 MiB resident; the compressed shard 13.2 s, peak 7,525 MiB (6,129 + 7,525 = 13,654 MiB against 12,288); rented RTX 4060 8 GB: 18.84 MH/s, 6,116 MiB resident; the shard 8.2 s, peak 7,532 MiB; 8 October 2026none yet. Packet: parameters the 5.5 GiB ds55 miner, igneum-prove-host-0317 compressed at threshold 2^26, sm_86 and sm_89; procedure coexist-rows.md; raw result the RESULT rows verbatim; reproduction none yet; review scope none; unresolved two cards on one day, the 6 October rows stand as 1 GiB-dataset rows

Click a column heading to sort; click again to reverse. Versions: the Igneum 2.0 devnet (igneum-devnet-4) runs since its first block at 17:14 UK on 8 October 2026; the release manifest, machine-readable, is regenerated at its first block and fills these at build time. As last read it names node 4cdcc488 on release-2.0.0-node, igneum-pow 1c420786, chain id 4465, read 8 October 2026, 17:2x UK. The labels stay distinct: a claim never moves up a label without the artefact the next table names. The public reference repository exists (the specifications, the pow crate, the simulators and the test material, at git.igneum.network); the full node, the miner and the proving code open later, so a row that cites them is tested by the team at most until they do. Node fork commits are the node fork’s; a document path is the repository’s. The source of this page is docs/evidence.md in the repository.

diff --git a/site/litepaper.html b/site/litepaper.html index ea0ea8699..72da41240 100644 --- a/site/litepaper.html +++ b/site/litepaper.html @@ -469,6 +469,14 @@ body.all .pager{display:none}

Igneum remains competitive on accessible commodity GPUs even when specialised mining hardware is assumed to exist, remain compatible and seek profit; its security does not rely on identifying that hardware or retiring it through emergency changes. Class v6 adopts the 64-register window and retains it across every rotation. Current modelling estimates a 1.5x to 3.1x energy-efficiency advantage for the specialised designs assessed as complete machines against the GPU tier, from a board on commodity DRAM at 1.5x to an SRAM-store die at 3.1x (1.5x to 2.3x on the GPU's own node). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment.

The labels. MODELLED. The GPU side is measured (the RTX 5090 at its 1,300 MHz lock on class v4, 8 October 2026). The chip’s core is placed and routed on ASAP7 with SRAM macros and scaled on claimed node factors; the chip’s memory and the rest of the machine (controller, host share, PSU, VRM, cooling) are modelled; no chip is measured, and the chip’s hardware cost is approximate within 2x. Beside it the coexistence verdict at these energies: the DRAM board passes six of the model’s seven conditions, the hybrid coexists only in a growing chain at cheap GPU electricity, the SRAM die fails the cost, hardware, fleet and margin conditions at its reconciled machine cost, and only private supply in a growing network coexists. The k lane’s own placed row amends the figures if it differs. The GPU side is measured: an RTX 5080 at its 1,100 MHz core lock, 2.06 microjoules per hash, and an RTX 5090 at its 1,300 MHz lock, 2.33 microjoules per hash, both under class v4, on the project’s own rigs and rented pods, 8 October 2026; the card’s cost of the window is measured too (a rented RTX 5090 and RTX 4090 at stock, 8 October 2026: within 5 percent per load with the liveness chain, no register spill). The chip side is synthesised and claimed: the clock-gated sequencer core with the 64-register window on ASAP7, scaled to N3 on the foundry’s headline factors (k about 0.37 at N3 and 0.51 node for node for the base core, the gated window adding about 0.13 of k against an adversary with a flop register file; the window’s liveness measured at 61 of 64 values necessary, its cost to the card measured under 5 percent); the window’s k is synthesis-derived and not a lower bound, and the multi-family adversary lane’s first core (its state in a macro) reads the window’s defence as close to nothing, a disagreement between two models that the placed rows settle. The chip’s memory is modelled: the GDDR7 board of the chip model. The placed gated figure is expected near 2.6x to 3.1x a node ahead and 2.3x to 2.7x node for node (approximate) and is served when its row lands.

The dataset policy (PROPOSED; the genesis size is the founder’s decision, pending). The dataset’s size is a one-off hardware ticket on specialised designs and a running energy tax on commodity cards: at 4 to 5.5 GiB a locked Blackwell card pays 12 to 14 percent more energy per hash than at 1 GiB (an 8 GB AMD card under 3 percent of rate), while the board on commodity DRAM pays nothing and the SRAM designs pay a hardware cost that does not change their outcome. The genesis size is scored by adversary burden against commodity burden and is the founder’s decision, pending; no size is served as decided here. Every later step is scored under the standard’s 5 percent GPU-cost rule and taken only when the chain’s own state outgrows the dataset, not on a calendar. (the card rows measured: an RTX 5090 at its 1,300 MHz lock on the project’s own rig, one paired mapping job, 8 October 2026, the cost the size’s and not the mapping’s; the chip tickets modelled and approximate; later steps’ costs expected, not measured.)

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DatasetEnergy per hash against 1 GiB, at stockAt the 1,300 MHz lockCards excluded by memorySRAM ticket on the hybrid boardSRAM ticket on the dieLabels
1 GiB (class v4 today)the controlthe controlnoneUSD 125one reticle, USD 500measured; modelled
2 GiB (class v5’s designed size)about +1 percentabout +4 percent (the morning’s run; a paired read in flight)none (an 8 GB card holds it)USD 250one reticle, USD 500measured; modelled
4 GiB+0.7 percent+11.7 percentnone by memory (an 8 GB AMD card measured -2.6 percent of rate; a 12 GB card loses mine-and-prove co-residence)USD 500two reticles, USD 1,000measured (paired, 8 October 2026, 18:2x UK); modelled
5.5 GiB+4.3 percent+13.4 percentnone by memory (an 8 GB card holds it with 1.8 GB spare, measured -2.5 percent of rate; a 12 GB card loses mine-and-prove co-residence)USD 690three reticles, USD 1,500measured (paired, 8 October 2026, 18:2x UK); modelled
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The energy columns are measured on an RTX 5090 on the project’s own rig, 8 October 2026, against its own 1 GiB control at stock and at the 1,300 MHz lock (250 batches of 2^24, fingerprints equal across sizes); the exclusions are by memory on the reference population, measured where a card ran the size; the SRAM tickets are modelled (the hybrid’s hot-half store at about USD 250 per GiB of N2 SRAM; the die’s reticle count at USD 500 a reticle, claimed). A locked card pays the size as energy, a specialised design as a one-off ticket; on the measured rows the knee cost saturates above a few gigabytes (about 12 to 14 percent at 4 to 5.5 GiB) and no size moves a specialised design’s economic outcome. The board on commodity DRAM pays nothing at any size (modelled).

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Three statements, kept separate. The baseline is the hash as it stands under the scoring rule; rotation is an optional improvement to that baseline, not the mechanism the claim rests on.

StatementWhat it saysLabel and date
Energy resistancePer machine against a locked RTX 5090, node for node and a node ahead: the DRAM board 1.5x to 1.6x (1.3x to 1.7x) and 1.8x; the board with SRAM holding the hottest half of the dataset 1.9x to 2.1x and 2.4x to 2.6x; the SRAM-store die 2.3x and 3.1x; across the adversary’s lane-count choice the same-node bracket is 1.5x to 2.1x and a node ahead 1.8x to 2.6x, so about 2x on the same node stands at the bracket’s top; per dollar of hardware at list price 3x to 6x (modelled on the placed full 18-family core, routed 8 October 2026, and the 32-lane core’s synthesis). The honest tier moves to the next node with every GPU generation; a chip must tape out again. Whole machine per tier (synthesis with the SRAM band and node factors, claimed; placed rows to follow): the complete GDDR7 machine about 1.8x the RTX 5090 at its lock per joule node for node and 2.1x a node ahead; 1.6x and 1.9x the RTX 5080; 2.8x and 3.3x the Ada, Ampere and RX 9070 XT cohort; about 1.5x the Apple tier, reported, never headlined.MODELLED: placed and routed core energies against the measured RTX 5090 lock row, 8 October 2026, no chip measured