fdcab858e3
igneum-pow 0.2.0: generator v2 draws exactly 16 load slots from instructions 1..63, a load's source from the registers written earlier and not read by a load since, the other 48 ops from the ten non-load weights; accept.rs is spec 01 section 1.4.6 (static: no stale load source, every register injected; dynamic: 64 units on the seed-keyed closed-form dataset, no constant bit, no lane-constant site, under 164 saturated, bias within 136 of 1024, distinct addresses above 245,760); a rejected candidate is replaced by the next attempt of the seed (seed || k_le32), 32 a consensus fault. Packs carry the generator version, attempt and program id. Version 1 kept as generate_v1 for the census. Packs: igneum-genesis, igneum-hourly, igneum-genesis-mh regenerated by igneum-pow export; new igneum-devnet-v4-epoch0 (devnet genesis hash, day bytes 20730). Checks: Rust 39 of 39 tests; Metal natively via the Swift port (export cross-check 3 of 3 warps, identical programs and vectors on five seeds incl. three with attempt 1, fuzz 2,000 of 2,000); CUDA emu 4 of 4 packs; OpenCL emu 2 packs x 2 configurations; Apple OpenCL 4 of 4 packs at 27.9 Mhash/s. Census 20,000: 5.225 percent rejected, accepted distinct mean 127.887. Spec 01 0.2 (1.4.2, 1.4.3, 1.4.6, 1.11, 1.15, 1.16, 1.17), igneum-pow README, the CUDA, OpenCL and Metal test notes, bench-log entry, ledger M5 and M6 Fixed. Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
123 lines
6.7 KiB
Text
123 lines
6.7 KiB
Text
// Generated by igneum-pow export (generator v2) for seed "igneum-epoch/edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07/day/69676e65756d2d6461792ffa50000000000000". Do not edit by hand.
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// Header-bound twin of igneum_hash in kernel.cu: the init words come from a kernel argument, not SEEDW.
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// Host declarations (also in program_bound.h if present):
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// struct IgneumInitWords { uint32_t w[8]; };
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// cudaError_t igneum_launch_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t baseNonce, uint32_t mask,
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// IgneumInitWords iw, uint32_t nonces, uint32_t blockWarps);
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// cudaError_t igneum_hash_bound_info(int* numRegs, int* blocksPerSM, uint32_t blockWarps);
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#include <cuda_runtime.h>
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#include <cstdint>
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#include "program.h"
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struct IgneumInitWords { uint32_t w[8]; };
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__device__ __forceinline__ uint32_t splitmix32(uint32_t x) {
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x ^= x >> 16; x *= 0x7feb352du;
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x ^= x >> 15; x *= 0x846ca68bu;
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x ^= x >> 16;
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return x;
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}
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__device__ __forceinline__ uint32_t rotl_imm(uint32_t x, uint32_t n) { return (x << n) | (x >> (32u - n)); }
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__device__ __forceinline__ uint32_t rotr_var(uint32_t x, uint32_t n) { n &= 31u; return (x >> n) | (x << ((32u - n) & 31u)); }
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__global__ void igneum_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t baseNonce, uint32_t mask, IgneumInitWords iw) {
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uint32_t gid = blockIdx.x * blockDim.x + threadIdx.x;
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uint32_t nonce = baseNonce + gid;
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uint32_t r0, r1, r2, r3, r4, r5, r6, r7;
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{ uint32_t x = nonce ^ iw.w[0]; x += 0x9e3779b9u * 1u; x = splitmix32(x); r0 = x ^ iw.w[1]; }
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{ uint32_t x = nonce ^ iw.w[1]; x += 0x9e3779b9u * 2u; x = splitmix32(x); r1 = x ^ iw.w[2]; }
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{ uint32_t x = nonce ^ iw.w[2]; x += 0x9e3779b9u * 3u; x = splitmix32(x); r2 = x ^ iw.w[3]; }
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{ uint32_t x = nonce ^ iw.w[3]; x += 0x9e3779b9u * 4u; x = splitmix32(x); r3 = x ^ iw.w[4]; }
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{ uint32_t x = nonce ^ iw.w[4]; x += 0x9e3779b9u * 5u; x = splitmix32(x); r4 = x ^ iw.w[5]; }
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{ uint32_t x = nonce ^ iw.w[5]; x += 0x9e3779b9u * 6u; x = splitmix32(x); r5 = x ^ iw.w[6]; }
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{ uint32_t x = nonce ^ iw.w[6]; x += 0x9e3779b9u * 7u; x = splitmix32(x); r6 = x ^ iw.w[7]; }
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{ uint32_t x = nonce ^ iw.w[7]; x += 0x9e3779b9u * 8u; x = splitmix32(x); r7 = x ^ iw.w[0]; }
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for (uint32_t it = 0u; it < 8u; ++it) {
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uint32_t sel = r0;
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r4 = r4 + r5 + ((((sel >> 13u) & 1u) != 0u) ? 0x5810667au : 0xea86e152u); // 0 add
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r2 = r2 ^ __shfl_xor_sync(0xffffffffu, r0, 4); // 1 shfl
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r3 = r3 + r2 + ((((sel >> 10u) & 1u) != 0u) ? 0x642e66dbu : 0x2cccb6cau); // 2 add
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r0 = rotl_imm(r0, 19u); // 3 rotl
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r7 = rotr_var(r7, r6); // 4 rotr
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r7 = r7 + r4 + ((((sel >> 21u) & 1u) != 0u) ? 0xc1535555u : 0xee02465fu); // 5 add
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r1 = __umulhi(r1, r7); // 6 mulhi
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r4 = r4 ^ ds[r2 & mask]; // 7 load
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r7 = r7 ^ ds[r4 & mask]; // 8 load
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r0 = r0 ^ ds[r3 & mask]; // 9 load
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r5 = r5 ^ ds[r1 & mask]; // 10 load
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r1 = r1 ^ ds[r5 & mask]; // 11 load
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r3 = __umulhi(r3, r5); // 12 mulhi
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r1 = r1 ^ ds[r3 & mask]; // 13 load
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r0 = r0 - r3; // 14 sub
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r5 = r1 * r3 + r5; // 15 mad
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r6 = __umulhi(r6, r1); // 16 mulhi
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r5 = r5 + r2 + ((((sel >> 28u) & 1u) != 0u) ? 0x8b965b57u : 0x697b3d00u); // 17 add
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r0 = __umulhi(r0, r6); // 18 mulhi
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r5 = rotr_var(r5, r3); // 19 rotr
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r5 = __umulhi(r5, r2); // 20 mulhi
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r1 = r1 + r0 + ((((sel >> 1u) & 1u) != 0u) ? 0x6d7e8d05u : 0xebcf247au); // 21 add
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r7 = r7 + r5 + ((((sel >> 12u) & 1u) != 0u) ? 0xb9e3577eu : 0xf66e7017u); // 22 add
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r1 = __umulhi(r1, r5); // 23 mulhi
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r2 = r2 - r5; // 24 sub
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r7 = r7 + r4 + ((((sel >> 2u) & 1u) != 0u) ? 0x699ef1bbu : 0x08ffa6c7u); // 25 add
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r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r4, 2); // 26 shfl
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r7 = r7 + r1 + ((((sel >> 14u) & 1u) != 0u) ? 0xb4ead2fbu : 0xe60fea84u); // 27 add
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r3 = r3 + r1 + ((((sel >> 6u) & 1u) != 0u) ? 0x8f30d21du : 0x65c76dabu); // 28 add
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r2 = r2 ^ ds[r1 & mask]; // 29 load
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r5 = r5 ^ ds[r7 & mask]; // 30 load
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r2 = r2 ^ ds[r5 & mask]; // 31 load
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r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r7, 4); // 32 shfl
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r4 = r5 * r7 + r4; // 33 mad
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r4 = r4 + r2 + ((((sel >> 21u) & 1u) != 0u) ? 0xc7ce690cu : 0x0480debeu); // 34 add
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r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r7, 8); // 35 shfl
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r7 = r7 + r1 + ((((sel >> 2u) & 1u) != 0u) ? 0xe10c2c95u : 0xc53b542eu); // 36 add
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r5 = r5 ^ r7; // 37 xor
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r2 = r2 | r1; // 38 or
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r1 = __umulhi(r1, r0); // 39 mulhi
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r6 = rotl_imm(r6, 19u); // 40 rotl
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r4 = __umulhi(r4, r6); // 41 mulhi
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r6 = r6 - r0; // 42 sub
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r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r3, 4); // 43 shfl
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r4 = r4 ^ ds[r2 & mask]; // 44 load
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r1 = r1 ^ r3; // 45 xor
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r7 = r7 ^ ds[r0 & mask]; // 46 load
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r3 = r3 ^ ds[r1 & mask]; // 47 load
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r5 = r5 * r3; // 48 mul
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r1 = r1 - r5; // 49 sub
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r2 = rotl_imm(r2, 8u); // 50 rotl
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r1 = r1 + r5 + ((((sel >> 23u) & 1u) != 0u) ? 0x77b9bd43u : 0xa900fec4u); // 51 add
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r4 = r4 ^ ds[r7 & mask]; // 52 load
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r2 = r2 - r7; // 53 sub
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r4 = r4 ^ r0; // 54 xor
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r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 55 add
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r2 = r2 ^ ds[r4 & mask]; // 56 load
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r0 = r1 * r4 + r0; // 57 mad
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r3 = r3 ^ ds[r5 & mask]; // 58 load
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r5 = r5 | r6; // 59 or
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r6 = r5 * r7 + r6; // 60 mad
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r4 = rotl_imm(r4, 28u); // 61 rotl
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r5 = __umulhi(r5, r0); // 62 mulhi
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r3 = r3 ^ ds[r6 & mask]; // 63 load
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}
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uint32_t lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u);
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uint32_t hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u);
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out[gid] = ((uint64_t)hi << 32) | (uint64_t)lo;
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}
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cudaError_t igneum_launch_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t baseNonce, uint32_t mask,
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IgneumInitWords iw, uint32_t nonces, uint32_t blockWarps) {
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if (blockWarps == 0u || blockWarps > 32u) return cudaErrorInvalidValue;
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uint32_t block = 32u * blockWarps;
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if (nonces == 0u || (nonces % block) != 0u) return cudaErrorInvalidValue;
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igneum_hash_bound<<<nonces / block, block>>>(ds, out, baseNonce, mask, iw);
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return cudaGetLastError();
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}
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cudaError_t igneum_hash_bound_info(int* numRegs, int* blocksPerSM, uint32_t blockWarps) {
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cudaFuncAttributes attr;
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cudaError_t e = cudaFuncGetAttributes(&attr, igneum_hash_bound);
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if (e != cudaSuccess) return e;
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*numRegs = attr.numRegs;
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return cudaOccupancyMaxActiveBlocksPerMultiprocessor(blocksPerSM, igneum_hash_bound, (int)(32u * blockWarps), 0);
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}
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