docs/plans/intel-arc.md: the OpenCL worker runs the B580 first (Intel's OpenCL 3.0 runtime, exchange auto with the
local-memory fallback the worker already carries), the expected ceiling from 456 GB/s (13 to 20 MH/s, approximate until
the memprobe), 12 GB = mine only (the prover is CUDA only), the Arc OpenCL gotchas (sub-group 16 vs 32, SLM, spills,
64-bit multiply, IGC's build options and compile time, two Intel platforms, no power API through OpenCL: IGCL next),
the fallback ladder with hours (SPIR-V into the same runtime, a Level Zero host, SYCL), the consequences per tier.
App: vendor "intel" from the OpenCL vendor string and the Windows name; Arc cards discrete, the Arc-branded processor
graphics integrated; the INTEL badge in the Intel blue token, light and dark; the row's no-reading sentence, the
measure-only tune words and the details panel's no-cap note; sweep.rs names IGCL as the source to come; detect.rs test
on a B580 line beside PC 1's list; view.test.mjs row test; ui-mock scenario intel.
PC 1 jobs (tools/intel-arc): the elevated driver job (ran twice on 7 October: run 1 exit 1007 = the bootstrapper's wrap
of the inner installer's 7 on my -report flag; run b with -s alone exit 1014 = inner 14, installed, restart required),
the restart job (the project lead's word), the read-back job, the packs kit and the bench job with the memprobe, class v4 and v3
benches, the local-exchange row, the bench-log row, the card-picker entry and the owner's consequences line.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
f39d64a7e2