422 lines
24 KiB
Text
422 lines
24 KiB
Text
// Generated by igneum-pow export (generator v2) for seed "igneum-epoch/edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07/day/69676e65756d2d6461792ffa50000000000000". Do not edit by hand.
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// Bit-exact twin of the Metal kernel for the same seed (see proto-cuda/CHECKLIST.md and program.metal).
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// Compiled ahead of time by nvcc together with proto-cuda/host.cu. No NVRTC.
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#include <cuda_runtime.h>
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#include <cstdint>
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#include "program.h"
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#include "memhard.h"
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__device__ __forceinline__ uint32_t splitmix32(uint32_t x) {
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x ^= x >> 16; x *= 0x7feb352du;
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x ^= x >> 15; x *= 0x846ca68bu;
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x ^= x >> 16;
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return x;
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}
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// n is a literal in 1..31 at every call site, so both shift amounts are in 1..31.
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__device__ __forceinline__ uint32_t rotl_imm(uint32_t x, uint32_t n) { return (x << n) | (x >> (32u - n)); }
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// n is masked to 0..31; the second shift amount is masked too, so n == 0 gives x.
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__device__ __forceinline__ uint32_t rotr_var(uint32_t x, uint32_t n) { n &= 31u; return (x >> n) | (x << ((32u - n) & 31u)); }
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__device__ __forceinline__ uint32_t ds_elem(uint32_t i, uint32_t d0, uint32_t d1) {
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uint32_t x = i ^ d0;
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x *= 0x9E3779B1u; x ^= x >> 15;
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x += d1;
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x *= 0x85EBCA77u; x ^= x >> 13;
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x *= 0xC2B2AE3Du; x ^= x >> 16;
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return x;
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}
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// Memory-hard dataset (MEMHARD.md). One thread per cache segment; one thread per 64-byte dataset item.
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// The core functions (mh_cache_segment, mh_item) are in memhard.h and are also compiled for the host.
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__global__ void igneum_cache_fill(uint32_t* cache, uint32_t nSegments) {
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uint32_t seg = blockIdx.x * blockDim.x + threadIdx.x;
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if (seg < nSegments) mh_cache_segment(cache, seg);
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}
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__global__ void igneum_build(uint32_t* ds, const uint32_t* cache, uint32_t nItems) {
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uint32_t t = blockIdx.x * blockDim.x + threadIdx.x;
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if (t < nItems) {
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uint32_t s[16];
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mh_item(cache, t, s);
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for (uint32_t i = 0u; i < 16u; ++i) ds[(size_t)mh_addr(t, i)] = s[i];
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}
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}
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// One hash per thread. blockDim.x is a multiple of 32; lane = threadIdx.x & 31 and every
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// __shfl_xor_sync stays inside the lane's own warp, exactly like simd_shuffle_xor inside a
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// 32-wide Metal SIMD group. Control flow is uniform, so the full 0xffffffff member mask is valid.
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__global__ void igneum_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonce, uint32_t mask) {
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uint32_t gid = blockIdx.x * blockDim.x + threadIdx.x;
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uint32_t nonce = baseNonce + gid;
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uint32_t r0, r1, r2, r3, r4, r5, r6, r7;
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{ uint32_t x = nonce ^ 0x667d0fbdu; x += 0x9e3779b9u; x = splitmix32(x); r0 = x ^ 0x7b8e5963u; } // SEEDW[0], 0x9e3779b9u * 1u, SEEDW[1]
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{ uint32_t x = nonce ^ 0x7b8e5963u; x += 0x3c6ef372u; x = splitmix32(x); r1 = x ^ 0x31c67e5eu; } // SEEDW[1], 0x9e3779b9u * 2u, SEEDW[2]
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{ uint32_t x = nonce ^ 0x31c67e5eu; x += 0xdaa66d2bu; x = splitmix32(x); r2 = x ^ 0x4529ddc6u; } // SEEDW[2], 0x9e3779b9u * 3u, SEEDW[3]
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{ uint32_t x = nonce ^ 0x4529ddc6u; x += 0x78dde6e4u; x = splitmix32(x); r3 = x ^ 0xef19d6d8u; } // SEEDW[3], 0x9e3779b9u * 4u, SEEDW[4]
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{ uint32_t x = nonce ^ 0xef19d6d8u; x += 0x1715609du; x = splitmix32(x); r4 = x ^ 0xaccf6211u; } // SEEDW[4], 0x9e3779b9u * 5u, SEEDW[5]
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{ uint32_t x = nonce ^ 0xaccf6211u; x += 0xb54cda56u; x = splitmix32(x); r5 = x ^ 0xda0aed32u; } // SEEDW[5], 0x9e3779b9u * 6u, SEEDW[6]
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{ uint32_t x = nonce ^ 0xda0aed32u; x += 0x5384540fu; x = splitmix32(x); r6 = x ^ 0xabc6df31u; } // SEEDW[6], 0x9e3779b9u * 7u, SEEDW[7]
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{ uint32_t x = nonce ^ 0xabc6df31u; x += 0xf1bbcdc8u; x = splitmix32(x); r7 = x ^ 0x667d0fbdu; } // SEEDW[7], 0x9e3779b9u * 8u, SEEDW[0]
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for (uint32_t it = 0u; it < 8u; ++it) {
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uint32_t sel = r0;
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r4 = r4 + r5 + ((((sel >> 13u) & 1u) != 0u) ? 0x5810667au : 0xea86e152u); // 0 add
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r7 = r7 ^ r0; // 1 xor
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r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r6, 1); // 2 shfl
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r4 = r4 - r1; // 3 sub
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r2 = r0 * r4 + r2; // 4 mad
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r4 = rotl_imm(r4, 9u); // 5 rotl
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r0 = rotr_var(r0, r2); // 6 rotr
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r6 = r6 ^ ds[((rotl_imm(r7 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x04000000u) & mask]; // 7 load
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r1 = r1 ^ ds[((rotl_imm(r4 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 8 load
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r1 = r1 ^ ds[((rotl_imm(r2 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 9 load
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r7 = r7 ^ ds[((rotl_imm(r0 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 10 load
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r7 = r7 ^ ds[((rotl_imm(r1 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 11 load
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r5 = r5 * r4; // 12 mul
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r7 = r7 ^ ds[((rotl_imm(r6 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 13 load
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r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r5, 16); // 14 shfl
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r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r5, 1); // 15 shfl
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r2 = r2 | r7; // 16 or
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r0 = rotr_var(r0, r6); // 17 rotr
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r7 = r7 + r5 + ((((sel >> 12u) & 1u) != 0u) ? 0xb9e3577eu : 0xf66e7017u); // 18 add
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r7 = rotl_imm(r7, 24u); // 19 rotl
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r6 = r6 + r7 + ((((sel >> 23u) & 1u) != 0u) ? 0x8c9f0ef8u : 0x52334d12u); // 20 add
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r2 = r2 | r6; // 21 or
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r6 = r5 * r4 + r6; // 22 mad
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r1 = r1 | r0; // 23 or
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r6 = r6 ^ r1; // 24 xor
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r2 = r2 + r6 + ((((sel >> 17u) & 1u) != 0u) ? 0x9cec0e12u : 0x659fc3d3u); // 25 add
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r7 = rotr_var(r7, r0); // 26 rotr
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r4 = r5 * r7 + r4; // 27 mad
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r3 = r2 * r4 + r3; // 28 mad
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r1 = r1 ^ ds[((rotl_imm(r4 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 29 load
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r2 = r2 ^ ds[((rotl_imm(r3 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x08000000u) & mask]; // 30 load
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r1 = r1 ^ ds[((rotl_imm(r5 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 31 load
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r7 = r7 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0xe403240eu : 0x070888a8u); // 32 add
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r2 = r2 + r0 + ((((sel >> 28u) & 1u) != 0u) ? 0x29701828u : 0xf2e46d55u); // 33 add
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r2 = r2 + r3 + ((((sel >> 14u) & 1u) != 0u) ? 0x343b7aeeu : 0x58f75b87u); // 34 add
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r2 = __umulhi(r2, r5); // 35 mulhi
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r4 = r4 ^ r2; // 36 xor
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r6 = r6 * r5; // 37 mul
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r7 = r7 ^ r0; // 38 xor
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r7 = r7 + r2 + ((((sel >> 19u) & 1u) != 0u) ? 0x32bbd117u : 0xb8180e9du); // 39 add
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r2 = rotr_var(r2, r3); // 40 rotr
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r7 = r7 - r0; // 41 sub
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r4 = r4 + r3 + ((((sel >> 4u) & 1u) != 0u) ? 0x6df7aed4u : 0x6ced15b7u); // 42 add
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r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r3, 4); // 43 shfl
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r0 = r0 ^ ds[((rotl_imm(r7 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 44 load
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r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 45 add
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r3 = r3 ^ ds[((rotl_imm(r1 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x00000000u) & mask]; // 46 load
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r6 = r6 ^ ds[((rotl_imm(r3 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 47 load
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r4 = __umulhi(r4, r2); // 48 mulhi
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r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xf572bdb9u : 0xa8bae6dfu); // 49 add
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r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r7, 4); // 50 shfl
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r6 = r6 + r0 + ((((sel >> 19u) & 1u) != 0u) ? 0x11e17c61u : 0x383b9260u); // 51 add
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r5 = r5 ^ ds[((rotl_imm(r2 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 52 load
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r6 = rotl_imm(r6, 12u); // 53 rotl
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r3 = rotl_imm(r3, 12u); // 54 rotl
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r2 = r2 + r1 + ((((sel >> 10u) & 1u) != 0u) ? 0x18d67dbbu : 0xac6be8e3u); // 55 add
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r1 = r1 ^ ds[((rotl_imm(r4 * 0x625e5ab3u, 19u) & 0x0fffffffu) | 0x00000000u) & mask]; // 56 load
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r5 = r5 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0xa75cd60du : 0xf03673feu); // 57 add
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r5 = r5 ^ ds[((rotl_imm(r0 * 0x625e5ab3u, 19u) & 0x03ffffffu) | 0x00000000u) & mask]; // 58 load
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r1 = r1 + r4 + ((((sel >> 7u) & 1u) != 0u) ? 0x8dfb96bbu : 0xdecd4794u); // 59 add
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r3 = __umulhi(r3, r2); // 60 mulhi
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r6 = r6 | r4; // 61 or
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r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r4, 8); // 62 shfl
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r3 = r3 ^ ds[((rotl_imm(r6 * 0x625e5ab3u, 19u) & 0x07ffffffu) | 0x08000000u) & mask]; // 63 load
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// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
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for (uint32_t sh = 0u; sh < 27u; ++sh) {
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r7 = r7 * r3; // s0 mul
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r7 = r7 + r4 + ((((sel >> 16u) & 1u) != 0u) ? 0x06575fd2u : 0xecb44e9cu); // s1 add
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r5 = __umulhi(r5, r0); // s2 mulhi
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r4 = r4 ^ __shfl_xor_sync(0xffffffffu, r5, 2); // s3 shfl
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r4 = r4 ^ __shfl_xor_sync(0xffffffffu, r1, 1); // s4 shfl
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r4 = r4 ^ __shfl_xor_sync(0xffffffffu, r5, 8); // s5 shfl
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r6 = r6 - r1; // s6 sub
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r3 = r3 | r4; // s7 or
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r0 = r4 * r7 + r0; // s8 mad
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r3 = r3 - r4; // s9 sub
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r6 = r6 * r3; // s10 mul
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r5 = __umulhi(r5, r0); // s11 mulhi
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r0 = r4 * r5 + r0; // s12 mad
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r3 = r3 + r7 + ((((sel >> 29u) & 1u) != 0u) ? 0x41da8352u : 0x78295146u); // s13 add
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r7 = r7 ^ r2; // s14 xor
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r1 = r1 + r4 + ((((sel >> 12u) & 1u) != 0u) ? 0x491bea93u : 0x1126a483u); // s15 add
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r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r2, 8); // s16 shfl
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r5 = rotr_var(r5, r0); // s17 rotr
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r2 = r2 - r1; // s18 sub
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r3 = __umulhi(r3, r2); // s19 mulhi
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r0 = r0 ^ r4; // s20 xor
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r2 = r2 + r3 + ((((sel >> 31u) & 1u) != 0u) ? 0xd0df3d0au : 0x7289ac7cu); // s21 add
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r2 = r2 ^ __shfl_xor_sync(0xffffffffu, r7, 2); // s22 shfl
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r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r0, 8); // s23 shfl
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r1 = r1 - r2; // s24 sub
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r7 = r3 * r1 + r7; // s25 mad
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r2 = r2 ^ r6; // s26 xor
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r4 = __umulhi(r4, r2); // s27 mulhi
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r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r2, 2); // s28 shfl
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r2 = r2 - r5; // s29 sub
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r7 = __umulhi(r7, r6); // s30 mulhi
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r2 = rotr_var(r2, r7); // s31 rotr
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r6 = rotl_imm(r6, 26u); // s32 rotl
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r0 = r0 * r7; // s33 mul
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r7 = r7 * r4; // s34 mul
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r6 = r0 * r1 + r6; // s35 mad
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r4 = r4 + r2 + ((((sel >> 4u) & 1u) != 0u) ? 0xb3e87396u : 0xfe2b1c7du); // s36 add
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r7 = rotr_var(r7, r4); // s37 rotr
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r5 = r2 * r7 + r5; // s38 mad
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r6 = r6 + r2 + ((((sel >> 16u) & 1u) != 0u) ? 0x31a906adu : 0xe036a560u); // s39 add
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r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r6, 4); // s40 shfl
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r5 = r5 ^ r0; // s41 xor
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r5 = r5 ^ r3; // s42 xor
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r6 = rotl_imm(r6, 31u); // s43 rotl
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r0 = rotl_imm(r0, 6u); // s44 rotl
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r2 = r0 * r6 + r2; // s45 mad
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r0 = r6 * r0 + r0; // s46 mad
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r5 = r5 ^ r2; // s47 xor
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r1 = r1 + r5 + ((((sel >> 27u) & 1u) != 0u) ? 0xc839ad2eu : 0xd802a3efu); // s48 add
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r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r1, 2); // s49 shfl
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r6 = r6 + r0 + ((((sel >> 18u) & 1u) != 0u) ? 0xe9d06965u : 0x8e71c4c0u); // s50 add
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r1 = rotl_imm(r1, 3u); // s51 rotl
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r6 = r6 ^ r2; // s52 xor
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r5 = r5 ^ r6; // s53 xor
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r2 = r2 * r6; // s54 mul
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r0 = __umulhi(r0, r2); // s55 mulhi
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r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r3, 1); // s56 shfl
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r1 = r1 + r2 + ((((sel >> 21u) & 1u) != 0u) ? 0x5b84a832u : 0xb0eb7d4eu); // s57 add
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r0 = rotr_var(r0, r1); // s58 rotr
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r6 = r6 + r4 + ((((sel >> 8u) & 1u) != 0u) ? 0x4e1a16c6u : 0xd35e37c1u); // s59 add
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r0 = r0 | r2; // s60 or
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r5 = rotr_var(r5, r3); // s61 rotr
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r4 = r4 - r2; // s62 sub
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r0 = r0 + r1 + ((((sel >> 27u) & 1u) != 0u) ? 0xec29413au : 0x16221227u); // s63 add
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r6 = rotl_imm(r6, 20u); // s64 rotl
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r1 = r1 ^ r2; // s65 xor
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r6 = rotl_imm(r6, 23u); // s66 rotl
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r1 = r1 | r4; // s67 or
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r7 = r4 * r0 + r7; // s68 mad
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r1 = r1 | r5; // s69 or
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r7 = r7 ^ r4; // s70 xor
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r2 = r2 * r3; // s71 mul
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r0 = r0 * r2; // s72 mul
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r7 = r7 + r6 + ((((sel >> 4u) & 1u) != 0u) ? 0x85c0f694u : 0x5708524au); // s73 add
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r3 = r7 * r0 + r3; // s74 mad
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r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r2, 8); // s75 shfl
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r5 = r5 - r7; // s76 sub
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r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r1, 2); // s77 shfl
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r5 = r5 + r0 + ((((sel >> 26u) & 1u) != 0u) ? 0xad4f292bu : 0xc4195db9u); // s78 add
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r5 = r5 * r6; // s79 mul
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r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r7, 2); // s80 shfl
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r5 = r5 * r6; // s81 mul
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r7 = r7 | r3; // s82 or
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r0 = r4 * r2 + r0; // s83 mad
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r4 = rotl_imm(r4, 12u); // s84 rotl
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r3 = r3 * r4; // s85 mul
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r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r2, 4); // s86 shfl
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r2 = r2 ^ __shfl_xor_sync(0xffffffffu, r7, 4); // s87 shfl
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r1 = r1 ^ r3; // s88 xor
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r5 = r5 ^ r1; // s89 xor
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r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r1, 16); // s90 shfl
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r5 = r5 + r0 + ((((sel >> 7u) & 1u) != 0u) ? 0xb41704ddu : 0x5570a07eu); // s91 add
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r0 = __umulhi(r0, r1); // s92 mulhi
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r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r0, 8); // s93 shfl
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r3 = r3 + r6 + ((((sel >> 18u) & 1u) != 0u) ? 0x4674baa3u : 0xcd1be982u); // s94 add
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r4 = rotl_imm(r4, 24u); // s95 rotl
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r3 = r7 * r4 + r3; // s96 mad
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r6 = r6 - r3; // s97 sub
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r1 = r5 * r6 + r1; // s98 mad
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r6 = rotr_var(r6, r2); // s99 rotr
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r5 = r5 ^ r1; // s100 xor
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r3 = r3 + r7 + ((((sel >> 7u) & 1u) != 0u) ? 0x3d25f873u : 0x60f87347u); // s101 add
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r3 = r3 - r5; // s102 sub
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r3 = r3 - r6; // s103 sub
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r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r6, 4); // s104 shfl
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r3 = r3 | r5; // s105 or
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r0 = r0 + r1 + ((((sel >> 22u) & 1u) != 0u) ? 0x018722b4u : 0x9a16bcfbu); // s106 add
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r2 = r2 + r5 + ((((sel >> 6u) & 1u) != 0u) ? 0x44cbb3d8u : 0xbc4b5e44u); // s107 add
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r2 = r6 * r1 + r2; // s108 mad
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r0 = r0 ^ r1; // s109 xor
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r4 = r4 | r2; // s110 or
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r2 = rotl_imm(r2, 13u); // s111 rotl
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r5 = __umulhi(r5, r2); // s112 mulhi
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r5 = r5 ^ r1; // s113 xor
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r0 = rotl_imm(r0, 15u); // s114 rotl
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r7 = r7 * r0; // s115 mul
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r0 = r7 * r0 + r0; // s116 mad
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|
r4 = rotl_imm(r4, 12u); // s117 rotl
|
|
r1 = r1 * r6; // s118 mul
|
|
r0 = __umulhi(r0, r3); // s119 mulhi
|
|
r4 = r0 * r0 + r4; // s120 mad
|
|
r0 = r0 + r5 + ((((sel >> 16u) & 1u) != 0u) ? 0x153e7b81u : 0x227a1887u); // s121 add
|
|
r6 = r6 + r3 + ((((sel >> 31u) & 1u) != 0u) ? 0x537e0843u : 0xfbb1908bu); // s122 add
|
|
r4 = __umulhi(r4, r5); // s123 mulhi
|
|
r3 = r3 ^ r1; // s124 xor
|
|
r3 = r3 + r7 + ((((sel >> 15u) & 1u) != 0u) ? 0xc2875857u : 0xc3e1337du); // s125 add
|
|
r4 = rotr_var(r4, r7); // s126 rotr
|
|
r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r0, 2); // s127 shfl
|
|
r3 = rotr_var(r3, r6); // s128 rotr
|
|
r1 = r1 * r0; // s129 mul
|
|
r4 = r4 ^ __shfl_xor_sync(0xffffffffu, r1, 16); // s130 shfl
|
|
r4 = r4 + r0 + ((((sel >> 5u) & 1u) != 0u) ? 0x39900c5eu : 0x87bd1ad9u); // s131 add
|
|
r3 = r0 * r3 + r3; // s132 mad
|
|
r4 = r4 * r2; // s133 mul
|
|
r5 = r6 * r0 + r5; // s134 mad
|
|
r4 = r5 * r4 + r4; // s135 mad
|
|
r6 = r6 + r3 + ((((sel >> 28u) & 1u) != 0u) ? 0xcb7e81cau : 0xc59dd71du); // s136 add
|
|
r7 = r7 * r5; // s137 mul
|
|
r6 = r6 * r3; // s138 mul
|
|
r0 = rotr_var(r0, r4); // s139 rotr
|
|
r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r5, 16); // s140 shfl
|
|
r6 = rotr_var(r6, r7); // s141 rotr
|
|
r3 = r3 * r7; // s142 mul
|
|
r0 = r0 + r7 + ((((sel >> 9u) & 1u) != 0u) ? 0x602dc90du : 0x273f8ee2u); // s143 add
|
|
r5 = rotl_imm(r5, 26u); // s144 rotl
|
|
r2 = r2 ^ r4; // s145 xor
|
|
r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r5, 16); // s146 shfl
|
|
r1 = r1 * r4; // s147 mul
|
|
r2 = r1 * r7 + r2; // s148 mad
|
|
r7 = rotr_var(r7, r2); // s149 rotr
|
|
r7 = rotr_var(r7, r3); // s150 rotr
|
|
r5 = r5 + r2 + ((((sel >> 17u) & 1u) != 0u) ? 0xb3e8ca69u : 0x6f435830u); // s151 add
|
|
r6 = r6 ^ r2; // s152 xor
|
|
r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r2, 16); // s153 shfl
|
|
r2 = r2 ^ r6; // s154 xor
|
|
r5 = rotr_var(r5, r7); // s155 rotr
|
|
r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r3, 4); // s156 shfl
|
|
r6 = r6 ^ r5; // s157 xor
|
|
r0 = r0 ^ r7; // s158 xor
|
|
r0 = r0 ^ r7; // s159 xor
|
|
r0 = __umulhi(r0, r3); // s160 mulhi
|
|
r1 = r1 * r5; // s161 mul
|
|
r4 = rotr_var(r4, r0); // s162 rotr
|
|
r4 = r1 * r2 + r4; // s163 mad
|
|
r3 = r3 + r6 + ((((sel >> 18u) & 1u) != 0u) ? 0xe88bec07u : 0x7b5c68f7u); // s164 add
|
|
r0 = rotl_imm(r0, 13u); // s165 rotl
|
|
r2 = r2 ^ r6; // s166 xor
|
|
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r4, 16); // s167 shfl
|
|
r2 = r2 ^ __shfl_xor_sync(0xffffffffu, r7, 2); // s168 shfl
|
|
r7 = r7 ^ r6; // s169 xor
|
|
r0 = r7 * r2 + r0; // s170 mad
|
|
r3 = rotl_imm(r3, 3u); // s171 rotl
|
|
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r6, 2); // s172 shfl
|
|
r0 = r0 + r1 + ((((sel >> 28u) & 1u) != 0u) ? 0xadc930fcu : 0xc53a1209u); // s173 add
|
|
r0 = r0 * r6; // s174 mul
|
|
r7 = __umulhi(r7, r0); // s175 mulhi
|
|
r3 = r3 | r2; // s176 or
|
|
r4 = r4 + r3 + ((((sel >> 16u) & 1u) != 0u) ? 0x36cdb68eu : 0x2def94b8u); // s177 add
|
|
r6 = r6 ^ r2; // s178 xor
|
|
r0 = rotl_imm(r0, 16u); // s179 rotl
|
|
r4 = r4 + r3 + ((((sel >> 5u) & 1u) != 0u) ? 0x230f4372u : 0x774065efu); // s180 add
|
|
r6 = r2 * r2 + r6; // s181 mad
|
|
r4 = r4 + r5 + ((((sel >> 18u) & 1u) != 0u) ? 0xbc379c7cu : 0x8c37e75bu); // s182 add
|
|
r0 = rotl_imm(r0, 26u); // s183 rotl
|
|
r4 = r4 | r2; // s184 or
|
|
r0 = r0 * r2; // s185 mul
|
|
r3 = r3 | r5; // s186 or
|
|
r1 = __umulhi(r1, r0); // s187 mulhi
|
|
r4 = r4 ^ __shfl_xor_sync(0xffffffffu, r2, 16); // s188 shfl
|
|
r5 = rotr_var(r5, r4); // s189 rotr
|
|
r3 = r0 * r3 + r3; // s190 mad
|
|
r1 = r1 | r7; // s191 or
|
|
r7 = r7 | r1; // s192 or
|
|
r1 = r5 * r4 + r1; // s193 mad
|
|
r0 = r0 - r7; // s194 sub
|
|
r6 = r6 + r0 + ((((sel >> 9u) & 1u) != 0u) ? 0x8751e547u : 0x2f8a59eeu); // s195 add
|
|
r0 = rotl_imm(r0, 8u); // s196 rotl
|
|
r3 = r3 + r4 + ((((sel >> 2u) & 1u) != 0u) ? 0x02b9bb4cu : 0x0f369a86u); // s197 add
|
|
r4 = r4 + r2 + ((((sel >> 11u) & 1u) != 0u) ? 0x74240d4cu : 0xe7922061u); // s198 add
|
|
r2 = r2 * r5; // s199 mul
|
|
r6 = r6 + r7 + ((((sel >> 16u) & 1u) != 0u) ? 0x7649c3c3u : 0xee0e3356u); // s200 add
|
|
r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r1, 16); // s201 shfl
|
|
r4 = r4 * r2; // s202 mul
|
|
r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r2, 1); // s203 shfl
|
|
r7 = r2 * r1 + r7; // s204 mad
|
|
r2 = rotl_imm(r2, 5u); // s205 rotl
|
|
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r1, 8); // s206 shfl
|
|
r7 = r7 * r2; // s207 mul
|
|
r0 = r0 * r3; // s208 mul
|
|
r1 = rotl_imm(r1, 7u); // s209 rotl
|
|
r5 = r5 + r3 + ((((sel >> 23u) & 1u) != 0u) ? 0x3d8f8187u : 0xc8db10a0u); // s210 add
|
|
r5 = r5 - r0; // s211 sub
|
|
r0 = rotr_var(r0, r7); // s212 rotr
|
|
r4 = r4 ^ __shfl_xor_sync(0xffffffffu, r2, 8); // s213 shfl
|
|
r1 = r1 ^ r3; // s214 xor
|
|
r1 = rotl_imm(r1, 19u); // s215 rotl
|
|
r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r3, 2); // s216 shfl
|
|
r2 = __umulhi(r2, r5); // s217 mulhi
|
|
r5 = rotl_imm(r5, 14u); // s218 rotl
|
|
r2 = r2 ^ __shfl_xor_sync(0xffffffffu, r1, 8); // s219 shfl
|
|
r7 = r7 - r5; // s220 sub
|
|
r3 = __umulhi(r3, r6); // s221 mulhi
|
|
r7 = r7 | r1; // s222 or
|
|
r1 = __umulhi(r1, r5); // s223 mulhi
|
|
r7 = r7 + r5 + ((((sel >> 24u) & 1u) != 0u) ? 0xd5a3fb54u : 0x689cdcf5u); // s224 add
|
|
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r7, 16); // s225 shfl
|
|
r3 = __umulhi(r3, r2); // s226 mulhi
|
|
r0 = r0 ^ r2; // s227 xor
|
|
r7 = r7 + r4 + ((((sel >> 8u) & 1u) != 0u) ? 0xba3b9728u : 0x267f928du); // s228 add
|
|
r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r7, 2); // s229 shfl
|
|
r4 = r4 - r6; // s230 sub
|
|
r0 = r0 | r1; // s231 or
|
|
r2 = rotl_imm(r2, 10u); // s232 rotl
|
|
r4 = r4 * r7; // s233 mul
|
|
r6 = r0 * r0 + r6; // s234 mad
|
|
r4 = rotl_imm(r4, 29u); // s235 rotl
|
|
r7 = r7 + r2 + ((((sel >> 13u) & 1u) != 0u) ? 0xa437db0eu : 0xed6dd62au); // s236 add
|
|
r4 = rotr_var(r4, r7); // s237 rotr
|
|
r2 = r2 + r0 + ((((sel >> 17u) & 1u) != 0u) ? 0x1c000e82u : 0x9f612006u); // s238 add
|
|
r7 = __umulhi(r7, r5); // s239 mulhi
|
|
r3 = __umulhi(r3, r6); // s240 mulhi
|
|
r0 = r0 ^ r7; // s241 xor
|
|
r4 = rotl_imm(r4, 11u); // s242 rotl
|
|
r3 = rotl_imm(r3, 21u); // s243 rotl
|
|
r4 = r4 + r2 + ((((sel >> 13u) & 1u) != 0u) ? 0x12705678u : 0x83ba196cu); // s244 add
|
|
r7 = r7 + r5 + ((((sel >> 2u) & 1u) != 0u) ? 0xea712528u : 0xa5d39c13u); // s245 add
|
|
r0 = r0 * r5; // s246 mul
|
|
r4 = r4 ^ __shfl_xor_sync(0xffffffffu, r0, 2); // s247 shfl
|
|
r3 = r3 ^ r2; // s248 xor
|
|
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r3, 4); // s249 shfl
|
|
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r3, 16); // s250 shfl
|
|
r5 = r5 + r3 + ((((sel >> 21u) & 1u) != 0u) ? 0x26ce965fu : 0x3006c6ebu); // s251 add
|
|
r3 = rotl_imm(r3, 1u); // s252 rotl
|
|
r7 = __umulhi(r7, r1); // s253 mulhi
|
|
r1 = r1 + r5 + ((((sel >> 1u) & 1u) != 0u) ? 0x9e34c13fu : 0xc2f46c6du); // s254 add
|
|
r4 = rotr_var(r4, r7); // s255 rotr
|
|
}
|
|
}
|
|
uint32_t lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u);
|
|
uint32_t hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u);
|
|
out[gid] = ((uint64_t)hi << 32) | (uint64_t)lo;
|
|
}
|
|
|
|
// Host-side launch wrappers. Declared in program.h, called from host.cu.
|
|
cudaError_t igneum_launch_cache_fill(uint32_t* cache, uint32_t nSegments) {
|
|
if (nSegments == 0u) return cudaErrorInvalidValue;
|
|
uint32_t block = 256u;
|
|
uint32_t grid = (nSegments + block - 1u) / block;
|
|
igneum_cache_fill<<<grid, block>>>(cache, nSegments);
|
|
return cudaGetLastError();
|
|
}
|
|
|
|
cudaError_t igneum_launch_build(uint32_t* ds, const uint32_t* cache, uint32_t nItems) {
|
|
if (nItems == 0u) return cudaErrorInvalidValue;
|
|
uint32_t block = 256u;
|
|
uint32_t grid = (nItems + block - 1u) / block;
|
|
igneum_build<<<grid, block>>>(ds, cache, nItems);
|
|
return cudaGetLastError();
|
|
}
|
|
|
|
cudaError_t igneum_launch_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonce, uint32_t mask,
|
|
uint32_t nonces, uint32_t blockWarps) {
|
|
if (blockWarps == 0u || blockWarps > 32u) return cudaErrorInvalidValue;
|
|
uint32_t block = 32u * blockWarps;
|
|
if (nonces == 0u || (nonces % block) != 0u) return cudaErrorInvalidValue;
|
|
igneum_hash<<<nonces / block, block>>>(ds, out, baseNonce, mask);
|
|
return cudaGetLastError();
|
|
}
|
|
|
|
cudaError_t igneum_hash_info(int* numRegs, int* blocksPerSM, uint32_t blockWarps) {
|
|
cudaFuncAttributes attr;
|
|
cudaError_t e = cudaFuncGetAttributes(&attr, igneum_hash);
|
|
if (e != cudaSuccess) return e;
|
|
*numRegs = attr.numRegs;
|
|
return cudaOccupancyMaxActiveBlocksPerMultiprocessor(blocksPerSM, igneum_hash, (int)(32u * blockWarps), 0);
|
|
}
|