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The merge: accept.rs takes master's shadow pass in run_unit (the per-load sub-blocks keep their place inside the loop; the end-of-iteration pass is empty for that class) and its Acc fields beside site_bit_ones; generator.rs records the per-load and tile id bytes through master's recorder (r.lit "perload", r.lit "mm8/" and the tiles field), nothing for the class v4 shape; export-exclude keeps both sides. The fix (the invention lane's finding, 8 October 2026, 10:48 UTC): BiasedIndexBit judged every index bit, and under an era a narrow-window site's top k bits are fixed by design, so every per-load form read 0 of 256 under any drawn era for the instrument's reason; it now judges only the bits inside each site's window mask (verify::window) and the (c'') pass, which runs the unit with no table, accumulates nothing. The research file's 20.2a-close reads REOPENED (the 16 x 27 form dead on the no-era census on both instruments; the sound form mx8+shl4096x1 accepts 234 of 256 seeds no-era; its drawn-era verdict the invention lane's 15:00 BST read); chip-model-v3 5.11 the same. chip-model-v3 5.12 (main's order, 11:3x UK): the 2 GiB SRAM full store on one N2 reticle (17x at zero shadow, 2.7x to 4.8x with it, USD 400 to 600 of silicon, an N2 project of USD 100 M to 500 M) and the custom HBM4E base die (6.5x to 14x, untouched by the four layers), per-bank PIM's structural blindness, the M5 Max at 0.78 microjoules as the honest denominator; lane B's figures, labelled. docs/design/class-v6-rotating-family.md: section 0's lead on the SRAM store, 0.1 the per-tier schedule table, layers 2 to 4 with lane A's priced schedule (5.5 / 8 / 11 GiB), lane D's three rings and the op-mix band (B = 4 on the injecting families, the lossy sum capped; 8 of 663 eras exhausting at the uncapped corner), the index fold as a layer-1 rule, the measured M5 Max size rows (-12 / -20 / -22 percent of rate at 2 / 4 / 8 GiB), the 5070 Ti stock pair, the x16 mixer rows with build-3's sibling-loaded method (11.4 ms, admissible false on the measurement), 7a lane B, 7b lane A, 7c lane C's layers 5 to 7, section 9 the served-line review for main's 20:00 word. Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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# Paths under the public export list that are NOT exported: research and operations documents written for the
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# team, not for the public spec mirror (one path per line, relative to the repository root; a directory excludes its
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# tree; # comments ignored). Read by tools/ci/identity-check.sh (pruned from the export copy before the grep) and by
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# igneum-public/tools/sync.sh (pruned from the mirror after the copy), so the two can never disagree.
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#
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# Rule (CLAUDE.md, "CI red is stop-the-line", 6 October 2026): a research document that reviews internal operations or
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# quotes the identity patterns as text lives here, outside the export list. A document that IS meant for the mirror is
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# not listed here and must pass the identity grep like everything else the public reads.
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#
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# 6 October 2026, 21:2x UK: the Horizon lane's polish review (lane 6) quotes the overlay network's product name, the
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# intake key variable name and the identity guard's own regexes as text; it blocked every master run from 20:23Z.
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docs/analysis/horizon/polish.md
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# the CI failure classification of 6 October 2026 (an operations document: run ids, step names, the fixes)
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docs/analysis/ci-failures-2026-10-06.md
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# 7 October 2026: the last research round (the mission lanes and the closed list): internal research written for the
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# owner, quoting his words and the operations record; the public spec mirror carries none of it
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docs/analysis/mission
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# 7 October 2026 (night): the Counter ASIC 4.0 research record (an internal research document: the founder's words, box names, lane records)
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docs/analysis/counter-asic-4-research.md
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# 8 October 2026: the class v6 design record (an internal research document: the founder's words, lane records)
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docs/design/class-v6-rotating-family.md
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# 7 October 2026: the in-house adversarial cryptanalysis pass (crypto-engage and the adv-* lanes): rule set, plans, reports and
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# copied logs are research and operations documents, not public export; the public text is the served sentence main landed.
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docs/analysis/cryptanalysis
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docs/plans/cryptanalysis
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# 8 October 2026: the class v6 research lanes (the hardware future, the rotating-family research): internal research written
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# for the founder on the chip model, quoting the operations record; the public text is whatever main lands from the synthesis.
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docs/analysis/class-v6
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