dc84789e34
Nothing changes for the default class: the pinned packs are byte-identical (tests/packs.rs), the v2 draw stream is untouched.
LoadClass {mix, load_slots, scratch}: fixed widths w16, w64, w64x4 (4 loads of 64 B), era mixes 50/35/15 and 25/50/25 drawn per load with one extra below(100) roll, and the scratch variant scr0/2/4/8 (persistent warps, 1 MiB per warp, tagged lazy fill, measurement only). A wide load reads the W-aligned address and folds every word: x = dst ^ w0; x = (rotl(x, 11) * 0x9e3779b1) ^ w[j]. Program ids carry the class. proto-opencl/host.c taken from opencl-rdna4 23810df (--memprobe, select read-back).
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
123 lines
10 KiB
Text
123 lines
10 KiB
Text
// Generated by igneum-pow export (generator v2) for seed "igneum-readwidth/A/2". Do not edit by hand.
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// Header-bound twin of igneum_hash in kernel.cu: the init words come from a kernel argument, not SEEDW.
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// Host declarations (also in program_bound.h if present):
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// struct IgneumInitWords { uint32_t w[8]; };
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// cudaError_t igneum_launch_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t baseNonce, uint32_t mask,
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// IgneumInitWords iw, uint32_t nonces, uint32_t blockWarps);
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// cudaError_t igneum_hash_bound_info(int* numRegs, int* blocksPerSM, uint32_t blockWarps);
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#include <cuda_runtime.h>
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#include <cstdint>
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#include "program.h"
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struct IgneumInitWords { uint32_t w[8]; };
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__device__ __forceinline__ uint32_t splitmix32(uint32_t x) {
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x ^= x >> 16; x *= 0x7feb352du;
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x ^= x >> 15; x *= 0x846ca68bu;
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x ^= x >> 16;
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return x;
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}
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__device__ __forceinline__ uint32_t rotl_imm(uint32_t x, uint32_t n) { return (x << n) | (x >> (32u - n)); }
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__device__ __forceinline__ uint32_t rotr_var(uint32_t x, uint32_t n) { n &= 31u; return (x >> n) | (x << ((32u - n) & 31u)); }
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__global__ void igneum_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t baseNonce, uint32_t mask, IgneumInitWords iw) {
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uint32_t gid = blockIdx.x * blockDim.x + threadIdx.x;
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uint32_t nonce = baseNonce + gid;
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uint32_t r0, r1, r2, r3, r4, r5, r6, r7;
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{ uint32_t x = nonce ^ iw.w[0]; x += 0x9e3779b9u * 1u; x = splitmix32(x); r0 = x ^ iw.w[1]; }
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{ uint32_t x = nonce ^ iw.w[1]; x += 0x9e3779b9u * 2u; x = splitmix32(x); r1 = x ^ iw.w[2]; }
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{ uint32_t x = nonce ^ iw.w[2]; x += 0x9e3779b9u * 3u; x = splitmix32(x); r2 = x ^ iw.w[3]; }
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{ uint32_t x = nonce ^ iw.w[3]; x += 0x9e3779b9u * 4u; x = splitmix32(x); r3 = x ^ iw.w[4]; }
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{ uint32_t x = nonce ^ iw.w[4]; x += 0x9e3779b9u * 5u; x = splitmix32(x); r4 = x ^ iw.w[5]; }
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{ uint32_t x = nonce ^ iw.w[5]; x += 0x9e3779b9u * 6u; x = splitmix32(x); r5 = x ^ iw.w[6]; }
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{ uint32_t x = nonce ^ iw.w[6]; x += 0x9e3779b9u * 7u; x = splitmix32(x); r6 = x ^ iw.w[7]; }
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{ uint32_t x = nonce ^ iw.w[7]; x += 0x9e3779b9u * 8u; x = splitmix32(x); r7 = x ^ iw.w[0]; }
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for (uint32_t it = 0u; it < 8u; ++it) {
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uint32_t sel = r0;
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r2 = r2 + r7 + ((((sel >> 7u) & 1u) != 0u) ? 0xd8952471u : 0x17c8e8eeu); // 0 add
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r0 = rotr_var(r0, r5); // 1 rotr
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r5 = r5 + r0 + ((((sel >> 21u) & 1u) != 0u) ? 0x4325cc6au : 0x37d9560au); // 2 add
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r7 = r7 ^ r5; // 3 xor
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{ uint32_t b_ = (r0 & mask) & ~15u; const uint4* l_ = (const uint4*)(ds + b_); uint4 v0_ = l_[0]; uint4 v1_ = l_[1]; uint4 v2_ = l_[2]; uint4 v3_ = l_[3]; uint32_t x_ = r3 ^ v0_.x; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v0_.y; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v0_.z; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v0_.w; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v1_.x; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v1_.y; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v1_.z; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v1_.w; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v2_.x; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v2_.y; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v2_.z; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v2_.w; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v3_.x; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v3_.y; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v3_.z; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v3_.w; r3 = x_; } // 4 load
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{ uint32_t b_ = (r7 & mask) & ~3u; const uint4* l_ = (const uint4*)(ds + b_); uint4 v0_ = l_[0]; uint32_t x_ = r5 ^ v0_.x; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v0_.y; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v0_.z; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v0_.w; r5 = x_; } // 5 load
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r0 = __umulhi(r0, r5); // 6 mulhi
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r4 = r4 * r7; // 7 mul
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r0 = r5 * r6 + r0; // 8 mad
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{ uint32_t b_ = (r2 & mask) & ~3u; const uint4* l_ = (const uint4*)(ds + b_); uint4 v0_ = l_[0]; uint32_t x_ = r6 ^ v0_.x; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v0_.y; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v0_.z; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v0_.w; r6 = x_; } // 9 load
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r0 = r0 ^ r6; // 10 xor
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r5 = r5 + r3 + ((((sel >> 22u) & 1u) != 0u) ? 0x81619a4cu : 0xbc4eca12u); // 11 add
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r4 = __umulhi(r4, r2); // 12 mulhi
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r2 = r2 ^ ds[r0 & mask]; // 13 load
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r0 = r0 + r2 + ((((sel >> 3u) & 1u) != 0u) ? 0xa557fd2bu : 0xcf9919eeu); // 14 add
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r4 = r4 + r5 + ((((sel >> 7u) & 1u) != 0u) ? 0x33857f70u : 0x36ec1d20u); // 15 add
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r7 = r7 + r5 + ((((sel >> 6u) & 1u) != 0u) ? 0x40495714u : 0x42f5db15u); // 16 add
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r7 = r7 ^ ds[r5 & mask]; // 17 load
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r3 = r3 ^ r6; // 18 xor
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{ uint32_t b_ = (r2 & mask) & ~15u; const uint4* l_ = (const uint4*)(ds + b_); uint4 v0_ = l_[0]; uint4 v1_ = l_[1]; uint4 v2_ = l_[2]; uint4 v3_ = l_[3]; uint32_t x_ = r7 ^ v0_.x; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v0_.y; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v0_.z; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v0_.w; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v1_.x; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v1_.y; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v1_.z; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v1_.w; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v2_.x; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v2_.y; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v2_.z; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v2_.w; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v3_.x; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v3_.y; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v3_.z; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v3_.w; r7 = x_; } // 19 load
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{ uint32_t b_ = (r3 & mask) & ~3u; const uint4* l_ = (const uint4*)(ds + b_); uint4 v0_ = l_[0]; uint32_t x_ = r5 ^ v0_.x; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v0_.y; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v0_.z; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v0_.w; r5 = x_; } // 20 load
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r1 = r1 ^ ds[r0 & mask]; // 21 load
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r1 = __umulhi(r1, r3); // 22 mulhi
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r1 = rotr_var(r1, r5); // 23 rotr
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r2 = __umulhi(r2, r0); // 24 mulhi
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{ uint32_t b_ = (r4 & mask) & ~15u; const uint4* l_ = (const uint4*)(ds + b_); uint4 v0_ = l_[0]; uint4 v1_ = l_[1]; uint4 v2_ = l_[2]; uint4 v3_ = l_[3]; uint32_t x_ = r0 ^ v0_.x; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v0_.y; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v0_.z; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v0_.w; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v1_.x; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v1_.y; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v1_.z; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v1_.w; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v2_.x; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v2_.y; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v2_.z; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v2_.w; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v3_.x; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v3_.y; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v3_.z; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v3_.w; r0 = x_; } // 25 load
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{ uint32_t b_ = (r1 & mask) & ~3u; const uint4* l_ = (const uint4*)(ds + b_); uint4 v0_ = l_[0]; uint32_t x_ = r0 ^ v0_.x; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v0_.y; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v0_.z; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v0_.w; r0 = x_; } // 26 load
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r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r2, 2); // 27 shfl
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r5 = r5 + r4 + ((((sel >> 12u) & 1u) != 0u) ? 0x58a2eb85u : 0x22029cb9u); // 28 add
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{ uint32_t b_ = (r5 & mask) & ~3u; const uint4* l_ = (const uint4*)(ds + b_); uint4 v0_ = l_[0]; uint32_t x_ = r2 ^ v0_.x; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v0_.y; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v0_.z; x_ = (rotl_imm(x_, 11u) * 0x9e3779b1u) ^ v0_.w; r2 = x_; } // 29 load
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r6 = r6 * r5; // 30 mul
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r6 = r6 ^ ds[r2 & mask]; // 31 load
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r7 = __umulhi(r7, r5); // 32 mulhi
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r0 = r0 ^ ds[r7 & mask]; // 33 load
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r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r2, 1); // 34 shfl
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r7 = r7 * r0; // 35 mul
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r5 = r5 ^ ds[r7 & mask]; // 36 load
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r3 = rotr_var(r3, r2); // 37 rotr
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r6 = rotl_imm(r6, 1u); // 38 rotl
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r3 = r3 * r0; // 39 mul
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r3 = __umulhi(r3, r7); // 40 mulhi
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r5 = r5 ^ r2; // 41 xor
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r4 = r4 * r0; // 42 mul
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r3 = r3 + r0 + ((((sel >> 4u) & 1u) != 0u) ? 0xfaaf2d1eu : 0x831bfab3u); // 43 add
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r0 = r1 * r6 + r0; // 44 mad
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r6 = rotl_imm(r6, 26u); // 45 rotl
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r2 = r2 ^ r1; // 46 xor
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r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r7, 2); // 47 shfl
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r1 = r1 ^ r2; // 48 xor
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r3 = r3 + r5 + ((((sel >> 7u) & 1u) != 0u) ? 0xc5759120u : 0x31df1a86u); // 49 add
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r1 = r4 * r1 + r1; // 50 mad
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r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r4, 2); // 51 shfl
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r5 = r5 + r4 + ((((sel >> 16u) & 1u) != 0u) ? 0x4e4a2759u : 0x553b85d1u); // 52 add
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r1 = r1 ^ ds[r3 & mask]; // 53 load
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r6 = rotl_imm(r6, 21u); // 54 rotl
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r1 = __umulhi(r1, r4); // 55 mulhi
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r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r3, 1); // 56 shfl
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r1 = r1 ^ r2; // 57 xor
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r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r6, 16); // 58 shfl
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r5 = r5 * r0; // 59 mul
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r4 = r4 ^ ds[r2 & mask]; // 60 load
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r0 = rotr_var(r0, r4); // 61 rotr
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r6 = r6 * r7; // 62 mul
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r6 = rotl_imm(r6, 2u); // 63 rotl
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}
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uint32_t lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u);
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uint32_t hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u);
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out[gid] = ((uint64_t)hi << 32) | (uint64_t)lo;
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}
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cudaError_t igneum_launch_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t baseNonce, uint32_t mask,
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IgneumInitWords iw, uint32_t nonces, uint32_t blockWarps) {
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if (blockWarps == 0u || blockWarps > 32u) return cudaErrorInvalidValue;
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uint32_t block = 32u * blockWarps;
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if (nonces == 0u || (nonces % block) != 0u) return cudaErrorInvalidValue;
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igneum_hash_bound<<<nonces / block, block>>>(ds, out, baseNonce, mask, iw);
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return cudaGetLastError();
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}
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cudaError_t igneum_hash_bound_info(int* numRegs, int* blocksPerSM, uint32_t blockWarps) {
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cudaFuncAttributes attr;
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cudaError_t e = cudaFuncGetAttributes(&attr, igneum_hash_bound);
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if (e != cudaSuccess) return e;
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*numRegs = attr.numRegs;
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return cudaOccupancyMaxActiveBlocksPerMultiprocessor(blocksPerSM, igneum_hash_bound, (int)(32u * blockWarps), 0);
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}
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