Igneum: the GPU-mined zkEVM L1. Node, miner, app, spec and site.
cebedaf9ea
The merge: accept.rs takes master's shadow pass in run_unit (the per-load sub-blocks keep their place inside the loop; the end-of-iteration pass is empty for that class) and its Acc fields beside site_bit_ones; generator.rs records the per-load and tile id bytes through master's recorder (r.lit "perload", r.lit "mm8/" and the tiles field), nothing for the class v4 shape; export-exclude keeps both sides. The fix (the invention lane's finding, 8 October 2026, 10:48 UTC): BiasedIndexBit judged every index bit, and under an era a narrow-window site's top k bits are fixed by design, so every per-load form read 0 of 256 under any drawn era for the instrument's reason; it now judges only the bits inside each site's window mask (verify::window) and the (c'') pass, which runs the unit with no table, accumulates nothing. The research file's 20.2a-close reads REOPENED (the 16 x 27 form dead on the no-era census on both instruments; the sound form mx8+shl4096x1 accepts 234 of 256 seeds no-era; its drawn-era verdict the invention lane's 15:00 BST read); chip-model-v3 5.11 the same. chip-model-v3 5.12 (main's order, 11:3x UK): the 2 GiB SRAM full store on one N2 reticle (17x at zero shadow, 2.7x to 4.8x with it, USD 400 to 600 of silicon, an N2 project of USD 100 M to 500 M) and the custom HBM4E base die (6.5x to 14x, untouched by the four layers), per-bank PIM's structural blindness, the M5 Max at 0.78 microjoules as the honest denominator; lane B's figures, labelled. docs/design/class-v6-rotating-family.md: section 0's lead on the SRAM store, 0.1 the per-tier schedule table, layers 2 to 4 with lane A's priced schedule (5.5 / 8 / 11 GiB), lane D's three rings and the op-mix band (B = 4 on the injecting families, the lossy sum capped; 8 of 663 eras exhausting at the uncapped corner), the index fold as a layer-1 rule, the measured M5 Max size rows (-12 / -20 / -22 percent of rate at 2 / 4 / 8 GiB), the 5070 Ti stock pair, the x16 mixer rows with build-3's sibling-loaded method (11.4 ms, admissible false on the measurement), 7a lane B, 7b lane A, 7c lane C's layers 5 to 7, section 9 the served-line review for main's 20:00 word. Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com> |
||
|---|---|---|
| .claude/agents | ||
| .github/workflows | ||
| app | ||
| brand | ||
| docs | ||
| igneum-census | ||
| igneum-pow | ||
| infra | ||
| packaging | ||
| pool | ||
| proto-cuda | ||
| proto-metal | ||
| proto-newpow | ||
| proto-opencl | ||
| proto-vdf | ||
| proving | ||
| relay | ||
| scene | ||
| sim | ||
| site | ||
| tools | ||
| .gitignore | ||
| .vercelignore | ||
| CLAUDE.md | ||
| rust-toolchain.toml | ||