igneum-labs c8e8b82add Class v6 floor lane 5 (invention): the knee row from PC 1 (the hash lane, kit d): at the 1,300 lock the hinted w64 form reads 37.6 against the 4-byte row's 100.6 MH/s at 2.3x the energy per hash, so W = 16 is dead at the knee as at stock; every row this lane owed on W = 16 is closed ... Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>		2026-10-08 14:04:48 +00:00
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floor	Class v6 floor lane 5 (invention): the knee row from PC 1 (the hash lane, kit d): at the 1,300 lock the hinted w64 form reads 37.6 against the 4-byte row's 100.6 MH/s at 2.3x the energy per hash, so W = 16 is dead at the knee as at stock; every row this lane owed on W = 16 is closed	2026-10-08 14:04:48 +00:00
hardware-future.md	Class v6 research lane B: the hardware future, five years out (first cut and the full report in one file)	2026-10-08 10:17:50 +00:00
history.md	Class v6 history lane, first cut: every ASIC-resistant proof of work and its chips by mechanism, the four-layer mapping with a number per chip class, and the three lessons that bind on v6	2026-10-08 10:19:10 +00:00