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tb_core_common.vh
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shadow-k: the design sweep (64 registers k 0.78, 1,024 imem 0.97 as built and about 0.6 with SRAM, select tree 0.55), the sweep variants' RTL and configs, the synthesis-row driver, the steady-state solve in the collector
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2026-10-08 14:32:45 +00:00 |
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tb_core_legacy.vh
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shadow-k: the design sweep (64 registers k 0.78, 1,024 imem 0.97 as built and about 0.6 with SRAM, select tree 0.55), the sweep variants' RTL and configs, the synthesis-row driver, the steady-state solve in the collector
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2026-10-08 14:32:45 +00:00 |
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tb_core_v6_8.v
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shadow-k: the design sweep (64 registers k 0.78, 1,024 imem 0.97 as built and about 0.6 with SRAM, select tree 0.55), the sweep variants' RTL and configs, the synthesis-row driver, the steady-state solve in the collector
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2026-10-08 14:32:45 +00:00 |
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tb_core_v6_8i1k.v
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shadow-k: the design sweep (64 registers k 0.78, 1,024 imem 0.97 as built and about 0.6 with SRAM, select tree 0.55), the sweep variants' RTL and configs, the synthesis-row driver, the steady-state solve in the collector
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2026-10-08 14:32:45 +00:00 |
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tb_core_v6_8r64.v
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shadow-k: the design sweep (64 registers k 0.78, 1,024 imem 0.97 as built and about 0.6 with SRAM, select tree 0.55), the sweep variants' RTL and configs, the synthesis-row driver, the steady-state solve in the collector
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2026-10-08 14:32:45 +00:00 |
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tb_core_v6_8sel.v
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shadow-k: the design sweep (64 registers k 0.78, 1,024 imem 0.97 as built and about 0.6 with SRAM, select tree 0.55), the sweep variants' RTL and configs, the synthesis-row driver, the steady-state solve in the collector
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2026-10-08 14:32:45 +00:00 |
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tb_core_v6_32.v
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shadow-k: the design sweep (64 registers k 0.78, 1,024 imem 0.97 as built and about 0.6 with SRAM, select tree 0.55), the sweep variants' RTL and configs, the synthesis-row driver, the steady-state solve in the collector
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2026-10-08 14:32:45 +00:00 |
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tb_core_v6_32all.v
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shadow-k: the design sweep (64 registers k 0.78, 1,024 imem 0.97 as built and about 0.6 with SRAM, select tree 0.55), the sweep variants' RTL and configs, the synthesis-row driver, the steady-state solve in the collector
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2026-10-08 14:32:45 +00:00 |
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tb_core_v6_32r16.v
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shadow-k: the design sweep (64 registers k 0.78, 1,024 imem 0.97 as built and about 0.6 with SRAM, select tree 0.55), the sweep variants' RTL and configs, the synthesis-row driver, the steady-state solve in the collector
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2026-10-08 14:32:45 +00:00 |
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tb_lane_arx.v
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chip-model: the shadow-k floor lane's RTL, testbenches and ORFS flow (ASAP7) for every class v6 mixer family
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2026-10-08 14:32:43 +00:00 |
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tb_lane_fold.v
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chip-model: the shadow-k floor lane's RTL, testbenches and ORFS flow (ASAP7) for every class v6 mixer family
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2026-10-08 14:32:43 +00:00 |
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tb_lane_lop3.v
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chip-model: the shadow-k floor lane's RTL, testbenches and ORFS flow (ASAP7) for every class v6 mixer family
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2026-10-08 14:32:43 +00:00 |
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tb_lane_mul.v
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chip-model: the shadow-k floor lane's RTL, testbenches and ORFS flow (ASAP7) for every class v6 mixer family
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2026-10-08 14:32:43 +00:00 |
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tb_lane_prmt.v
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chip-model: the shadow-k floor lane's RTL, testbenches and ORFS flow (ASAP7) for every class v6 mixer family
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2026-10-08 14:32:43 +00:00 |
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tb_scratch8k.v
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chip-model: the shadow-k floor lane's RTL, testbenches and ORFS flow (ASAP7) for every class v6 mixer family
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2026-10-08 14:32:43 +00:00 |
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tb_shfl32.v
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chip-model: the shadow-k floor lane's RTL, testbenches and ORFS flow (ASAP7) for every class v6 mixer family
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2026-10-08 14:32:43 +00:00 |
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tb_tile8.v
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chip-model: the shadow-k floor lane's RTL, testbenches and ORFS flow (ASAP7) for every class v6 mixer family
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2026-10-08 14:32:43 +00:00 |
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tb_xbar32.v
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chip-model: the shadow-k floor lane's RTL, testbenches and ORFS flow (ASAP7) for every class v6 mixer family
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2026-10-08 14:32:43 +00:00 |
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