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arx.mk
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chip-model: the shadow-k floor lane's RTL, testbenches and ORFS flow (ASAP7) for every class v6 mixer family
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2026-10-08 12:59:10 +01:00 |
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arx.sdc
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chip-model: the shadow-k floor lane's RTL, testbenches and ORFS flow (ASAP7) for every class v6 mixer family
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2026-10-08 12:59:10 +01:00 |
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collect.py
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shadow-k: the design sweep (64 registers k 0.78, 1,024 imem 0.97 as built and about 0.6 with SRAM, select tree 0.55), the sweep variants' RTL and configs, the synthesis-row driver, the steady-state solve in the collector
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2026-10-08 14:51:23 +01:00 |
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core8.mk
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chip-model: the programmable shadow core (core_v6: imem, fetch, decode, per-lane register file, the class units, era registers), 8, 32 and 32-lane 16-register builds, synthesis-only power path
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2026-10-08 13:18:54 +01:00 |
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core8.sdc
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chip-model: the programmable shadow core (core_v6: imem, fetch, decode, per-lane register file, the class units, era registers), 8, 32 and 32-lane 16-register builds, synthesis-only power path
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2026-10-08 13:18:54 +01:00 |
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core8i1k.mk
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shadow-k: the design sweep (64 registers k 0.78, 1,024 imem 0.97 as built and about 0.6 with SRAM, select tree 0.55), the sweep variants' RTL and configs, the synthesis-row driver, the steady-state solve in the collector
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2026-10-08 14:51:23 +01:00 |
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core8i1k.sdc
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shadow-k: the design sweep (64 registers k 0.78, 1,024 imem 0.97 as built and about 0.6 with SRAM, select tree 0.55), the sweep variants' RTL and configs, the synthesis-row driver, the steady-state solve in the collector
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2026-10-08 14:51:23 +01:00 |
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core8r64.mk
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shadow-k: the design sweep (64 registers k 0.78, 1,024 imem 0.97 as built and about 0.6 with SRAM, select tree 0.55), the sweep variants' RTL and configs, the synthesis-row driver, the steady-state solve in the collector
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2026-10-08 14:51:23 +01:00 |
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core8r64.sdc
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shadow-k: the design sweep (64 registers k 0.78, 1,024 imem 0.97 as built and about 0.6 with SRAM, select tree 0.55), the sweep variants' RTL and configs, the synthesis-row driver, the steady-state solve in the collector
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2026-10-08 14:51:23 +01:00 |
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core8sel.mk
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shadow-k: the design sweep (64 registers k 0.78, 1,024 imem 0.97 as built and about 0.6 with SRAM, select tree 0.55), the sweep variants' RTL and configs, the synthesis-row driver, the steady-state solve in the collector
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2026-10-08 14:51:23 +01:00 |
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core8sel.sdc
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shadow-k: the design sweep (64 registers k 0.78, 1,024 imem 0.97 as built and about 0.6 with SRAM, select tree 0.55), the sweep variants' RTL and configs, the synthesis-row driver, the steady-state solve in the collector
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2026-10-08 14:51:23 +01:00 |
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core32.mk
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chip-model: the programmable shadow core (core_v6: imem, fetch, decode, per-lane register file, the class units, era registers), 8, 32 and 32-lane 16-register builds, synthesis-only power path
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2026-10-08 13:18:54 +01:00 |
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core32.sdc
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chip-model: the programmable shadow core (core_v6: imem, fetch, decode, per-lane register file, the class units, era registers), 8, 32 and 32-lane 16-register builds, synthesis-only power path
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2026-10-08 13:18:54 +01:00 |
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core32all.mk
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shadow-k: the design sweep (64 registers k 0.78, 1,024 imem 0.97 as built and about 0.6 with SRAM, select tree 0.55), the sweep variants' RTL and configs, the synthesis-row driver, the steady-state solve in the collector
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2026-10-08 14:51:23 +01:00 |
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core32all.sdc
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shadow-k: the design sweep (64 registers k 0.78, 1,024 imem 0.97 as built and about 0.6 with SRAM, select tree 0.55), the sweep variants' RTL and configs, the synthesis-row driver, the steady-state solve in the collector
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2026-10-08 14:51:23 +01:00 |
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core32r16.mk
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chip-model: the programmable shadow core (core_v6: imem, fetch, decode, per-lane register file, the class units, era registers), 8, 32 and 32-lane 16-register builds, synthesis-only power path
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2026-10-08 13:18:54 +01:00 |
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core32r16.sdc
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chip-model: the programmable shadow core (core_v6: imem, fetch, decode, per-lane register file, the class units, era registers), 8, 32 and 32-lane 16-register builds, synthesis-only power path
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2026-10-08 13:18:54 +01:00 |
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designs.txt
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shadow-k: the design sweep (64 registers k 0.78, 1,024 imem 0.97 as built and about 0.6 with SRAM, select tree 0.55), the sweep variants' RTL and configs, the synthesis-row driver, the steady-state solve in the collector
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2026-10-08 14:51:23 +01:00 |
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edge.py
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shadow-k: the programmable core's synthesis-only row (6.9 pJ per lane-op ASAP7, k 0.56 at the lock at N3), the edge table in the absolute convention, the lease-routed Makefile
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2026-10-08 14:05:13 +01:00 |
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fold.mk
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chip-model: the shadow-k floor lane's RTL, testbenches and ORFS flow (ASAP7) for every class v6 mixer family
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2026-10-08 12:59:10 +01:00 |
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fold.sdc
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chip-model: the shadow-k floor lane's RTL, testbenches and ORFS flow (ASAP7) for every class v6 mixer family
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2026-10-08 12:59:10 +01:00 |
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gl2sim.sh
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chip-model: the programmable shadow core (core_v6: imem, fetch, decode, per-lane register file, the class units, era registers), 8, 32 and 32-lane 16-register builds, synthesis-only power path
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2026-10-08 13:18:54 +01:00 |
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lop3.mk
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chip-model: the shadow-k floor lane's RTL, testbenches and ORFS flow (ASAP7) for every class v6 mixer family
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2026-10-08 12:59:10 +01:00 |
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lop3.sdc
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chip-model: the shadow-k floor lane's RTL, testbenches and ORFS flow (ASAP7) for every class v6 mixer family
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2026-10-08 12:59:10 +01:00 |
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mix.py
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chip-model: shadow-k collector, mix optimiser, edge rows; the report's method sections
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2026-10-08 13:05:02 +01:00 |
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mul.mk
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chip-model: the shadow-k floor lane's RTL, testbenches and ORFS flow (ASAP7) for every class v6 mixer family
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2026-10-08 12:59:10 +01:00 |
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mul.sdc
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chip-model: the shadow-k floor lane's RTL, testbenches and ORFS flow (ASAP7) for every class v6 mixer family
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2026-10-08 12:59:10 +01:00 |
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power.tcl
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shadow-k: the programmable core's synthesis-only row (6.9 pJ per lane-op ASAP7, k 0.56 at the lock at N3), the edge table in the absolute convention, the lease-routed Makefile
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2026-10-08 14:05:13 +01:00 |
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prmt.mk
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chip-model: the shadow-k floor lane's RTL, testbenches and ORFS flow (ASAP7) for every class v6 mixer family
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2026-10-08 12:59:10 +01:00 |
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prmt.sdc
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chip-model: the shadow-k floor lane's RTL, testbenches and ORFS flow (ASAP7) for every class v6 mixer family
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2026-10-08 12:59:10 +01:00 |
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scratch.mk
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chip-model: shadow-k collector, mix optimiser, edge rows; the report's method sections
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2026-10-08 13:05:02 +01:00 |
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scratch.sdc
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chip-model: the shadow-k floor lane's RTL, testbenches and ORFS flow (ASAP7) for every class v6 mixer family
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2026-10-08 12:59:10 +01:00 |
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shfl.mk
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chip-model: shadow-k collector, mix optimiser, edge rows; the report's method sections
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2026-10-08 13:05:02 +01:00 |
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shfl.sdc
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chip-model: the shadow-k floor lane's RTL, testbenches and ORFS flow (ASAP7) for every class v6 mixer family
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2026-10-08 12:59:10 +01:00 |
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sim.sh
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chip-model: the programmable shadow core (core_v6: imem, fetch, decode, per-lane register file, the class units, era registers), 8, 32 and 32-lane 16-register builds, synthesis-only power path
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2026-10-08 13:18:54 +01:00 |
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synthrow.sh
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shadow-k: the design sweep (64 registers k 0.78, 1,024 imem 0.97 as built and about 0.6 with SRAM, select tree 0.55), the sweep variants' RTL and configs, the synthesis-row driver, the steady-state solve in the collector
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2026-10-08 14:51:23 +01:00 |
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tile.mk
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chip-model: the shadow-k floor lane's RTL, testbenches and ORFS flow (ASAP7) for every class v6 mixer family
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2026-10-08 12:59:10 +01:00 |
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tile.sdc
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chip-model: the shadow-k floor lane's RTL, testbenches and ORFS flow (ASAP7) for every class v6 mixer family
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2026-10-08 12:59:10 +01:00 |
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xbar.mk
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chip-model: shadow-k collector, mix optimiser, edge rows; the report's method sections
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2026-10-08 13:05:02 +01:00 |
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xbar.sdc
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chip-model: the shadow-k floor lane's RTL, testbenches and ORFS flow (ASAP7) for every class v6 mixer family
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2026-10-08 12:59:10 +01:00 |
