igneum-labs 1c02320532 Merge class-v6-history fd32fdc5 into master (gate: green on fd32fdc5, recorded by tools/ci/pre-push.sh; landed on the build mirror)		2026-10-08 10:45:04 +00:00
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family-gate.md	Class v6 family gate (lane D), first cut: the parameter table with bands and margins, the sampling bound (rule of three, the union bound over the per-era tests' measured miss rates, the stratified corners), the three rings of per-era tests with known-failed shapes and clean-seed costs, the board over the testnet period and the proof-of-testing record format, the honest line; the harness running on the boxes and its first 16-era reading (the era-stride class at 130 to 511 sigma on one address bit in 7 of 16 drawn eras); docs/analysis/class-v6 excluded from the public export	2026-10-08 10:25:17 +00:00
hardware-future.md	Class v6 research lane B: the hardware future, five years out (first cut and the full report in one file)	2026-10-08 10:17:50 +00:00
history.md	Class v6 history lane, revision 3: the dataset-floor schedule priced per tier and against the chips (section 4.2a, main's ask of 11:2x UK)	2026-10-08 10:38:53 +00:00