igneum-labs 6a1943efc0 Class v6 floor lane 3: section 2.2c (W = 16 across the three chips: the die 66x to 19x if the 5090 passes, 36x at the measured w64 row; GDDR7 4.4x, HBM3 6.7x) and section 4.3 (the capex wall on the corrected USD 20 to 75 M project floor: no chip project below USD 23 M a year of miner revenue, every DRAM-board project above USD 340 M) ... Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com> Documents-only replay of 7bc9de4b4 (8e9588de0) for the box mirror master		2026-10-08 12:29:15 +00:00
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floor	Class v6 floor lane 3: section 2.2c (W = 16 across the three chips: the die 66x to 19x if the 5090 passes, 36x at the measured w64 row; GDDR7 4.4x, HBM3 6.7x) and section 4.3 (the capex wall on the corrected USD 20 to 75 M project floor: no chip project below USD 23 M a year of miner revenue, every DRAM-board project above USD 340 M)	2026-10-08 12:29:15 +00:00
logs	Merge class-v6-family-gate a39dbeca into master (gate: green on a39dbeca, recorded by tools/ci/pre-push.sh; landed on the build mirror)	2026-10-08 12:12:39 +00:00
family-gate.md	Class v6 family gate, the 17:00 cut: the harness as a plain diff at 3dc3117c (the founder-strings check refuses the patch form's author lines)	2026-10-08 11:35:25 +00:00
hardware-future.md	Class v6 research lane B: the hardware future, five years out (first cut and the full report in one file)	2026-10-08 10:17:50 +00:00
history.md	Class v6 history lane, revision 3: the dataset-floor schedule priced per tier and against the chips (section 4.2a, main's ask of 11:2x UK)	2026-10-08 10:38:53 +00:00
invention.md	Class v6 invention: the 5090 rows for the two per-load packs (the sound form costs the card 15 to 20 percent more per shadow instruction than the whole block, +19 W unlocked and +6.6 W at the knee at class v4's count; rank 1's GPU column corrected, the verdict restated with the honest sign)	2026-10-08 11:45:37 +00:00