igneum/docs/analysis
igneum-labs 4e2a4cd647 Horizon: lane 1 (consensus-security) lands, with the 51 percent paper
docs/analysis/51-percent.md: what a 51 percent attacker can and cannot do on Igneum, with
numbers (the selected-chain race over a 90-s hold, the lock as the reorder bound, the veto
at 1/3 of weight and its rental cost, the departure case and the LEAVE item, the p2p surface).
docs/analysis/horizon/consensus-security.md: the attack catalogue across GHOSTDAG ordering,
the difficulty rule, the finality weight, miner signalling, proof records, the exec layer and
p2p, each with the bound and the rental cost at the measured USD 11.7 per GH/s-hour; the
pruned-node unwrap class with its sibling list in the sync and IBD flows; fourteen ranked
defences, three of them not recommended with the reason.

Models and results: sim/horizon/consensus-security/ (ghostdag_sim.py, finality_horizon.py,
cost_model.py, signalling.py, result files).

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-06 20:07:43 +00:00
..
horizon Horizon: lane 1 (consensus-security) lands, with the 51 percent paper 2026-10-06 20:07:43 +00:00
51-percent.md Horizon: lane 1 (consensus-security) lands, with the 51 percent paper 2026-10-06 20:07:43 +00:00
amd-proving.md docs/analysis/amd-proving.md: no zkVM proves on AMD (SP1, RISC Zero, Jolt, OpenVM, ICICLE cited), the SP1 CPU prover measured on PC 1 beside the miners (282 s a shard at any size, 30 GB RSS: no CPU tier), the tier consequences and the public line; PC 1 job scripts with the bash -n gate; bench-log entry 2026-10-05 21:02:59 +00:00
asic-resistance-history.md docs/analysis/asic-resistance-history.md: the 2011 to 2026 history of ASIC resistance (31 rows, chip, gain per joule, months held, response), the papers, the chip economics and the market-cap table, ten lessons, the audit of class v2 and the Counter ASIC 2.0 layers, seven ranked additions (partial-store chip row first), nine candidates placed nowhere 2026-10-05 22:38:17 +00:00
base-fee-floor.md Prover mirrors the fee switch: both tables and fees_v1_activation_daa in the shard input, guest re-pinned, devnet runbook for H = 210,000 2026-10-05 16:24:35 +00:00
card-lifetime-2026-10-05.md CI on the merged 0.3.11 tree: MacBook reworded in the analysis prose (the identity check's hostname pattern), a presence check before the kit's first use in the three proving-v1 PC 2 scripts (C32), pc1-cpu-prove.ps1 on the socket check's allow list (the CPU path starts no GPU server) 2026-10-05 22:44:09 +00:00
chip-model-v3.md Merge branch 'ca3-derive' into ca3-coord 2026-10-06 07:51:00 +00:00
difficulty-2026-10-03.md Difficulty: timestamp attack fixed in spec 2.3, simulator, analysis addendum, ledger M23 2026-10-04 00:56:20 +00:00
difficulty-2026-10-04-oscillation.md Difficulty: the live oscillation of 4 October, its cause, the DAG replay and rule v2 (reference window 600 behind a height switch) 2026-10-04 13:26:23 +00:00
economy-2026-10-04.md Economy: agent-based mining-versus-proving simulation, six stress scenarios, lever study, analysis and bench entry 2026-10-03 23:16:46 +00:00
hashrate-decay-2026-10-03.md Hash-rate decay on the RTX 5090: diagnosis, Metal reproduction, proposed Seeder fix 2026-10-03 23:31:23 +00:00
hashrate-decay-2026-10-03.patch Hash-rate decay on the RTX 5090: diagnosis, Metal reproduction, proposed Seeder fix 2026-10-03 23:31:23 +00:00
horizon-2026-10.md Horizon: lanes 2 (algorithm), 7 (frontier) and 8 (new-pow designs) land, with the summary skeleton 2026-10-06 19:51:23 +00:00
int8-matrix-family.md Counter ASIC 2.0 layer 7: RTX 5090 and RX 9070 XT dot4 numbers from PC 1 (job run-dot4-20261005): dp4a 7.45 T/s on the 5090 via inline PTX, v_dot4_i32_iu8 0.66 T/s on the 9070 XT via the clang builtin in Adrenalin OpenCL C, signed emulation 7.1x / 1.46x / 4.7x the ALU step on NVIDIA / AMD / Apple; no PC platform lists cl_khr_integer_dot_product 2026-10-05 20:31:33 +00:00
latency-shadow-2026-10-06.md Counter ASIC 3.0 item 8: the RTX 5090 rows, the chip side on the measured 11 pJ per op, the verdict 2026-10-06 08:44:57 +00:00
m16-recompute-attacker-2026-10-05.md FUD sweep round 6 (evening, 5 October): eleven rolled-out fixes moved to Fixed with live measurement lines, F21/F22 shipped but switch not thrown, M20 closed on the 0.3.5 merge; P14 one base-fee definition in spec 05; M16 recompute-attacker cost model; C4 overlay-against-GHOSTDAG runner 2026-10-05 16:02:02 +00:00
prover-floor.md Prover floor: sweep 1 table and reading (the Setup-time keys bind at 12.7 GB) 2026-10-05 22:42:17 +00:00
prover-tiers-real-cards.md Prover tiers on real cards (eleven rented cards, patched SP1 server) and the rental cost of hash: the analysis file and its two bench-log entries, cut from gpu-fleet for the site 2026-10-06 19:21:28 +00:00
proving-methods.md CI on the merged 0.3.11 tree: MacBook reworded in the analysis prose (the identity check's hostname pattern), a presence check before the kit's first use in the three proving-v1 PC 2 scripts (C32), pc1-cpu-prove.ps1 on the socket check's allow list (the CPU path starts no GPU server) 2026-10-05 22:44:09 +00:00
scratch-soundness.md ca2-soundness: docs/analysis/scratch-soundness.md alone (its code is already in the tree through the mixer merge; the branch merge conflicted there); release-0.3.11 plan: C37 and C38 2026-10-05 23:04:38 +00:00
security-budget.md Evidence page, end-to-end proving standard, funding plan, security-budget stress, payment routes 2026-10-03 22:35:03 +00:00
sram-mirror.md Counter ASIC 2.0 layer 6, revision 2: shipped cache-die density (AMD V-Cache 64 MB on 41 mm^2 at 7 nm, Hot Chips 33) as the headline column beside the bit-cell lower bound; mirror 106 to 164 mm^2 and $30 to $56 per die at 256 MiB; year 0 to 10, hot-table and option tables redone; latency citations section (MEMSYS 2018, Chang 2017, mining-chip memory types) 2026-10-05 20:20:46 +00:00
weak-program-census-2026-10-03.md Mac app: dial the public seed node first, the home node second 2026-10-03 22:28:58 +00:00