igneum-josh 6fab785c51 chip-model: shadow-k collector, mix optimiser, edge rows; the report's method sections ... Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>		2026-10-08 13:05:02 +01:00
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floor	chip-model: shadow-k collector, mix optimiser, edge rows; the report's method sections	2026-10-08 13:05:02 +01:00
hardware-future.md	Class v6 research lane B: the hardware future, five years out (first cut and the full report in one file)	2026-10-08 11:17:50 +01:00
history.md	Class v6 history lane, first cut: every ASIC-resistant proof of work and its chips by mechanism, the four-layer mapping with a number per chip class, and the three lessons that bind on v6	2026-10-08 11:19:10 +01:00