igneum-labs 44bb0b406d shadow-k: the design sweep (64 registers k 0.78, 1,024 imem 0.97 as built and about 0.6 with SRAM, select tree 0.55), the sweep variants' RTL and configs, the synthesis-row driver, the steady-state solve in the collector ... Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com> Documents-only replay of 036c1aded (bfccc26ed4) for the box mirror master		2026-10-08 14:32:45 +00:00
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core_v6.v	shadow-k: the design sweep (64 registers k 0.78, 1,024 imem 0.97 as built and about 0.6 with SRAM, select tree 0.55), the sweep variants' RTL and configs, the synthesis-row driver, the steady-state solve in the collector	2026-10-08 14:32:45 +00:00
core_v6_8.v	shadow-k: the design sweep (64 registers k 0.78, 1,024 imem 0.97 as built and about 0.6 with SRAM, select tree 0.55), the sweep variants' RTL and configs, the synthesis-row driver, the steady-state solve in the collector	2026-10-08 14:32:45 +00:00
core_v6_8i1k.v	shadow-k: the design sweep (64 registers k 0.78, 1,024 imem 0.97 as built and about 0.6 with SRAM, select tree 0.55), the sweep variants' RTL and configs, the synthesis-row driver, the steady-state solve in the collector	2026-10-08 14:32:45 +00:00
core_v6_8r64.v	shadow-k: the design sweep (64 registers k 0.78, 1,024 imem 0.97 as built and about 0.6 with SRAM, select tree 0.55), the sweep variants' RTL and configs, the synthesis-row driver, the steady-state solve in the collector	2026-10-08 14:32:45 +00:00
core_v6_8sel.v	shadow-k: the design sweep (64 registers k 0.78, 1,024 imem 0.97 as built and about 0.6 with SRAM, select tree 0.55), the sweep variants' RTL and configs, the synthesis-row driver, the steady-state solve in the collector	2026-10-08 14:32:45 +00:00
core_v6_32.v	shadow-k: the design sweep (64 registers k 0.78, 1,024 imem 0.97 as built and about 0.6 with SRAM, select tree 0.55), the sweep variants' RTL and configs, the synthesis-row driver, the steady-state solve in the collector	2026-10-08 14:32:45 +00:00
core_v6_32all.v	shadow-k: the design sweep (64 registers k 0.78, 1,024 imem 0.97 as built and about 0.6 with SRAM, select tree 0.55), the sweep variants' RTL and configs, the synthesis-row driver, the steady-state solve in the collector	2026-10-08 14:32:45 +00:00
core_v6_32r16.v	shadow-k: the design sweep (64 registers k 0.78, 1,024 imem 0.97 as built and about 0.6 with SRAM, select tree 0.55), the sweep variants' RTL and configs, the synthesis-row driver, the steady-state solve in the collector	2026-10-08 14:32:45 +00:00
lane_arx.v	chip-model: the shadow-k floor lane's RTL, testbenches and ORFS flow (ASAP7) for every class v6 mixer family	2026-10-08 14:32:43 +00:00
lane_common.vh	chip-model: the shadow-k floor lane's RTL, testbenches and ORFS flow (ASAP7) for every class v6 mixer family	2026-10-08 14:32:43 +00:00
lane_fold.v	chip-model: the shadow-k floor lane's RTL, testbenches and ORFS flow (ASAP7) for every class v6 mixer family	2026-10-08 14:32:43 +00:00
lane_lop3.v	chip-model: the shadow-k floor lane's RTL, testbenches and ORFS flow (ASAP7) for every class v6 mixer family	2026-10-08 14:32:43 +00:00
lane_mul.v	chip-model: the shadow-k floor lane's RTL, testbenches and ORFS flow (ASAP7) for every class v6 mixer family	2026-10-08 14:32:43 +00:00
lane_prmt.v	chip-model: the shadow-k floor lane's RTL, testbenches and ORFS flow (ASAP7) for every class v6 mixer family	2026-10-08 14:32:43 +00:00
scratch8k.v	chip-model: the shadow-k floor lane's RTL, testbenches and ORFS flow (ASAP7) for every class v6 mixer family	2026-10-08 14:32:43 +00:00
shfl32.v	chip-model: the shadow-k floor lane's RTL, testbenches and ORFS flow (ASAP7) for every class v6 mixer family	2026-10-08 14:32:43 +00:00
tile8.v	chip-model: the shadow-k floor lane's RTL, testbenches and ORFS flow (ASAP7) for every class v6 mixer family	2026-10-08 14:32:43 +00:00
xbar32.v	chip-model: the shadow-k floor lane's RTL, testbenches and ORFS flow (ASAP7) for every class v6 mixer family	2026-10-08 14:32:43 +00:00