igneum-labs 43adcf75c5 Class v6 family gate, 6.10: the hash lane's layer-8-off draw through the acceptance on class-v6 542cd7028 against the same-crate windowed control (PASS: r 0.18 against 0.27 at width 4, the (c''') cost 2 against 13 percent, 0 hot sets and 0 over 1.2x at 2^20, the bit-R share up with the windows gone, the fold the lever); the harness port diff at 542cd7028 ... Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>		2026-10-08 17:54:46 +00:00
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logs	Class v6 family gate, 6.10: the hash lane's layer-8-off draw through the acceptance on class-v6 542cd7028 against the same-crate windowed control (PASS: r 0.18 against 0.27 at width 4, the (c''') cost 2 against 13 percent, 0 hot sets and 0 over 1.2x at 2^20, the bit-R share up with the windows gone, the fold the lever); the harness port diff at 542cd7028	2026-10-08 17:54:46 +00:00
family-gate.md	Class v6 family gate, 6.10: the hash lane's layer-8-off draw through the acceptance on class-v6 542cd7028 against the same-crate windowed control (PASS: r 0.18 against 0.27 at width 4, the (c''') cost 2 against 13 percent, 0 hot sets and 0 over 1.2x at 2^20, the bit-R share up with the windows gone, the fold the lever); the harness port diff at 542cd7028	2026-10-08 17:54:46 +00:00
hardware-future.md	Class v6 research lane B: the hardware future, five years out (first cut and the full report in one file)	2026-10-08 10:17:50 +00:00
history.md	Class v6 history lane, first cut: every ASIC-resistant proof of work and its chips by mechanism, the four-layer mapping with a number per chip class, and the three lessons that bind on v6	2026-10-08 10:19:10 +00:00