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amd-proving.md
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docs/analysis/amd-proving.md: no zkVM proves on AMD (SP1, RISC Zero, Jolt, OpenVM, ICICLE cited), the SP1 CPU prover measured on PC 1 beside the miners (282 s a shard at any size, 30 GB RSS: no CPU tier), the tier consequences and the public line; PC 1 job scripts with the bash -n gate; bench-log entry
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2026-10-05 21:02:59 +00:00 |
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asic-resistance-history.md
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docs/analysis/asic-resistance-history.md: the 2011 to 2026 history of ASIC resistance (31 rows, chip, gain per joule, months held, response), the papers, the chip economics and the market-cap table, ten lessons, the audit of class v2 and the Counter ASIC 2.0 layers, seven ranked additions (partial-store chip row first), nine candidates placed nowhere
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2026-10-05 22:38:17 +00:00 |
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base-fee-floor.md
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Prover mirrors the fee switch: both tables and fees_v1_activation_daa in the shard input, guest re-pinned, devnet runbook for H = 210,000
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2026-10-05 16:24:35 +00:00 |
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card-lifetime-2026-10-05.md
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CI on the merged 0.3.11 tree: MacBook reworded in the analysis prose (the identity check's hostname pattern), a presence check before the kit's first use in the three proving-v1 PC 2 scripts (C32), pc1-cpu-prove.ps1 on the socket check's allow list (the CPU path starts no GPU server)
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2026-10-05 22:44:09 +00:00 |
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chip-model-v3.md
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verifier regression of e08909f fixed (derive_items out of line, one instance per cache size with the line mask a constant: v2 0.609 ms per unit against readwidth's 0.607, was 1.33); x8 into class v3 under the delegated rule (V3_CLASS = MX8; mx8-genesis and mx8-devnet-epoch0 re-exported through the seam, the devnet one with the era inside; the mx4 packs kept as the x4 record, generator 2); tests/packs.rs and tests/mixer.rs on the x8 class; mixer-x4.md 6.2a, 6.4a, 6.5 decision, 6.6 the regression; chip-model-v3.md headline x8 (0.92x with the factor); bench-log addendum with the PC 1 build rows
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2026-10-05 22:10:55 +00:00 |
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difficulty-2026-10-03.md
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Difficulty: timestamp attack fixed in spec 2.3, simulator, analysis addendum, ledger M23
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2026-10-04 00:56:20 +00:00 |
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difficulty-2026-10-04-oscillation.md
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Difficulty: the live oscillation of 4 October, its cause, the DAG replay and rule v2 (reference window 600 behind a height switch)
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2026-10-04 13:26:23 +00:00 |
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economy-2026-10-04.md
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Economy: agent-based mining-versus-proving simulation, six stress scenarios, lever study, analysis and bench entry
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2026-10-03 23:16:46 +00:00 |
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hashrate-decay-2026-10-03.md
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Hash-rate decay on the RTX 5090: diagnosis, Metal reproduction, proposed Seeder fix
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2026-10-03 23:31:23 +00:00 |
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hashrate-decay-2026-10-03.patch
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Hash-rate decay on the RTX 5090: diagnosis, Metal reproduction, proposed Seeder fix
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2026-10-03 23:31:23 +00:00 |
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int8-matrix-family.md
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Counter ASIC 2.0 layer 7: RTX 5090 and RX 9070 XT dot4 numbers from PC 1 (job run-dot4-20261005): dp4a 7.45 T/s on the 5090 via inline PTX, v_dot4_i32_iu8 0.66 T/s on the 9070 XT via the clang builtin in Adrenalin OpenCL C, signed emulation 7.1x / 1.46x / 4.7x the ALU step on NVIDIA / AMD / Apple; no PC platform lists cl_khr_integer_dot_product
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2026-10-05 20:31:33 +00:00 |
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m16-recompute-attacker-2026-10-05.md
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FUD sweep round 6 (evening, 5 October): eleven rolled-out fixes moved to Fixed with live measurement lines, F21/F22 shipped but switch not thrown, M20 closed on the 0.3.5 merge; P14 one base-fee definition in spec 05; M16 recompute-attacker cost model; C4 overlay-against-GHOSTDAG runner
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2026-10-05 16:02:02 +00:00 |
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prover-floor.md
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Prover floor: sweep 1 table and reading (the Setup-time keys bind at 12.7 GB)
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2026-10-05 22:42:17 +00:00 |
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proving-methods.md
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CI on the merged 0.3.11 tree: MacBook reworded in the analysis prose (the identity check's hostname pattern), a presence check before the kit's first use in the three proving-v1 PC 2 scripts (C32), pc1-cpu-prove.ps1 on the socket check's allow list (the CPU path starts no GPU server)
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2026-10-05 22:44:09 +00:00 |
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scratch-soundness.md
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ca2-soundness: docs/analysis/scratch-soundness.md alone (its code is already in the tree through the mixer merge; the branch merge conflicted there); release-0.3.11 plan: C37 and C38
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2026-10-05 23:04:38 +00:00 |
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security-budget.md
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Evidence page, end-to-end proving standard, funding plan, security-budget stress, payment routes
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2026-10-03 22:35:03 +00:00 |
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sram-mirror.md
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Counter ASIC 2.0 layer 6, revision 2: shipped cache-die density (AMD V-Cache 64 MB on 41 mm^2 at 7 nm, Hot Chips 33) as the headline column beside the bit-cell lower bound; mirror 106 to 164 mm^2 and $30 to $56 per die at 256 MiB; year 0 to 10, hot-table and option tables redone; latency citations section (MEMSYS 2018, Chang 2017, mining-chip memory types)
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2026-10-05 20:20:46 +00:00 |
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weak-program-census-2026-10-03.md
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Mac app: dial the public seed node first, the home node second
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2026-10-03 22:28:58 +00:00 |
