igneum-labs 2b7cafee15 Class v6 floor lane 4: floor lane 1's stock rows taken (the 4090 and H100; the occupancy knob 1 to 2 percent), the class v5 watts driver and the memory-clock try (box-cardbench-v2m.sh) on 16 card classes in parallel ... Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>		2026-10-08 12:22:22 +00:00
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floor	Class v6 floor lane 4: floor lane 1's stock rows taken (the 4090 and H100; the occupancy knob 1 to 2 percent), the class v5 watts driver and the memory-clock try (box-cardbench-v2m.sh) on 16 card classes in parallel	2026-10-08 12:22:22 +00:00
hardware-future.md	Class v6 research lane B: the hardware future, five years out (first cut and the full report in one file)	2026-10-08 10:17:50 +00:00
history.md	Class v6 history lane, first cut: every ASIC-resistant proof of work and its chips by mechanism, the four-layer mapping with a number per chip class, and the three lessons that bind on v6	2026-10-08 10:19:10 +00:00