279 lines
15 KiB
Common Lisp
279 lines
15 KiB
Common Lisp
// Generated by igneum-pow export (generator v2) for seed "igneum-epoch/edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07/day/69676e65756d2d6461792ffa50000000000000". Do not edit by hand.
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// OpenCL C twin of the Metal kernel for the same seed (see proto-opencl/README.md, WAVEFRONT.md and program.metal).
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// Built from source at runtime by proto-opencl/host.c, which passes these defines:
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// IGNEUM_GROUP work-group size of igneum_hash, a multiple of 32 (default 32: one work-group = one 32-lane unit)
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// IGNEUM_EXCHANGE 0 = local-memory exchange with a barrier (any device, any wave width; the default)
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// 1 = sub_group_shuffle_xor (cl_khr_subgroup_shuffle), only with IGNEUM_GROUP 32 and a sub-group size of exactly 32
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// 2 = intel_sub_group_shuffle_xor (cl_intel_subgroups), same condition
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// The verification unit is always 32 lanes. A 64-wide hardware wave (AMD GCN/CDNA, RDNA in wave64) runs two units;
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// the exchange masks are 1, 2, 4, 8, 16, so every partner lane lies inside the lane's own aligned run of 32.
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#ifndef IGNEUM_GROUP
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#define IGNEUM_GROUP 32
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#endif
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#ifndef IGNEUM_EXCHANGE
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#define IGNEUM_EXCHANGE 0
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#endif
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#ifdef __OPENCL_VERSION__
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#define IGNEUM_KERNEL_HASH __kernel __attribute__((reqd_work_group_size(IGNEUM_GROUP, 1, 1)))
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#define IGNEUM_LOCAL_WORDS(name, n) __local uint name[n]
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#if IGNEUM_EXCHANGE == 1
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#ifdef cl_khr_subgroups
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#pragma OPENCL EXTENSION cl_khr_subgroups : enable
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#endif
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#ifdef cl_khr_subgroup_shuffle
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#pragma OPENCL EXTENSION cl_khr_subgroup_shuffle : enable
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#endif
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#elif IGNEUM_EXCHANGE == 2
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#pragma OPENCL EXTENSION cl_intel_subgroups : enable
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#endif
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#else
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// Not an OpenCL compiler: proto-opencl/emu compiles this file as C++ and supplies the built-ins and these two macros.
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#include "emu_opencl.h"
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#endif
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#if IGNEUM_EXCHANGE == 1
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#define IGNEUM_SHFL_XOR(dst, a, m) dst = sub_group_shuffle_xor((a), (uint)(m))
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#define IGNEUM_BCAST0(dst, a) dst = sub_group_broadcast((a), 0u)
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#elif IGNEUM_EXCHANGE == 2
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#define IGNEUM_SHFL_XOR(dst, a, m) dst = intel_sub_group_shuffle_xor((a), (uint)(m))
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#define IGNEUM_BCAST0(dst, a) dst = sub_group_broadcast((a), 0u)
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#else
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// Local-memory exchange. Two buffers of IGNEUM_GROUP words alternate (xk counts exchanges), so one barrier per
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// exchange is enough: a lane can only overwrite buffer b at exchange k+2 after passing barrier k+1, and every lane
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// reaches barrier k+1 only after its read of buffer b at exchange k. The partner lid ^ m stays inside the lane's
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// aligned run of 32 because m < 32. Control flow is uniform, so every work-item reaches every barrier.
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#define IGNEUM_SHFL_XOR(dst, a, m) { xch[(xk & 1u) * IGNEUM_GROUP + lid] = (a); barrier(CLK_LOCAL_MEM_FENCE); dst = xch[(xk & 1u) * IGNEUM_GROUP + (lid ^ (uint)(m))]; xk += 1u; }
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#define IGNEUM_BCAST0(dst, a) { xch[(xk & 1u) * IGNEUM_GROUP + lid] = (a); barrier(CLK_LOCAL_MEM_FENCE); dst = xch[(xk & 1u) * IGNEUM_GROUP + (lid & ~31u)]; xk += 1u; }
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#endif
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static inline uint splitmix32(uint x) {
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x ^= x >> 16; x *= 0x7feb352du;
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x ^= x >> 15; x *= 0x846ca68bu;
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x ^= x >> 16;
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return x;
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}
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// n is a literal in 1..31 at every call site. OpenCL rotate() rotates left by n modulo 32.
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static inline uint rotl_imm(uint x, uint n) { return rotate(x, n); }
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// Right rotation by n modulo 32 as a left rotation by (32 - n) modulo 32; n == 0 gives x.
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static inline uint rotr_var(uint x, uint n) { return rotate(x, (0u - n) & 31u); }
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static inline uint ds_elem(uint i, uint d0, uint d1) {
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uint x = i ^ d0;
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x *= 0x9E3779B1u; x ^= x >> 15;
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x += d1;
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x *= 0x85EBCA77u; x ^= x >> 13;
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x *= 0xC2B2AE3Du; x ^= x >> 16;
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return x;
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}
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// Memory-hard dataset core (MEMHARD.md). Cache: 2^26 words in 2^16 segments of 64 chained ChaCha12 lines.
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// Item: 8 rounds of 8 x seed-parameterised mixer + one 64-byte cache read, then 8 x final mixer (class v3, mixer multiplier 8,
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// docs/plans/mixer-x4.md: the round key of application j of round r is 0x9E3779B9 * (r * m + j + 1)). All parameters are literals.
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#define MH_CACHE_LINE_MASK 0x003fffffu
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#define MH_SEGMENT_LINES 64u
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#define MH_QR(a, b, c, d, r1, r2, r3, r4) { a += b; d ^= a; d = mh_rotl(d, r1); c += d; b ^= c; b = mh_rotl(b, r2); a += b; d ^= a; d = mh_rotl(d, r3); c += d; b ^= c; b = mh_rotl(b, r4); }
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static inline uint mh_rotl(uint x, uint n) { return (x << n) | (x >> (32u - n)); } // n in 1..31 at every call site
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// y = ChaCha12 core(x) + x
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static inline void mh_chacha_block(const uint* x, uint* y) {
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for (uint i = 0u; i < 16u; ++i) y[i] = x[i];
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for (uint r = 0u; r < 6u; ++r) {
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MH_QR(y[0], y[4], y[8], y[12], 16u, 12u, 8u, 7u) MH_QR(y[1], y[5], y[9], y[13], 16u, 12u, 8u, 7u)
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MH_QR(y[2], y[6], y[10], y[14], 16u, 12u, 8u, 7u) MH_QR(y[3], y[7], y[11], y[15], 16u, 12u, 8u, 7u)
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MH_QR(y[0], y[5], y[10], y[15], 16u, 12u, 8u, 7u) MH_QR(y[1], y[6], y[11], y[12], 16u, 12u, 8u, 7u)
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MH_QR(y[2], y[7], y[8], y[13], 16u, 12u, 8u, 7u) MH_QR(y[3], y[4], y[9], y[14], 16u, 12u, 8u, 7u)
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}
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for (uint i = 0u; i < 16u; ++i) y[i] += x[i];
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}
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// One cache segment: 64 chained lines written at cache[seg * 1024]. in_j = prev ^ (sigma || K || seg || j || tag), prev_0 = 0.
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static inline void mh_cache_segment(__global uint* cache, uint seg) {
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uint prev[16]; uint x[16]; uint y[16];
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for (uint i = 0u; i < 16u; ++i) prev[i] = 0u;
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for (uint j = 0u; j < MH_SEGMENT_LINES; ++j) {
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x[0] = 0x61707865u ^ prev[0]; x[1] = 0x3320646eu ^ prev[1]; x[2] = 0x79622d32u ^ prev[2]; x[3] = 0x6b206574u ^ prev[3];
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x[4] = 0xceed56d7u ^ prev[4];
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x[5] = 0x9ba270d2u ^ prev[5];
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x[6] = 0x82caab2du ^ prev[6];
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x[7] = 0x81ebce0eu ^ prev[7];
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x[8] = 0x12b6ecf1u ^ prev[8];
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x[9] = 0xd0f3fd7cu ^ prev[9];
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x[10] = 0xd872eefeu ^ prev[10];
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x[11] = 0xc158c7bdu ^ prev[11];
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x[12] = seg ^ prev[12]; x[13] = j ^ prev[13]; x[14] = 0x49676e65u ^ prev[14]; x[15] = 0x756d4d48u ^ prev[15];
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mh_chacha_block(x, y);
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__global uint* line = cache + ((seg * MH_SEGMENT_LINES + j) * 16u);
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for (uint i = 0u; i < 16u; ++i) { line[i] = y[i]; prev[i] = y[i]; }
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}
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}
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// M_r: per word (s ^ (RC + rk)) * MUL, then a column round and a diagonal round with the seed-drawn rotations.
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static inline void mh_mixer(uint* s, uint rk) {
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s[0] = (s[0] ^ (0xc6892460u + rk)) * 0xf351d601u;
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s[1] = (s[1] ^ (0x25b7228au + rk)) * 0xa3bb398fu;
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s[2] = (s[2] ^ (0xcd515004u + rk)) * 0xb5a09e35u;
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s[3] = (s[3] ^ (0x2846527au + rk)) * 0x7509c9c1u;
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s[4] = (s[4] ^ (0xa6324241u + rk)) * 0x6bbf31e9u;
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s[5] = (s[5] ^ (0x36e3ec53u + rk)) * 0xfc849a79u;
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s[6] = (s[6] ^ (0x82961bacu + rk)) * 0xded91851u;
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s[7] = (s[7] ^ (0x0f97ba7du + rk)) * 0x8d9113d1u;
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s[8] = (s[8] ^ (0xb6f921a9u + rk)) * 0x0ff15225u;
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s[9] = (s[9] ^ (0x3ada24e5u + rk)) * 0x3a5bdd41u;
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s[10] = (s[10] ^ (0xde20ab91u + rk)) * 0xab533435u;
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s[11] = (s[11] ^ (0x5378eeb2u + rk)) * 0xe1c55ad5u;
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s[12] = (s[12] ^ (0x7d161662u + rk)) * 0xe6d3bd0du;
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s[13] = (s[13] ^ (0x89353cc1u + rk)) * 0x9d9ffbbdu;
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s[14] = (s[14] ^ (0xb1aa03a2u + rk)) * 0xbb2a3cf3u;
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s[15] = (s[15] ^ (0x788acae6u + rk)) * 0x50a7c08du;
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MH_QR(s[0], s[4], s[8], s[12], 17u, 12u, 20u, 23u) MH_QR(s[1], s[5], s[9], s[13], 17u, 12u, 20u, 23u)
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MH_QR(s[2], s[6], s[10], s[14], 17u, 12u, 20u, 23u) MH_QR(s[3], s[7], s[11], s[15], 17u, 12u, 20u, 23u)
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MH_QR(s[0], s[5], s[10], s[15], 7u, 3u, 27u, 16u) MH_QR(s[1], s[6], s[11], s[12], 7u, 3u, 27u, 16u)
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MH_QR(s[2], s[7], s[8], s[13], 7u, 3u, 27u, 16u) MH_QR(s[3], s[4], s[9], s[14], 7u, 3u, 27u, 16u)
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}
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// Item t: 16 words. s = (K, t * MUL[i] + RC[i]); 8 rounds of 8 x mixer + cache line s[0] & mask; 8 x final mixer.
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static inline void mh_item(__global const uint* cache, uint t, uint* s) {
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s[0] = 0xceed56d7u;
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s[1] = 0x9ba270d2u;
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s[2] = 0x82caab2du;
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s[3] = 0x81ebce0eu;
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s[4] = 0x12b6ecf1u;
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s[5] = 0xd0f3fd7cu;
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s[6] = 0xd872eefeu;
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s[7] = 0xc158c7bdu;
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s[8] = t * 0xf351d601u + 0xc6892460u;
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s[9] = t * 0xa3bb398fu + 0x25b7228au;
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s[10] = t * 0xb5a09e35u + 0xcd515004u;
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s[11] = t * 0x7509c9c1u + 0x2846527au;
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s[12] = t * 0x6bbf31e9u + 0xa6324241u;
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s[13] = t * 0xfc849a79u + 0x36e3ec53u;
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s[14] = t * 0xded91851u + 0x82961bacu;
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s[15] = t * 0x8d9113d1u + 0x0f97ba7du;
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for (uint r = 0u; r < 8u; ++r) {
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for (uint j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (r * 8u + j + 1u));
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__global const uint* line = cache + ((s[0] & MH_CACHE_LINE_MASK) * 16u);
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for (uint i = 0u; i < 16u; ++i) s[i] ^= line[i];
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}
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for (uint j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (64u + j + 1u));
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}
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// dataset[w] without the dataset: derive item w >> 4 and take word w & 15.
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static inline uint mh_word(__global const uint* cache, uint w) { uint s[16]; mh_item(cache, w >> 4u, s); return s[w & 15u]; }
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// Memory-hard dataset (MEMHARD.md). One work-item per cache segment; one work-item per 64-byte dataset item.
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// The same constants as memhard.h in this pack (one emitter, three dialects).
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__kernel void igneum_cache_fill(__global uint* cache, uint nSegments) {
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uint seg = (uint)get_global_id(0);
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if (seg < nSegments) mh_cache_segment(cache, seg);
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}
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__kernel void igneum_build(__global uint* ds, __global const uint* cache, uint nItems) {
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uint t = (uint)get_global_id(0);
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if (t < nItems) {
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uint s[16];
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mh_item(cache, t, s);
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__global uint* d = ds + ((ulong)t * 16u);
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for (uint i = 0u; i < 16u; ++i) d[i] = s[i];
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}
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}
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// One hash per work-item. IGNEUM_GROUP is a multiple of 32; lane = lid & 31 and every exchange stays inside the
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// lane's own aligned run of 32 work-items, exactly like simd_shuffle_xor inside a 32-wide Metal SIMD group and
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// __shfl_xor_sync inside a CUDA warp. Control flow is uniform (no branches at all).
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IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out, uint baseNonce, uint mask) {
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uint gid = (uint)get_global_id(0);
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uint lid = (uint)get_local_id(0);
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uint nonce = baseNonce + gid;
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uint r0, r1, r2, r3, r4, r5, r6, r7;
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#if IGNEUM_EXCHANGE == 0
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IGNEUM_LOCAL_WORDS(xch, 2 * IGNEUM_GROUP);
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uint xk = 0u;
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#else
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(void)lid;
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#endif
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{ uint x = nonce ^ 0x667d0fbdu; x += 0x9e3779b9u; x = splitmix32(x); r0 = x ^ 0x7b8e5963u; } // SEEDW[0], 0x9e3779b9u * 1u, SEEDW[1]
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{ uint x = nonce ^ 0x7b8e5963u; x += 0x3c6ef372u; x = splitmix32(x); r1 = x ^ 0x31c67e5eu; } // SEEDW[1], 0x9e3779b9u * 2u, SEEDW[2]
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{ uint x = nonce ^ 0x31c67e5eu; x += 0xdaa66d2bu; x = splitmix32(x); r2 = x ^ 0x4529ddc6u; } // SEEDW[2], 0x9e3779b9u * 3u, SEEDW[3]
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{ uint x = nonce ^ 0x4529ddc6u; x += 0x78dde6e4u; x = splitmix32(x); r3 = x ^ 0xef19d6d8u; } // SEEDW[3], 0x9e3779b9u * 4u, SEEDW[4]
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{ uint x = nonce ^ 0xef19d6d8u; x += 0x1715609du; x = splitmix32(x); r4 = x ^ 0xaccf6211u; } // SEEDW[4], 0x9e3779b9u * 5u, SEEDW[5]
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{ uint x = nonce ^ 0xaccf6211u; x += 0xb54cda56u; x = splitmix32(x); r5 = x ^ 0xda0aed32u; } // SEEDW[5], 0x9e3779b9u * 6u, SEEDW[6]
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{ uint x = nonce ^ 0xda0aed32u; x += 0x5384540fu; x = splitmix32(x); r6 = x ^ 0xabc6df31u; } // SEEDW[6], 0x9e3779b9u * 7u, SEEDW[7]
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{ uint x = nonce ^ 0xabc6df31u; x += 0xf1bbcdc8u; x = splitmix32(x); r7 = x ^ 0x667d0fbdu; } // SEEDW[7], 0x9e3779b9u * 8u, SEEDW[0]
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for (uint it = 0u; it < 8u; ++it) {
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uint sel = r0;
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r4 = r4 + r5 + ((((sel >> 13u) & 1u) != 0u) ? 0x5810667au : 0xea86e152u); // 0 add
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{ uint t_; IGNEUM_SHFL_XOR(t_, r0, 4u); r2 = r2 ^ t_; } // 1 shfl
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r3 = r3 + r2 + ((((sel >> 10u) & 1u) != 0u) ? 0x642e66dbu : 0x2cccb6cau); // 2 add
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r0 = rotl_imm(r0, 19u); // 3 rotl
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r7 = rotr_var(r7, r6); // 4 rotr
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r7 = r7 + r4 + ((((sel >> 21u) & 1u) != 0u) ? 0xc1535555u : 0xee02465fu); // 5 add
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r1 = mul_hi(r1, r7); // 6 mulhi
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r4 = r4 ^ ds[r2 & mask]; // 7 load
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r7 = r7 ^ ds[r4 & mask]; // 8 load
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r0 = r0 ^ ds[r3 & mask]; // 9 load
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r5 = r5 ^ ds[r1 & mask]; // 10 load
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r1 = r1 ^ ds[r5 & mask]; // 11 load
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r3 = mul_hi(r3, r5); // 12 mulhi
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r1 = r1 ^ ds[r3 & mask]; // 13 load
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r0 = r0 - r3; // 14 sub
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r5 = r1 * r3 + r5; // 15 mad
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r6 = mul_hi(r6, r1); // 16 mulhi
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r5 = r5 + r2 + ((((sel >> 28u) & 1u) != 0u) ? 0x8b965b57u : 0x697b3d00u); // 17 add
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r0 = mul_hi(r0, r6); // 18 mulhi
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r5 = rotr_var(r5, r3); // 19 rotr
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r5 = mul_hi(r5, r2); // 20 mulhi
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r1 = r1 + r0 + ((((sel >> 1u) & 1u) != 0u) ? 0x6d7e8d05u : 0xebcf247au); // 21 add
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r7 = r7 + r5 + ((((sel >> 12u) & 1u) != 0u) ? 0xb9e3577eu : 0xf66e7017u); // 22 add
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r1 = mul_hi(r1, r5); // 23 mulhi
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r2 = r2 - r5; // 24 sub
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r7 = r7 + r4 + ((((sel >> 2u) & 1u) != 0u) ? 0x699ef1bbu : 0x08ffa6c7u); // 25 add
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{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 2u); r3 = r3 ^ t_; } // 26 shfl
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r7 = r7 + r1 + ((((sel >> 14u) & 1u) != 0u) ? 0xb4ead2fbu : 0xe60fea84u); // 27 add
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r3 = r3 + r1 + ((((sel >> 6u) & 1u) != 0u) ? 0x8f30d21du : 0x65c76dabu); // 28 add
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r2 = r2 ^ ds[r1 & mask]; // 29 load
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r5 = r5 ^ ds[r7 & mask]; // 30 load
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r2 = r2 ^ ds[r5 & mask]; // 31 load
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{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 4u); r1 = r1 ^ t_; } // 32 shfl
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r4 = r5 * r7 + r4; // 33 mad
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r4 = r4 + r2 + ((((sel >> 21u) & 1u) != 0u) ? 0xc7ce690cu : 0x0480debeu); // 34 add
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{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 8u); r3 = r3 ^ t_; } // 35 shfl
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r7 = r7 + r1 + ((((sel >> 2u) & 1u) != 0u) ? 0xe10c2c95u : 0xc53b542eu); // 36 add
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r5 = r5 ^ r7; // 37 xor
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r2 = r2 | r1; // 38 or
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r1 = mul_hi(r1, r0); // 39 mulhi
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r6 = rotl_imm(r6, 19u); // 40 rotl
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r4 = mul_hi(r4, r6); // 41 mulhi
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r6 = r6 - r0; // 42 sub
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{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r6 = r6 ^ t_; } // 43 shfl
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r4 = r4 ^ ds[r2 & mask]; // 44 load
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r1 = r1 ^ r3; // 45 xor
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r7 = r7 ^ ds[r0 & mask]; // 46 load
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r3 = r3 ^ ds[r1 & mask]; // 47 load
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r5 = r5 * r3; // 48 mul
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r1 = r1 - r5; // 49 sub
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r2 = rotl_imm(r2, 8u); // 50 rotl
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r1 = r1 + r5 + ((((sel >> 23u) & 1u) != 0u) ? 0x77b9bd43u : 0xa900fec4u); // 51 add
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r4 = r4 ^ ds[r7 & mask]; // 52 load
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r2 = r2 - r7; // 53 sub
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r4 = r4 ^ r0; // 54 xor
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r1 = r1 + r6 + ((((sel >> 14u) & 1u) != 0u) ? 0x83e825bfu : 0xe09f54e9u); // 55 add
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r2 = r2 ^ ds[r4 & mask]; // 56 load
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r0 = r1 * r4 + r0; // 57 mad
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r3 = r3 ^ ds[r5 & mask]; // 58 load
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r5 = r5 | r6; // 59 or
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r6 = r5 * r7 + r6; // 60 mad
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r4 = rotl_imm(r4, 28u); // 61 rotl
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r5 = mul_hi(r5, r0); // 62 mulhi
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r3 = r3 ^ ds[r6 & mask]; // 63 load
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|
}
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uint lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u);
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|
uint hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u);
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|
out[gid] = ((ulong)hi << 32) | (ulong)lo;
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|
}
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|
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#if IGNEUM_EXCHANGE != 0
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// Reports the sub-group size this device uses for a work-group of IGNEUM_GROUP items. host.c runs it only when the
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|
// per-kernel query (clGetKernelSubGroupInfoKHR on igneum_hash) is unavailable; that query is preferred because a
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|
// compiler may pick a different wave width per kernel (RDNA: wave32 or wave64). See WAVEFRONT.md.
|
|
IGNEUM_KERNEL_HASH void igneum_probe_subgroup(__global uint* out) {
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|
if (get_local_id(0) == 0u) { out[0] = get_sub_group_size(); out[1] = get_num_sub_groups(); }
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}
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|
#endif
|