igneum-labs 0dc59c302e shadow-k: the window's measured GPU side (no spill, 83 and 67 percent occupancy, at most 5 percent per load); the time-multiplexed core, the connected-state draw, the simplified FP32 units and the pod mode ... Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com> Documents-only replay of 26844fde7 (86e5b0fb24) for the box mirror master		2026-10-08 20:42:28 +00:00
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denominator.md	Class v6 floor lane 4: the RX 7600 (8 GB) measured on PC 1 (13.88 MH/s at 113 W, 8.14 microjoules, the card-in job 15:50 UK) added to the tiers table and the AMD estimates re-based on it; 10 of 10 on build-3	2026-10-08 15:04:38 +00:00
invention.md	Class v6 floor lane 5 (invention): the knee row from PC 1 (the hash lane, kit d): at the 1,300 lock the hinted w64 form reads 37.6 against the 4-byte row's 100.6 MH/s at 2.3x the energy per hash, so W = 16 is dead at the knee as at stock; every row this lane owed on W = 16 is closed	2026-10-08 14:05:41 +00:00
shadow-k.md	shadow-k: the window's measured GPU side (no spill, 83 and 67 percent occupancy, at most 5 percent per load); the time-multiplexed core, the connected-state draw, the simplified FP32 units and the pod mode	2026-10-08 20:42:28 +00:00
sm-sparse.md	Class v6 floor lane 1: sm-sparse.md amendment, the memory-clock ladder on PC 1 at the 1,300 lock (the 5090's PHY has two states, 13,801 and 7,001 MHz; the half-rate state loses 43 percent of rate for 37 percent of watts, energy per hash up 12 percent on class v3 and 5 on class v4: the memory clock is not a lever; the memory path read as 11 nJ per read at the margin, equal to the DRAM chase probes)	2026-10-08 14:49:41 +00:00
sram-and-floor.md	Class v6: the genesis dataset size DECIDED at 4 GiB (the founder's word at 20:00 UK, FROZEN as class_v6_dataset_steps [(0, 4096 MiB)]); change (3) and the served policy sentence as decided; the chip line's a-node-ahead end 3.3x with the floor marked	2026-10-08 19:31:58 +00:00