igneum-labs 08010e76a4 Class v6 family gate, 6.9 closed: the best-mix table's exact or = 0 attempts rows at both widths on build-4 (r 0.29 and 0.16, 0 exhausted, the floors at the width's cost), the owed line closed; the harness ported onto class-v6 a7c2c082f for the layer-8-off acceptance ... Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>		2026-10-08 17:20:45 +00:00
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logs	Class v6 family gate, 6.9 closed: the best-mix table's exact or = 0 attempts rows at both widths on build-4 (r 0.29 and 0.16, 0 exhausted, the floors at the width's cost), the owed line closed; the harness ported onto class-v6 a7c2c082f for the layer-8-off acceptance	2026-10-08 17:20:45 +00:00
family-gate.md	Class v6 family gate, 6.9 closed: the best-mix table's exact or = 0 attempts rows at both widths on build-4 (r 0.29 and 0.16, 0 exhausted, the floors at the width's cost), the owed line closed; the harness ported onto class-v6 a7c2c082f for the layer-8-off acceptance	2026-10-08 17:20:45 +00:00
hardware-future.md	Class v6 research lane B: the hardware future, five years out (first cut and the full report in one file)	2026-10-08 10:17:50 +00:00
history.md	Class v6 history lane, first cut: every ASIC-resistant proof of work and its chips by mechanism, the four-layer mapping with a number per chip class, and the three lessons that bind on v6	2026-10-08 10:19:10 +00:00