igneum/proto-cuda/packs-readwidth/mixB-5/program.json
igneum-labs 771e89abce read-width experiment (gate 1): load classes W=4/16/64, per-load width mix, scratch RMW variant behind a generator flag; 20 packs; CPU verifier and acceptance mirror; emulator shims
Nothing changes for the default class: the pinned packs are byte-identical (tests/packs.rs), the v2 draw stream is untouched.
LoadClass {mix, load_slots, scratch}: fixed widths w16, w64, w64x4 (4 loads of 64 B), era mixes 50/35/15 and 25/50/25 drawn per load with one extra below(100) roll, and the scratch variant scr0/2/4/8 (persistent warps, 1 MiB per warp, tagged lazy fill, measurement only). A wide load reads the W-aligned address and folds every word: x = dst ^ w0; x = (rotl(x, 11) * 0x9e3779b1) ^ w[j]. Program ids carry the class. proto-opencl/host.c taken from opencl-rdna4 5034e81 (--memprobe, select read-back).

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 19:46:54 +00:00

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JSON

{
"format": "igneum-program-pack-3",
"generator": 2,
"attempt": 0,
"program_id": "0x6a607f9221afe5da",
"program_id_derivation": "FNV-1a 64 over 'igneum-program/' || generator_le32 || seed_words as little-endian bytes || attempt_le32",
"dataset_mode": "memory-hard",
"seed": "igneum-readwidth/B/5",
"seed_bytes": "69676e65756d2d7265616477696474682f422f35",
"seed_words": ["0xd572f9e9", "0x30b20f21", "0x91d2d3fc", "0x9395a5a1", "0xef3dcd1f", "0x8c9e416e", "0x47c6146e", "0x360af18a"],
"seed_derivation": "seed_words = FNV-1a 64 over seed_bytes (attempt 0) or seed_bytes || attempt_le32 (attempt k >= 1), basis ^ (salt * 0x9E3779B97F4A7C15) for salt 0..3, then h ^= h>>33; h *= 0xff51afd7ed558ccd; h ^= h>>33; words[2*salt] = low 32, words[2*salt+1] = high 32",
"generator_rule": "version 2: exactly 16 load slots drawn first from instructions 1..63 (partial Fisher-Yates), the other 48 ops from the ten non-load weights (sum 75); a load's source is drawn from the registers other than dst written by an earlier instruction and not read by a load since; the candidate must pass the acceptance rule of spec 01 section 1.4.6 (static: no cyclically stale load source, every register has an injecting write; dynamic: 64 units on the seed-keyed closed-form dataset with no constant register bit, no lane-constant load site, under 164 saturated final values, every output bit within 136 of 1024, distinct addresses above 245760), else the next attempt of the seed is tried",
"lanes": 32,
"registers": 8,
"iterations": 8,
"instruction_count": 64,
"loads_per_hash": 128,
"load_class": "mix25-50-25",
"load_slots": 16,
"load_mix_percent_4_16_64": [25, 50, 25],
"load_width_counts_4_16_64": [1, 11, 4],
"bytes_per_hash": 3488,
"wide_load": "read-width experiment (5 October 2026, docs/plans/read-width.md), NOT the lottery hash: a load of W words (width field, 4 or 16) reads dataset[b .. b + W) with b = (src & mask) & ~(W - 1) and folds every word into dst: x = dst ^ w[0]; for j in 1..W: x = (rotl(x, 11) * 0x9e3779b1) ^ w[j]; dst = x; width 1 is the plain load; the width is drawn per instruction from the class mix with one extra below(100) draw after the nine of version 2, and the program id is FNV-1a 64 over 'igneum-program-rw/' || generator_le32 || seed words || attempt_le32 || mix[3] || load_slots",
"op_mix": {"load": 16, "shfl": 9, "add": 6, "mul": 6, "mad": 5, "sub": 5, "xor": 5, "or": 4, "rotl": 4, "rotr": 3, "mulhi": 1},
"register_init": "for i in 0..7: x = nonce ^ seed_words[i]; x += 0x9e3779b9 * (i+1) (mod 2^32); x = splitmix32(x); r[i] = x ^ seed_words[(i+1) & 7]",
"splitmix32": "x ^= x>>16; x *= 0x7feb352d; x ^= x>>15; x *= 0x846ca68b; x ^= x>>16",
"iteration": "sel = r0 sampled once at the top of each iteration, then all instructions in order",
"output": "lo = r0 ^ rotl(r1,7) ^ rotl(r2,14) ^ rotl(r3,21); hi = r4 ^ rotl(r5,9) ^ rotl(r6,18) ^ rotl(r7,27); out = (hi << 32) | lo",
"op_semantics": {
"add": "dst = dst + src + (bit `bit` of sel ? imm2 : imm)",
"sub": "dst = dst - src",
"mul": "dst = dst * src (low 32)",
"mulhi": "dst = high 32 bits of dst * src",
"xor": "dst = dst ^ src",
"or": "dst = dst | src",
"rotl": "dst = rotl(dst, rot), rot in 1..31",
"rotr": "dst = rotr(dst, src & 31)",
"mad": "dst = src * src2 + dst",
"shfl": "dst = dst ^ (src of lane (lane ^ mask)), mask in {1,2,4,8,16}, within the 32-lane warp",
"load": "dst = dst ^ dataset[src & dataset.mask]",
"wload": "base = (src of lane 0 & dataset.mask) & ~31; dst = dst ^ dataset[base + lane] (warp-coalesced 128-byte load, lever b, only when --wide-frac > 0)"
},
"dataset": {
"log2_words": 28,
"bytes": 1073741824,
"mask": "0x0fffffff",
"day": "2026-10-03",
"day_bytes": "6461792f323032362d31302d3033",
"day_words_from": "seed_words_from_bytes(day_bytes)",
"d0": "0x3067619f",
"d1": "0x3c269176",
"mode": "memory-hard",
"spec": "proto-metal/MEMHARD.md",
"key": ["0x3067619f", "0x3c269176", "0x84a03b03", "0xf8c63294", "0xff977c5b", "0xe60def3e", "0x63630141", "0xb8fbcb58"],
"key_derivation": "the 8 words of seed_words_from_bytes(day_bytes); d0, d1 are key[0], key[1]",
"cache": {"log2_words": 26, "bytes": 268435456, "line_words": 16, "segment_lines": 64, "segments": 65536, "block": "ChaCha12 core + feed-forward, rotations 16 12 8 7", "sigma": ["0x61707865", "0x3320646e", "0x79622d32", "0x6b206574"], "tag": ["0x49676e65", "0x756d4d48"], "chain": "in_j = prev_line ^ (sigma[0..3] || key[0..7] || seg || j || tag[0..1]); line_j = block(in_j); prev_0 = 0"},
"mixer": {"draw": "SplitMix64 seeded with key[0] | key[1] << 32: rot[0..7] = 1 + next() % 31, mul[0..15] = low32(next()) | 1, rc[0..15] = low32(next())", "rot": [20, 20, 19, 4, 26, 3, 3, 27], "mul": ["0x42146205", "0x52cbe0fb", "0x7ecf4a03", "0x6728907f", "0xd81d9751", "0x132952c3", "0xf60de277", "0x05358035", "0xbaf6499d", "0xe4db9667", "0x3e98f45d", "0xd0004edd", "0x2691630d", "0x9beb3bcf", "0xab310379", "0x99cfb423"], "rc": ["0xbab68293", "0xcc162340", "0x6ce151cc", "0xe62b8997", "0xc9c80297", "0xf74a1654", "0x3d704af5", "0x3cf522b7", "0x2b9cac04", "0xa880ac10", "0x13e5dd1d", "0x6fc3e233", "0x2d83eeac", "0x9006e8bf", "0x2c4b5362", "0x31b49ee2"], "round": "for i in 0..15: s[i] = (s[i] ^ (rc[i] + (r+1) * 0x9E3779B9)) * mul[i]; then quarter rounds on columns (0,4,8,12) (1,5,9,13) (2,6,10,14) (3,7,11,15) with rot[0..3] and diagonals (0,5,10,15) (1,6,11,12) (2,7,8,13) (3,4,9,14) with rot[4..7]", "quarter_round": "a += b; d ^= a; d = rotl(d, r1); c += d; b ^= c; b = rotl(b, r2); a += b; d ^= a; d = rotl(d, r3); c += d; b ^= c; b = rotl(b, r4)"},
"item": "s[0..7] = key; s[8+i] = t * mul[i] + rc[i] for i in 0..7; for r in 0..7: s = M_r(s); line = s[0] & 0x003fffff; s[i] ^= cache[line * 16 + i]; then s = M_8(s); item(t) = s",
"word": "dataset[w] = item(w >> 4)[w & 15]"
},
"instructions": [
{"i": 0, "op": "mul", "dst": 3, "src": 1, "src2": 5, "imm": "0x8d99879f", "imm2": "0xa0b4a6c1", "rot": 7, "bit": 29, "mask": 16, "width": 1},
{"i": 1, "op": "shfl", "dst": 2, "src": 4, "src2": 0, "imm": "0x6eb233b5", "imm2": "0xa60c7aee", "rot": 2, "bit": 18, "mask": 4, "width": 1},
{"i": 2, "op": "xor", "dst": 0, "src": 6, "src2": 6, "imm": "0x08bb9aa0", "imm2": "0xc3c30d7b", "rot": 12, "bit": 13, "mask": 16, "width": 1},
{"i": 3, "op": "load", "dst": 4, "src": 3, "src2": 2, "imm": "0x65cf244b", "imm2": "0xc8e345dd", "rot": 13, "bit": 14, "mask": 1, "width": 16},
{"i": 4, "op": "load", "dst": 6, "src": 0, "src2": 6, "imm": "0xbd2e02d9", "imm2": "0x12c4bffd", "rot": 8, "bit": 20, "mask": 8, "width": 1},
{"i": 5, "op": "shfl", "dst": 2, "src": 0, "src2": 3, "imm": "0x45017107", "imm2": "0xe7972d4b", "rot": 11, "bit": 26, "mask": 2, "width": 1},
{"i": 6, "op": "shfl", "dst": 7, "src": 6, "src2": 3, "imm": "0x6fee330f", "imm2": "0x63572bf7", "rot": 30, "bit": 28, "mask": 4, "width": 1},
{"i": 7, "op": "rotl", "dst": 5, "src": 2, "src2": 3, "imm": "0x655cf6dd", "imm2": "0x9f4cbce8", "rot": 8, "bit": 30, "mask": 1, "width": 1},
{"i": 8, "op": "mad", "dst": 1, "src": 5, "src2": 7, "imm": "0xc2d75c8a", "imm2": "0x5dda61cd", "rot": 6, "bit": 14, "mask": 16, "width": 1},
{"i": 9, "op": "mul", "dst": 0, "src": 3, "src2": 5, "imm": "0xd185bb8e", "imm2": "0x19fef814", "rot": 4, "bit": 7, "mask": 2, "width": 1},
{"i": 10, "op": "mul", "dst": 0, "src": 4, "src2": 3, "imm": "0xc448790d", "imm2": "0x5eccbec1", "rot": 17, "bit": 5, "mask": 16, "width": 1},
{"i": 11, "op": "shfl", "dst": 3, "src": 0, "src2": 5, "imm": "0x2124d54a", "imm2": "0xb61e62fc", "rot": 16, "bit": 17, "mask": 16, "width": 1},
{"i": 12, "op": "load", "dst": 4, "src": 5, "src2": 4, "imm": "0x1210ee04", "imm2": "0x6c0239db", "rot": 16, "bit": 18, "mask": 8, "width": 4},
{"i": 13, "op": "shfl", "dst": 0, "src": 2, "src2": 2, "imm": "0x8a4ec78b", "imm2": "0x9fff9bdd", "rot": 19, "bit": 0, "mask": 16, "width": 1},
{"i": 14, "op": "sub", "dst": 4, "src": 6, "src2": 0, "imm": "0x1efbdf5f", "imm2": "0x2b3fbc72", "rot": 24, "bit": 31, "mask": 16, "width": 1},
{"i": 15, "op": "or", "dst": 7, "src": 5, "src2": 5, "imm": "0x7c272d45", "imm2": "0xcb7860aa", "rot": 20, "bit": 13, "mask": 2, "width": 1},
{"i": 16, "op": "rotr", "dst": 0, "src": 6, "src2": 3, "imm": "0x133400bd", "imm2": "0x5b4307e2", "rot": 15, "bit": 30, "mask": 2, "width": 1},
{"i": 17, "op": "sub", "dst": 1, "src": 7, "src2": 6, "imm": "0x60b98288", "imm2": "0x7266fa37", "rot": 5, "bit": 8, "mask": 2, "width": 1},
{"i": 18, "op": "sub", "dst": 3, "src": 6, "src2": 2, "imm": "0x81238503", "imm2": "0xada4d549", "rot": 8, "bit": 10, "mask": 8, "width": 1},
{"i": 19, "op": "sub", "dst": 5, "src": 4, "src2": 3, "imm": "0x97d5351f", "imm2": "0x87da996e", "rot": 16, "bit": 0, "mask": 16, "width": 1},
{"i": 20, "op": "shfl", "dst": 3, "src": 5, "src2": 4, "imm": "0x61a9fb98", "imm2": "0x5d6413a9", "rot": 27, "bit": 2, "mask": 1, "width": 1},
{"i": 21, "op": "or", "dst": 1, "src": 2, "src2": 0, "imm": "0x76659fd4", "imm2": "0x1b52a4fd", "rot": 3, "bit": 7, "mask": 16, "width": 1},
{"i": 22, "op": "shfl", "dst": 1, "src": 0, "src2": 0, "imm": "0x7072d886", "imm2": "0x31c1c1e4", "rot": 5, "bit": 17, "mask": 4, "width": 1},
{"i": 23, "op": "rotr", "dst": 5, "src": 3, "src2": 2, "imm": "0x4e913f3c", "imm2": "0x650bcb89", "rot": 4, "bit": 7, "mask": 4, "width": 1},
{"i": 24, "op": "load", "dst": 7, "src": 2, "src2": 2, "imm": "0xd693898d", "imm2": "0x4eafd5cf", "rot": 26, "bit": 15, "mask": 8, "width": 4},
{"i": 25, "op": "load", "dst": 1, "src": 0, "src2": 3, "imm": "0x78fc3704", "imm2": "0xf64c3a71", "rot": 12, "bit": 8, "mask": 8, "width": 4},
{"i": 26, "op": "or", "dst": 7, "src": 1, "src2": 3, "imm": "0xbea69d0d", "imm2": "0x6827d6f3", "rot": 13, "bit": 9, "mask": 2, "width": 1},
{"i": 27, "op": "load", "dst": 2, "src": 7, "src2": 1, "imm": "0xd0d39c63", "imm2": "0x4f108768", "rot": 10, "bit": 14, "mask": 4, "width": 4},
{"i": 28, "op": "xor", "dst": 3, "src": 4, "src2": 3, "imm": "0xe4e057c0", "imm2": "0x16f1be43", "rot": 24, "bit": 23, "mask": 1, "width": 1},
{"i": 29, "op": "load", "dst": 6, "src": 5, "src2": 5, "imm": "0xb89861c5", "imm2": "0x8e5ee7bd", "rot": 13, "bit": 6, "mask": 16, "width": 16},
{"i": 30, "op": "add", "dst": 5, "src": 4, "src2": 0, "imm": "0xd0651e01", "imm2": "0x90aaff78", "rot": 10, "bit": 15, "mask": 16, "width": 1},
{"i": 31, "op": "load", "dst": 1, "src": 3, "src2": 1, "imm": "0x966081ac", "imm2": "0x12902378", "rot": 18, "bit": 22, "mask": 16, "width": 16},
{"i": 32, "op": "mul", "dst": 0, "src": 4, "src2": 1, "imm": "0x8191bcaf", "imm2": "0x6e9c9179", "rot": 21, "bit": 18, "mask": 8, "width": 1},
{"i": 33, "op": "add", "dst": 0, "src": 3, "src2": 2, "imm": "0x8ac5ddc2", "imm2": "0x3d45d6cf", "rot": 15, "bit": 2, "mask": 1, "width": 1},
{"i": 34, "op": "load", "dst": 6, "src": 4, "src2": 5, "imm": "0xfe5e8e98", "imm2": "0x42f50042", "rot": 10, "bit": 8, "mask": 4, "width": 4},
{"i": 35, "op": "xor", "dst": 6, "src": 2, "src2": 0, "imm": "0x91c0ab45", "imm2": "0xd04ac64a", "rot": 17, "bit": 19, "mask": 1, "width": 1},
{"i": 36, "op": "xor", "dst": 1, "src": 6, "src2": 4, "imm": "0x33ee7c8a", "imm2": "0x95a5252f", "rot": 25, "bit": 4, "mask": 2, "width": 1},
{"i": 37, "op": "mad", "dst": 0, "src": 4, "src2": 3, "imm": "0xecf08fbc", "imm2": "0x410bb43e", "rot": 23, "bit": 4, "mask": 8, "width": 1},
{"i": 38, "op": "rotl", "dst": 7, "src": 1, "src2": 6, "imm": "0xce8d1fbd", "imm2": "0xa4eb0972", "rot": 17, "bit": 22, "mask": 16, "width": 1},
{"i": 39, "op": "add", "dst": 5, "src": 7, "src2": 6, "imm": "0x651ff080", "imm2": "0x4b7eb232", "rot": 13, "bit": 0, "mask": 2, "width": 1},
{"i": 40, "op": "load", "dst": 1, "src": 2, "src2": 0, "imm": "0x9b6de222", "imm2": "0xa65a3196", "rot": 19, "bit": 3, "mask": 8, "width": 4},
{"i": 41, "op": "mulhi", "dst": 6, "src": 1, "src2": 5, "imm": "0x2eb1b89c", "imm2": "0xcd51c7e9", "rot": 22, "bit": 28, "mask": 16, "width": 1},
{"i": 42, "op": "load", "dst": 1, "src": 6, "src2": 0, "imm": "0x34c83029", "imm2": "0xc7caa918", "rot": 23, "bit": 23, "mask": 2, "width": 16},
{"i": 43, "op": "load", "dst": 3, "src": 0, "src2": 7, "imm": "0x5fdcdab2", "imm2": "0x091f2301", "rot": 10, "bit": 18, "mask": 8, "width": 4},
{"i": 44, "op": "load", "dst": 6, "src": 7, "src2": 7, "imm": "0x12f2c079", "imm2": "0x9f9f8573", "rot": 11, "bit": 8, "mask": 1, "width": 4},
{"i": 45, "op": "mul", "dst": 3, "src": 2, "src2": 2, "imm": "0xca1cb045", "imm2": "0xbefca4ec", "rot": 5, "bit": 23, "mask": 8, "width": 1},
{"i": 46, "op": "shfl", "dst": 6, "src": 5, "src2": 6, "imm": "0x511f46fb", "imm2": "0x11028be8", "rot": 4, "bit": 25, "mask": 2, "width": 1},
{"i": 47, "op": "mad", "dst": 4, "src": 2, "src2": 3, "imm": "0xe1547c3a", "imm2": "0x6513ccb5", "rot": 5, "bit": 29, "mask": 8, "width": 1},
{"i": 48, "op": "add", "dst": 4, "src": 2, "src2": 5, "imm": "0x4f0330b4", "imm2": "0x97f34047", "rot": 26, "bit": 20, "mask": 16, "width": 1},
{"i": 49, "op": "xor", "dst": 6, "src": 3, "src2": 0, "imm": "0x8fa8489b", "imm2": "0xf72c5554", "rot": 6, "bit": 5, "mask": 16, "width": 1},
{"i": 50, "op": "add", "dst": 0, "src": 2, "src2": 3, "imm": "0x6e73a5d8", "imm2": "0xb24ddcb5", "rot": 19, "bit": 17, "mask": 4, "width": 1},
{"i": 51, "op": "rotl", "dst": 6, "src": 3, "src2": 6, "imm": "0x5a2a99f0", "imm2": "0xff22310a", "rot": 22, "bit": 19, "mask": 1, "width": 1},
{"i": 52, "op": "mul", "dst": 4, "src": 0, "src2": 4, "imm": "0x2f1f4fd7", "imm2": "0xb39caa61", "rot": 21, "bit": 8, "mask": 4, "width": 1},
{"i": 53, "op": "rotr", "dst": 6, "src": 3, "src2": 0, "imm": "0x11dec3cc", "imm2": "0xf2c4a139", "rot": 3, "bit": 10, "mask": 2, "width": 1},
{"i": 54, "op": "load", "dst": 0, "src": 6, "src2": 5, "imm": "0x31111698", "imm2": "0x3ccec9cd", "rot": 22, "bit": 9, "mask": 2, "width": 4},
{"i": 55, "op": "sub", "dst": 3, "src": 1, "src2": 0, "imm": "0x579deaba", "imm2": "0x71c63728", "rot": 25, "bit": 12, "mask": 16, "width": 1},
{"i": 56, "op": "shfl", "dst": 3, "src": 7, "src2": 6, "imm": "0xa537855c", "imm2": "0x93db1532", "rot": 2, "bit": 5, "mask": 1, "width": 1},
{"i": 57, "op": "or", "dst": 3, "src": 1, "src2": 4, "imm": "0x8ba9bc0c", "imm2": "0xfdda17c1", "rot": 29, "bit": 18, "mask": 8, "width": 1},
{"i": 58, "op": "mad", "dst": 4, "src": 7, "src2": 4, "imm": "0x872fe127", "imm2": "0x47a6166c", "rot": 10, "bit": 10, "mask": 1, "width": 1},
{"i": 59, "op": "load", "dst": 1, "src": 0, "src2": 7, "imm": "0x0089e437", "imm2": "0xcf6c172e", "rot": 14, "bit": 17, "mask": 1, "width": 4},
{"i": 60, "op": "mad", "dst": 4, "src": 6, "src2": 3, "imm": "0x9a9b124b", "imm2": "0x25a02ef4", "rot": 7, "bit": 19, "mask": 4, "width": 1},
{"i": 61, "op": "rotl", "dst": 2, "src": 6, "src2": 2, "imm": "0x0489abc1", "imm2": "0x13809620", "rot": 30, "bit": 4, "mask": 8, "width": 1},
{"i": 62, "op": "load", "dst": 2, "src": 1, "src2": 5, "imm": "0xb1f6105a", "imm2": "0xefbc6585", "rot": 8, "bit": 4, "mask": 4, "width": 4},
{"i": 63, "op": "add", "dst": 7, "src": 4, "src2": 5, "imm": "0x12a17f52", "imm2": "0x4bcca5ca", "rot": 23, "bit": 3, "mask": 1, "width": 1}
]
}