igneum/proto-cuda/packs-readwidth/mixB-1/program.json
igneum-labs dc84789e34 read-width experiment (gate 1): load classes W=4/16/64, per-load width mix, scratch RMW variant behind a generator flag; 20 packs; CPU verifier and acceptance mirror; emulator shims
Nothing changes for the default class: the pinned packs are byte-identical (tests/packs.rs), the v2 draw stream is untouched.
LoadClass {mix, load_slots, scratch}: fixed widths w16, w64, w64x4 (4 loads of 64 B), era mixes 50/35/15 and 25/50/25 drawn per load with one extra below(100) roll, and the scratch variant scr0/2/4/8 (persistent warps, 1 MiB per warp, tagged lazy fill, measurement only). A wide load reads the W-aligned address and folds every word: x = dst ^ w0; x = (rotl(x, 11) * 0x9e3779b1) ^ w[j]. Program ids carry the class. proto-opencl/host.c taken from opencl-rdna4 23810df (--memprobe, select read-back).

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-05 19:46:54 +00:00

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JSON

{
"format": "igneum-program-pack-3",
"generator": 2,
"attempt": 0,
"program_id": "0x695b119dcb76931b",
"program_id_derivation": "FNV-1a 64 over 'igneum-program/' || generator_le32 || seed_words as little-endian bytes || attempt_le32",
"dataset_mode": "memory-hard",
"seed": "igneum-readwidth/B/1",
"seed_bytes": "69676e65756d2d7265616477696474682f422f31",
"seed_words": ["0x3e345412", "0xfc2b3a0e", "0x7740353d", "0x2df159db", "0x50bc6eed", "0x2e61acb2", "0x3c800bff", "0xbaecd8c1"],
"seed_derivation": "seed_words = FNV-1a 64 over seed_bytes (attempt 0) or seed_bytes || attempt_le32 (attempt k >= 1), basis ^ (salt * 0x9E3779B97F4A7C15) for salt 0..3, then h ^= h>>33; h *= 0xff51afd7ed558ccd; h ^= h>>33; words[2*salt] = low 32, words[2*salt+1] = high 32",
"generator_rule": "version 2: exactly 16 load slots drawn first from instructions 1..63 (partial Fisher-Yates), the other 48 ops from the ten non-load weights (sum 75); a load's source is drawn from the registers other than dst written by an earlier instruction and not read by a load since; the candidate must pass the acceptance rule of spec 01 section 1.4.6 (static: no cyclically stale load source, every register has an injecting write; dynamic: 64 units on the seed-keyed closed-form dataset with no constant register bit, no lane-constant load site, under 164 saturated final values, every output bit within 136 of 1024, distinct addresses above 245760), else the next attempt of the seed is tried",
"lanes": 32,
"registers": 8,
"iterations": 8,
"instruction_count": 64,
"loads_per_hash": 128,
"load_class": "mix25-50-25",
"load_slots": 16,
"load_mix_percent_4_16_64": [25, 50, 25],
"load_width_counts_4_16_64": [6, 8, 2],
"bytes_per_hash": 2240,
"wide_load": "read-width experiment (5 October 2026, docs/plans/read-width.md), NOT the lottery hash: a load of W words (width field, 4 or 16) reads dataset[b .. b + W) with b = (src & mask) & ~(W - 1) and folds every word into dst: x = dst ^ w[0]; for j in 1..W: x = (rotl(x, 11) * 0x9e3779b1) ^ w[j]; dst = x; width 1 is the plain load; the width is drawn per instruction from the class mix with one extra below(100) draw after the nine of version 2, and the program id is FNV-1a 64 over 'igneum-program-rw/' || generator_le32 || seed words || attempt_le32 || mix[3] || load_slots",
"op_mix": {"load": 16, "add": 11, "rotr": 6, "mad": 5, "mul": 5, "rotl": 5, "xor": 5, "mulhi": 4, "shfl": 3, "or": 2, "sub": 2},
"register_init": "for i in 0..7: x = nonce ^ seed_words[i]; x += 0x9e3779b9 * (i+1) (mod 2^32); x = splitmix32(x); r[i] = x ^ seed_words[(i+1) & 7]",
"splitmix32": "x ^= x>>16; x *= 0x7feb352d; x ^= x>>15; x *= 0x846ca68b; x ^= x>>16",
"iteration": "sel = r0 sampled once at the top of each iteration, then all instructions in order",
"output": "lo = r0 ^ rotl(r1,7) ^ rotl(r2,14) ^ rotl(r3,21); hi = r4 ^ rotl(r5,9) ^ rotl(r6,18) ^ rotl(r7,27); out = (hi << 32) | lo",
"op_semantics": {
"add": "dst = dst + src + (bit `bit` of sel ? imm2 : imm)",
"sub": "dst = dst - src",
"mul": "dst = dst * src (low 32)",
"mulhi": "dst = high 32 bits of dst * src",
"xor": "dst = dst ^ src",
"or": "dst = dst | src",
"rotl": "dst = rotl(dst, rot), rot in 1..31",
"rotr": "dst = rotr(dst, src & 31)",
"mad": "dst = src * src2 + dst",
"shfl": "dst = dst ^ (src of lane (lane ^ mask)), mask in {1,2,4,8,16}, within the 32-lane warp",
"load": "dst = dst ^ dataset[src & dataset.mask]",
"wload": "base = (src of lane 0 & dataset.mask) & ~31; dst = dst ^ dataset[base + lane] (warp-coalesced 128-byte load, lever b, only when --wide-frac > 0)"
},
"dataset": {
"log2_words": 28,
"bytes": 1073741824,
"mask": "0x0fffffff",
"day": "2026-10-03",
"day_bytes": "6461792f323032362d31302d3033",
"day_words_from": "seed_words_from_bytes(day_bytes)",
"d0": "0x3067619f",
"d1": "0x3c269176",
"mode": "memory-hard",
"spec": "proto-metal/MEMHARD.md",
"key": ["0x3067619f", "0x3c269176", "0x84a03b03", "0xf8c63294", "0xff977c5b", "0xe60def3e", "0x63630141", "0xb8fbcb58"],
"key_derivation": "the 8 words of seed_words_from_bytes(day_bytes); d0, d1 are key[0], key[1]",
"cache": {"log2_words": 26, "bytes": 268435456, "line_words": 16, "segment_lines": 64, "segments": 65536, "block": "ChaCha12 core + feed-forward, rotations 16 12 8 7", "sigma": ["0x61707865", "0x3320646e", "0x79622d32", "0x6b206574"], "tag": ["0x49676e65", "0x756d4d48"], "chain": "in_j = prev_line ^ (sigma[0..3] || key[0..7] || seg || j || tag[0..1]); line_j = block(in_j); prev_0 = 0"},
"mixer": {"draw": "SplitMix64 seeded with key[0] | key[1] << 32: rot[0..7] = 1 + next() % 31, mul[0..15] = low32(next()) | 1, rc[0..15] = low32(next())", "rot": [20, 20, 19, 4, 26, 3, 3, 27], "mul": ["0x42146205", "0x52cbe0fb", "0x7ecf4a03", "0x6728907f", "0xd81d9751", "0x132952c3", "0xf60de277", "0x05358035", "0xbaf6499d", "0xe4db9667", "0x3e98f45d", "0xd0004edd", "0x2691630d", "0x9beb3bcf", "0xab310379", "0x99cfb423"], "rc": ["0xbab68293", "0xcc162340", "0x6ce151cc", "0xe62b8997", "0xc9c80297", "0xf74a1654", "0x3d704af5", "0x3cf522b7", "0x2b9cac04", "0xa880ac10", "0x13e5dd1d", "0x6fc3e233", "0x2d83eeac", "0x9006e8bf", "0x2c4b5362", "0x31b49ee2"], "round": "for i in 0..15: s[i] = (s[i] ^ (rc[i] + (r+1) * 0x9E3779B9)) * mul[i]; then quarter rounds on columns (0,4,8,12) (1,5,9,13) (2,6,10,14) (3,7,11,15) with rot[0..3] and diagonals (0,5,10,15) (1,6,11,12) (2,7,8,13) (3,4,9,14) with rot[4..7]", "quarter_round": "a += b; d ^= a; d = rotl(d, r1); c += d; b ^= c; b = rotl(b, r2); a += b; d ^= a; d = rotl(d, r3); c += d; b ^= c; b = rotl(b, r4)"},
"item": "s[0..7] = key; s[8+i] = t * mul[i] + rc[i] for i in 0..7; for r in 0..7: s = M_r(s); line = s[0] & 0x003fffff; s[i] ^= cache[line * 16 + i]; then s = M_8(s); item(t) = s",
"word": "dataset[w] = item(w >> 4)[w & 15]"
},
"instructions": [
{"i": 0, "op": "mad", "dst": 5, "src": 4, "src2": 0, "imm": "0x392cc69d", "imm2": "0xdff38f87", "rot": 18, "bit": 19, "mask": 2, "width": 1},
{"i": 1, "op": "rotl", "dst": 1, "src": 7, "src2": 0, "imm": "0xa731596a", "imm2": "0x4ce406f5", "rot": 23, "bit": 27, "mask": 4, "width": 1},
{"i": 2, "op": "load", "dst": 0, "src": 5, "src2": 5, "imm": "0x4d78cee5", "imm2": "0x7a624dd7", "rot": 16, "bit": 24, "mask": 16, "width": 4},
{"i": 3, "op": "mad", "dst": 5, "src": 4, "src2": 2, "imm": "0x80a8d418", "imm2": "0x3f405868", "rot": 21, "bit": 4, "mask": 8, "width": 1},
{"i": 4, "op": "mul", "dst": 1, "src": 6, "src2": 4, "imm": "0xc4e8867c", "imm2": "0xd2ad8c44", "rot": 26, "bit": 21, "mask": 16, "width": 1},
{"i": 5, "op": "add", "dst": 1, "src": 0, "src2": 6, "imm": "0x9db46598", "imm2": "0x9dd9fb05", "rot": 14, "bit": 6, "mask": 16, "width": 1},
{"i": 6, "op": "shfl", "dst": 1, "src": 7, "src2": 5, "imm": "0xc9049c0f", "imm2": "0x007f6621", "rot": 24, "bit": 19, "mask": 16, "width": 1},
{"i": 7, "op": "mul", "dst": 6, "src": 1, "src2": 7, "imm": "0x073fea86", "imm2": "0x1ed9dff1", "rot": 26, "bit": 24, "mask": 2, "width": 1},
{"i": 8, "op": "mulhi", "dst": 1, "src": 7, "src2": 5, "imm": "0x3faa8f96", "imm2": "0x01445abc", "rot": 26, "bit": 3, "mask": 4, "width": 1},
{"i": 9, "op": "mulhi", "dst": 2, "src": 1, "src2": 1, "imm": "0x97d622e9", "imm2": "0xfd732e57", "rot": 28, "bit": 29, "mask": 1, "width": 1},
{"i": 10, "op": "add", "dst": 0, "src": 4, "src2": 4, "imm": "0xe45fcceb", "imm2": "0xc15822b6", "rot": 15, "bit": 13, "mask": 2, "width": 1},
{"i": 11, "op": "mad", "dst": 5, "src": 1, "src2": 2, "imm": "0x6148c1cc", "imm2": "0xdaa7b1d3", "rot": 3, "bit": 25, "mask": 16, "width": 1},
{"i": 12, "op": "mul", "dst": 4, "src": 7, "src2": 1, "imm": "0x7b0965e5", "imm2": "0x5086e5aa", "rot": 30, "bit": 28, "mask": 16, "width": 1},
{"i": 13, "op": "load", "dst": 0, "src": 5, "src2": 4, "imm": "0x4c87a2ab", "imm2": "0x5db5ba1c", "rot": 22, "bit": 19, "mask": 16, "width": 16},
{"i": 14, "op": "xor", "dst": 3, "src": 4, "src2": 6, "imm": "0xdc246d40", "imm2": "0xa5cfff4a", "rot": 6, "bit": 19, "mask": 16, "width": 1},
{"i": 15, "op": "xor", "dst": 1, "src": 6, "src2": 6, "imm": "0x6d3e113d", "imm2": "0x69e25584", "rot": 12, "bit": 27, "mask": 2, "width": 1},
{"i": 16, "op": "rotr", "dst": 5, "src": 6, "src2": 2, "imm": "0x45569439", "imm2": "0x14d0f916", "rot": 10, "bit": 5, "mask": 16, "width": 1},
{"i": 17, "op": "rotr", "dst": 3, "src": 7, "src2": 1, "imm": "0x412cb31a", "imm2": "0xe0713d9c", "rot": 17, "bit": 0, "mask": 2, "width": 1},
{"i": 18, "op": "shfl", "dst": 1, "src": 4, "src2": 3, "imm": "0x2419b99c", "imm2": "0x9ab3a71e", "rot": 17, "bit": 15, "mask": 16, "width": 1},
{"i": 19, "op": "load", "dst": 5, "src": 6, "src2": 7, "imm": "0xa1f88336", "imm2": "0xca05a80c", "rot": 17, "bit": 22, "mask": 8, "width": 1},
{"i": 20, "op": "rotl", "dst": 6, "src": 7, "src2": 4, "imm": "0x51de29c5", "imm2": "0xfe2d2af0", "rot": 30, "bit": 20, "mask": 1, "width": 1},
{"i": 21, "op": "load", "dst": 5, "src": 2, "src2": 6, "imm": "0x5db413b6", "imm2": "0x3dad8864", "rot": 20, "bit": 23, "mask": 4, "width": 4},
{"i": 22, "op": "xor", "dst": 3, "src": 5, "src2": 0, "imm": "0xdeadb225", "imm2": "0x7397a1f2", "rot": 5, "bit": 3, "mask": 2, "width": 1},
{"i": 23, "op": "add", "dst": 5, "src": 7, "src2": 7, "imm": "0x1d4f8db7", "imm2": "0x950603c6", "rot": 19, "bit": 6, "mask": 1, "width": 1},
{"i": 24, "op": "load", "dst": 3, "src": 4, "src2": 5, "imm": "0x148ee6e2", "imm2": "0xfc0cbfef", "rot": 1, "bit": 23, "mask": 16, "width": 4},
{"i": 25, "op": "load", "dst": 0, "src": 1, "src2": 1, "imm": "0x114e77c3", "imm2": "0x8b1c13f1", "rot": 4, "bit": 0, "mask": 8, "width": 16},
{"i": 26, "op": "add", "dst": 2, "src": 3, "src2": 3, "imm": "0x55db0d92", "imm2": "0x0ae476a4", "rot": 24, "bit": 31, "mask": 4, "width": 1},
{"i": 27, "op": "load", "dst": 5, "src": 6, "src2": 5, "imm": "0xee300382", "imm2": "0x1609cf99", "rot": 8, "bit": 11, "mask": 16, "width": 1},
{"i": 28, "op": "load", "dst": 2, "src": 5, "src2": 2, "imm": "0x96783a44", "imm2": "0x0f090418", "rot": 11, "bit": 24, "mask": 1, "width": 4},
{"i": 29, "op": "xor", "dst": 1, "src": 6, "src2": 7, "imm": "0x6c8d15c2", "imm2": "0x2cde0f35", "rot": 18, "bit": 14, "mask": 4, "width": 1},
{"i": 30, "op": "mulhi", "dst": 7, "src": 4, "src2": 1, "imm": "0xc68ea9de", "imm2": "0xc45d9dfa", "rot": 29, "bit": 14, "mask": 2, "width": 1},
{"i": 31, "op": "rotr", "dst": 6, "src": 3, "src2": 5, "imm": "0x2b816dd1", "imm2": "0xdf13f697", "rot": 17, "bit": 12, "mask": 2, "width": 1},
{"i": 32, "op": "load", "dst": 0, "src": 3, "src2": 3, "imm": "0x6711453d", "imm2": "0x78ae13e9", "rot": 2, "bit": 6, "mask": 4, "width": 1},
{"i": 33, "op": "rotr", "dst": 5, "src": 0, "src2": 3, "imm": "0xe0068514", "imm2": "0xba437440", "rot": 14, "bit": 2, "mask": 2, "width": 1},
{"i": 34, "op": "rotl", "dst": 5, "src": 3, "src2": 7, "imm": "0xdde8ab9a", "imm2": "0x9b3f4073", "rot": 20, "bit": 26, "mask": 1, "width": 1},
{"i": 35, "op": "mulhi", "dst": 0, "src": 4, "src2": 2, "imm": "0x2b47ae8c", "imm2": "0x2617710c", "rot": 30, "bit": 29, "mask": 1, "width": 1},
{"i": 36, "op": "add", "dst": 6, "src": 7, "src2": 0, "imm": "0x5d6e3dc5", "imm2": "0xfe7a0454", "rot": 22, "bit": 18, "mask": 8, "width": 1},
{"i": 37, "op": "load", "dst": 2, "src": 1, "src2": 7, "imm": "0x21116475", "imm2": "0xbe53b7b8", "rot": 21, "bit": 2, "mask": 8, "width": 4},
{"i": 38, "op": "rotl", "dst": 2, "src": 7, "src2": 2, "imm": "0xd76a18c4", "imm2": "0xb7ed0d92", "rot": 19, "bit": 10, "mask": 16, "width": 1},
{"i": 39, "op": "add", "dst": 3, "src": 6, "src2": 3, "imm": "0xe7e241ba", "imm2": "0xc1d4ae24", "rot": 10, "bit": 20, "mask": 16, "width": 1},
{"i": 40, "op": "load", "dst": 4, "src": 7, "src2": 0, "imm": "0xb1006316", "imm2": "0x617eb11a", "rot": 1, "bit": 27, "mask": 1, "width": 4},
{"i": 41, "op": "add", "dst": 3, "src": 1, "src2": 3, "imm": "0xb45cdd60", "imm2": "0x8f9f8556", "rot": 5, "bit": 21, "mask": 16, "width": 1},
{"i": 42, "op": "shfl", "dst": 5, "src": 2, "src2": 1, "imm": "0x8fc745c7", "imm2": "0x98256336", "rot": 16, "bit": 7, "mask": 4, "width": 1},
{"i": 43, "op": "mul", "dst": 0, "src": 1, "src2": 3, "imm": "0xe8aea431", "imm2": "0xfeed34f6", "rot": 30, "bit": 2, "mask": 8, "width": 1},
{"i": 44, "op": "rotr", "dst": 0, "src": 7, "src2": 4, "imm": "0x8f1da3ee", "imm2": "0xa9c20edf", "rot": 19, "bit": 17, "mask": 2, "width": 1},
{"i": 45, "op": "sub", "dst": 5, "src": 3, "src2": 7, "imm": "0x9da4c5e7", "imm2": "0xbcd50b0c", "rot": 7, "bit": 18, "mask": 1, "width": 1},
{"i": 46, "op": "mad", "dst": 2, "src": 7, "src2": 7, "imm": "0x837be930", "imm2": "0x9b62650b", "rot": 5, "bit": 23, "mask": 1, "width": 1},
{"i": 47, "op": "mad", "dst": 6, "src": 3, "src2": 1, "imm": "0x825afaa4", "imm2": "0x0cf9f1f0", "rot": 17, "bit": 9, "mask": 2, "width": 1},
{"i": 48, "op": "mul", "dst": 0, "src": 7, "src2": 2, "imm": "0x4424f910", "imm2": "0xbaeba671", "rot": 23, "bit": 6, "mask": 4, "width": 1},
{"i": 49, "op": "add", "dst": 0, "src": 4, "src2": 7, "imm": "0x3fa0c5cd", "imm2": "0xb9083b6c", "rot": 28, "bit": 1, "mask": 2, "width": 1},
{"i": 50, "op": "add", "dst": 4, "src": 6, "src2": 4, "imm": "0x2d6873e8", "imm2": "0x9eecc778", "rot": 29, "bit": 13, "mask": 16, "width": 1},
{"i": 51, "op": "sub", "dst": 2, "src": 7, "src2": 2, "imm": "0xace9966d", "imm2": "0xe4213c89", "rot": 30, "bit": 18, "mask": 8, "width": 1},
{"i": 52, "op": "rotl", "dst": 6, "src": 7, "src2": 0, "imm": "0x03bc6330", "imm2": "0x32d9aee6", "rot": 6, "bit": 19, "mask": 1, "width": 1},
{"i": 53, "op": "rotr", "dst": 3, "src": 5, "src2": 1, "imm": "0xef7e5b3e", "imm2": "0xb2aea388", "rot": 27, "bit": 31, "mask": 2, "width": 1},
{"i": 54, "op": "load", "dst": 3, "src": 2, "src2": 2, "imm": "0x711b4f5d", "imm2": "0xac8e6837", "rot": 1, "bit": 5, "mask": 1, "width": 4},
{"i": 55, "op": "load", "dst": 7, "src": 5, "src2": 7, "imm": "0xb0f4faf4", "imm2": "0xb13fe736", "rot": 16, "bit": 2, "mask": 4, "width": 4},
{"i": 56, "op": "or", "dst": 2, "src": 6, "src2": 5, "imm": "0x4f416150", "imm2": "0x2a9f59e3", "rot": 31, "bit": 6, "mask": 4, "width": 1},
{"i": 57, "op": "load", "dst": 4, "src": 0, "src2": 0, "imm": "0x54ce0fba", "imm2": "0x48d98570", "rot": 11, "bit": 2, "mask": 4, "width": 1},
{"i": 58, "op": "xor", "dst": 3, "src": 6, "src2": 6, "imm": "0xf34a7cca", "imm2": "0xf345c73d", "rot": 18, "bit": 18, "mask": 16, "width": 1},
{"i": 59, "op": "load", "dst": 0, "src": 6, "src2": 6, "imm": "0x730474e9", "imm2": "0xb90ac73f", "rot": 25, "bit": 31, "mask": 4, "width": 1},
{"i": 60, "op": "add", "dst": 2, "src": 4, "src2": 1, "imm": "0x5052a1c3", "imm2": "0x19c76fb3", "rot": 12, "bit": 3, "mask": 1, "width": 1},
{"i": 61, "op": "load", "dst": 7, "src": 4, "src2": 0, "imm": "0xbecfc16b", "imm2": "0xd2837365", "rot": 21, "bit": 22, "mask": 8, "width": 1},
{"i": 62, "op": "or", "dst": 6, "src": 1, "src2": 3, "imm": "0x7353a546", "imm2": "0xcc33abd9", "rot": 24, "bit": 5, "mask": 4, "width": 1},
{"i": 63, "op": "add", "dst": 5, "src": 1, "src2": 1, "imm": "0x08c757c0", "imm2": "0x535fe3fa", "rot": 21, "bit": 4, "mask": 4, "width": 1}
]
}