igneum/tools/chip-model/rtl/flow/tile.mk
igneum-labs 23fcb5dc62 chip-model: the shadow-k floor lane's RTL, testbenches and ORFS flow (ASAP7) for every class v6 mixer family
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 9009ed0f4 (bfccc26ed4) for the box mirror master
2026-10-08 14:32:43 +00:00

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Makefile

# ORFS design config for the tile shadow-core family (top tile8), ASAP7.
export PLATFORM = asap7
export DESIGN_NAME = tile8
export DESIGN_NICKNAME = tile
export VERILOG_FILES = /work/rtl/tile8.v
export VERILOG_INCLUDE_DIRS = /work/rtl
export SDC_FILE = /work/flow/tile.sdc
export CORE_UTILIZATION = 40
export CORE_ASPECT_RATIO = 1
export CORE_MARGIN = 0.5
export PLACE_DENSITY = 0.55
export CORNER = TC
export SKIP_LAST_GASP = 1
export WORK_HOME = /work/out/tile